from nmigen.hdl.dsl import Module
from nmutil.formaltest import FHDLTestCase
from nmigen_gf.reference.clmul import clmul
-from nmutil.clmul import BitwiseXorReduce, CLMulAdd
+from nmigen_gf.hdl.clmul import BitwiseXorReduce, CLMulAdd
from nmigen.sim import Delay
from nmutil.sim_util import do_sim, hash_256