fix after move

diff --git a/src/nmigen_gf/hdl/test/test_clmul.py b/src/nmigen_gf/hdl/test/test_clmul.py
index ed39fedf32a5b595997e44ea9dbb8fccd5898186..dc0e6fd149758416762ff668a25b3e9067562c97 100644 (file)
--- a/src/nmigen_gf/hdl/test/test_clmul.py
+++ b/src/nmigen_gf/hdl/test/test_clmul.py
@@ -12,7 +12,7 @@ from nmigen.hdl.ast import (AnyConst, Assert, Signal, Const, unsigned, signed,
 from nmigen.hdl.dsl import Module
 from nmutil.formaltest import FHDLTestCase
 from nmigen_gf.reference.clmul import clmul
-from nmutil.clmul import BitwiseXorReduce, CLMulAdd
+from nmigen_gf.hdl.clmul import BitwiseXorReduce, CLMulAdd
 from nmigen.sim import Delay
 from nmutil.sim_util import do_sim, hash_256