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Wire up missing CRG / DDR3 clock control / reset signals
[gram.git]
/
examples
/
ecp5_crg.py
2022-04-09
Raptor Engineering...
Wire up missing CRG / DDR3 clock control / reset signals
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2022-04-07
Raptor Engineering...
Add initial support for external DRAM init on the Rapto...
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