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add vss/vdd as pins, gets the net into the VST
[soclayout.git] / experiments10_verilog / pll.py
2021-06-05 Luke Kenneth Casso... add vss/vdd as pins, gets the net into the VST blob | commitdiff | raw
2021-06-05 Luke Kenneth Casso... set power type in fake pll vdd/vss blob | commitdiff | raw | diff to current
2021-06-05 Luke Kenneth Casso... whoops, fake pll/mem need vss/vdd blob | commitdiff | raw | diff to current
2021-06-05 Luke Kenneth Casso... add dummy (fake) PLL to experiments10_verilog for testing blob | commitdiff | raw | diff to current