rename cell to "real_pll" to avoid conflict with cell also named "pll"
[soclayout.git] / experiments9 /
2021-05-24 Luke Kenneth Casso... rename cell to "real_pll" to avoid conflict with cell...
2021-05-24 Luke Kenneth Casso... add dummy/fake/ghost PLL blackbox cell
2021-05-22 Luke Kenneth Casso... rename PLL pad names
2021-05-22 Luke Kenneth Casso... correct PLL names
2021-05-22 Luke Kenneth Casso... re-add 4k sram
2021-05-22 Luke Kenneth Casso... annoying rename of pll analog pin
2021-05-22 Luke Kenneth Casso... manually rename ls180sram4k module to ls180
2021-05-22 Luke Kenneth Casso... update PLL to use submodule Instance
2021-04-30 Luke Kenneth Casso... do an SRAM search by looking for matching along the...
2021-04-30 Luke Kenneth Casso... 4k sram build
2021-04-30 Luke Kenneth Casso... use "make view" not "make vst"
2021-04-30 Luke Kenneth Casso... add fake LibreSOCMem library to freepdk_c4m45
2021-04-30 Luke Kenneth Casso... add symlink to "fake" LibreSOCMem
2021-04-30 Luke Kenneth Casso... enabling experiments9 new LibreSOCMem fake blackbox...
2021-04-30 Luke Kenneth Casso... using renamed (single) spblock_512w64b8w
2021-04-30 Luke Kenneth Casso... using new single spblock_512xxx in experiments9
2021-04-30 Luke Kenneth Casso... add complete series of pins onto fake SRAM
2021-04-28 Luke Kenneth Casso... first experiment creating a LibreSOCMem library with...
2021-04-28 Luke Kenneth Casso... create function which pre-creates the blackbox cells
2021-04-28 Luke Kenneth Casso... name everything back to spblock_512w64b8w now that...
2021-04-28 Luke Kenneth Casso... rename spblock modules to just straight spblock_512w64b...
2021-04-28 Luke Kenneth Casso... also add createSRAMblocks to freepdk_c4m45
2021-04-28 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-04-28 Jean-Paul ChaputManagement of SRAMs block at Coriolis devel.
2021-04-28 Luke Kenneth Casso... add vbe spblock models to non_generated and build scripts
2021-04-28 Luke Kenneth Casso... shrinking regfile sizes some more
2021-04-27 Luke Kenneth Casso... add blackbox attribute to spblock512*.v
2021-04-27 Luke Kenneth Casso... also add blackboxes spblock512* etc.
2021-04-27 Luke Kenneth Casso... add copying over of spblock*.v and pll.v to build scripts
2021-04-25 Jean-Paul ChaputCorrect setup for experiment9/freepdk_c4m45, restrict...
2021-04-24 Luke Kenneth Casso... cleanup mksyms.sh to include FreePDK_C4M45
2021-04-24 Luke Kenneth Casso... add export of PDKMASTER_TOP to experiments9/freepdk_c4m45
2021-04-24 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-04-24 Jean-Paul ChaputForgot to update experiments9 doDesign file for FreePDK 45.
2021-04-24 Jean-Paul ChaputKeep in synch with the latest Coriolis. SRAM models...
2021-04-22 Luke Kenneth Casso... make placement of SRAMs optional, and PLL as well,...
2021-04-20 Luke Kenneth Casso... manually comment out pll and sdcard pins
2021-04-19 Staf VerhaegenTop layer -> metal6
2021-04-19 Staf Verhaegenexperiments9/freepdk_c4m45: Reduce core size.
2021-04-18 Luke Kenneth Casso... argh, found the blackbox problem: yosys is "doing the...
2021-04-18 Luke Kenneth Casso... try renaming spblock without the underscore
2021-04-18 Luke Kenneth Casso... try changing layout of blackbox spblock_512w64b8w
2021-04-18 Luke Kenneth Casso... experimenting with blackboxes
2021-04-18 Luke Kenneth Casso... rename spblock_512w64b8w, and vco_test_ana for pll
2021-04-18 Luke Kenneth Casso... rename blackboxes to lowercase, spblock_512w64b8w, pll
2021-04-18 Luke Kenneth Casso... update ls180 sram4k
2021-04-18 Luke Kenneth Casso... add yosys BLACKBOX SPBlock_512W64B8W - still blif2vst...
2021-04-18 Luke Kenneth Casso... must use VST_FLAGS uniquify uppercase
2021-04-18 Luke Kenneth Casso... sort out adding SPBlock_512 SRAM verilog to ls180
2021-04-18 Luke Kenneth Casso... update tsmc_018 4k build script
2021-04-18 Luke Kenneth Casso... use correct arguments to litex build to create 4k srams...
2021-04-18 Luke Kenneth Casso... rename ls180sram4k to ls180
2021-04-18 Luke Kenneth Casso... add full core variant including 4k sram of ls180
2021-04-18 Luke Kenneth Casso... update libresoc.v, c4m-jtag fsm was renamed
2021-04-18 Luke Kenneth Casso... update libresoc.v, c4m-jtag fsm was renamed
2021-04-12 Luke Kenneth Casso... update PLL signal output names
2021-04-12 Staf VerhaegendoDesign.py: Disable SRAM placement
2021-04-12 Staf VerhaegenReduce core size.
2021-04-12 Luke Kenneth Casso... another attempt to get 100% completed route
2021-04-11 Luke Kenneth Casso... good grief, increasing ls180 core size to 70,000, 100...
2021-04-11 Luke Kenneth Casso... increase core size to see if global routing can be...
2021-04-11 Luke Kenneth Casso... whitespace cleanup
2021-04-11 Luke Kenneth Casso... use auto-generated pinmux ioPadsSpecs
2021-04-11 Luke Kenneth Casso... use verilog version of ls180 in FreePDK_c4m45
2021-04-11 Luke Kenneth Casso... crank up the numbers (again)
2021-04-11 Staf VerhaegenWip of P&R of ls180 with C4M FreePDK45.
2021-04-11 Staf Verhaegenexperiments9: Ignore pinmux generated files.
2021-04-11 Staf Verhaegenmksym.sh: Check exitence of alliance-check-toolkit
2021-04-11 Luke Kenneth Casso... crank up the numbers to see if routing completion can...
2021-04-11 Luke Kenneth Casso... increase katana tracks reserved
2021-04-10 Luke Kenneth Casso... use verilog for ls180 instead of ilang
2021-04-10 Luke Kenneth Casso... make VST names unique, for GHDL to cope
2021-04-09 Luke Kenneth Casso... whitespace
2021-04-09 Luke Kenneth Casso... whitespace cleanup
2021-04-09 Luke Kenneth Casso... rename design of experiments10 to match ls180 chip...
2021-04-01 Luke Kenneth Casso... update / refresh full core DFF
2021-04-01 Luke Kenneth Casso... update / refresh full core DFF
2021-03-30 Luke Kenneth Casso... update 4k SRAM ls180.il
2021-03-30 Luke Kenneth Casso... add yosys version number
2021-03-29 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-29 Jean-Paul ChaputAdd a placeholder for the PLL in the doDesign.py for...
2021-03-29 Luke Kenneth Casso... Revert "enable high fanout in ls180 experiment9 doDesig...
2021-03-29 Luke Kenneth Casso... enable high fanout in ls180 experiment9 doDesign.py
2021-03-29 Luke Kenneth Casso... aaagh found bug in litex setup, 64 bit WB bus was truncated
2021-03-28 Luke Kenneth Casso... reduce SPR regfile size considerably
2021-03-28 Luke Kenneth Casso... reduce INT and FAST regfile sizes by sharing ports
2021-03-27 Luke Kenneth Casso... add missing floorplan function call
2021-03-27 Luke Kenneth Casso... hooray, corrected pinouts
2021-03-27 Luke Kenneth Casso... really weird error "unsupported direction for eint...
2021-03-23 Jean-Paul ChaputUodated doDesign for the latest ls180 (sram variant).
2021-03-22 Luke Kenneth Casso... increase DFF RAM size slightly
2021-03-22 Luke Kenneth Casso... add very small DFF srams variant
2021-03-22 Luke Kenneth Casso... create small dff with 4x 4k SRAMs
2021-03-22 Luke Kenneth Casso... ls180.il update
2021-03-22 Luke Kenneth Casso... argh pinmux generating bi-directional SDR DM when it...
2021-03-18 Luke Kenneth Casso... update ls180.il
2021-03-16 Luke Kenneth Casso... update ls180.il 4ksram with correct sdram connections
2021-03-16 Jean-Paul ChaputAdd experiment9/symbolic to test the multiple drivers...
2021-03-14 Jean-Paul ChaputMerge branch 'master' of ssh://libre-riscv.org:922...
2021-03-14 Jean-Paul ChaputAdjusted doDesign.py scripts to use Chip.doChipFloorplan().
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