Backport litedram 05ed5bf59d31029d3f91c5a348cdd539a150631b
[gram.git] / gram / common.py
2022-04-07 Raptor Engineering... Backport litedram 05ed5bf59d31029d3f91c5a348cdd539a150631b
2022-03-17 Luke Kenneth Casso... initialise bitslip with a specific value rather than...
2022-02-24 Luke Kenneth Casso... add a BitSlip module
2020-07-29 Jean THOMASExpose data_width
2020-07-28 Jean THOMASRemove classes for read and write ports, add parameter...
2020-07-28 Jean THOMASRemove unused set_rdimm
2020-07-24 Jean THOMASFix tXXDController (was overflowing)
2020-07-20 Jean THOMASRemove DQSPattern
2020-07-20 Jean THOMASFix code styling
2020-07-20 Jean THOMASAdding test for tXXDController
2020-07-20 Jean THOMASSimplify parameters code for DQSPattern
2020-07-20 Jean THOMASRemove unused code (PHYPadsCombiner/PHYPadsReducer)
2020-07-09 Jean THOMASRemove unused BitFlip
2020-06-12 Jean THOMASFix default clock domain for gramNativePort
2020-06-11 Jean THOMASRemove unused legacy attributes (fixes #3)
2020-06-11 Jean THOMASAdd no_retiming attribute
2020-06-09 Jean THOMASRun autopep8
2020-06-08 Jean THOMASRename LiteDRAM to gram
2020-06-08 Jean THOMASAdd copyright
2020-06-04 Jean THOMASCorrect nMigen transition bugs
2020-06-03 Jean THOMASInitial commit