git.libre-soc.org Git - gram.git/history - gram/simulation/icarusecpix5platform.py

2022-03-10	Luke Kenneth Casso...	tidyup on gramWishbone class, add comments	blob \| commitdiff \| raw
2022-03-01	Luke Kenneth Casso...	fix up simulation to be more like VERSA_ECP5	blob \| commitdiff \| raw \| diff to current
2022-02-25	Luke Kenneth Casso...	allow DDR3 reset (rst) signal to be controlled by DFI...	blob \| commitdiff \| raw \| diff to current
2020-08-04	Jean THOMAS	Fix simulation to support diff pairs	blob \| commitdiff \| raw \| diff to current
2020-07-28	Jean THOMAS	Remove unused resources	blob \| commitdiff \| raw \| diff to current
2020-07-23	Jean THOMAS	Fix platform code for simulation	blob \| commitdiff \| raw \| diff to current
2020-07-20	Jean THOMAS	Use PinsN when possible (fixes #27)	blob \| commitdiff \| raw \| diff to current
2020-07-06	Jean THOMAS	Rename from cke to clk_en	blob \| commitdiff \| raw \| diff to current
2020-07-01	Jean THOMAS	Fix Iverilog simulation	blob \| commitdiff \| raw \| diff to current
2020-07-01	Jean THOMAS	Generate ilang file	blob \| commitdiff \| raw \| diff to current
2020-06-26	Jean THOMAS	Add DDRSoC simulation	blob \| commitdiff \| raw \| diff to current