git.libre-soc.org Git - gram.git/history - gram/simulation/simsoc.py

[gram.git] / gram / simulation / simsoc.py

2022-03-01	Luke Kenneth Casso...	fix up simulation to be more like VERSA_ECP5	blob \| commitdiff \| raw
2022-02-25	Luke Kenneth Casso...	allow DDR3 reset (rst) signal to be controlled by DFI...	blob \| commitdiff \| raw \| diff to current
2020-07-27	Jean THOMAS	Wire directly to the Wishbone bus, making simulations...	blob \| commitdiff \| raw \| diff to current
2020-07-20	Jean THOMAS	Use PinsN when possible (fixes #27)	blob \| commitdiff \| raw \| diff to current
2020-07-17	Jean THOMAS	Use XDR for ba pins	blob \| commitdiff \| raw \| diff to current
2020-07-17	Jean THOMAS	Use XDR for address pins	blob \| commitdiff \| raw \| diff to current
2020-07-17	Jean THOMAS	Use nMigen's XDR for DDR clk	blob \| commitdiff \| raw \| diff to current
2020-07-15	Jean THOMAS	Increase UART bridge speed in simulation, decrease...	blob \| commitdiff \| raw \| diff to current
2020-07-13	Jean THOMAS	Fix gearing and UART speed	blob \| commitdiff \| raw \| diff to current
2020-07-03	Jean THOMAS	Externalize CRG into its own file	blob \| commitdiff \| raw \| diff to current
2020-07-01	Jean THOMAS	Fix Iverilog simulation	blob \| commitdiff \| raw \| diff to current
2020-06-30	Jean THOMAS	Build nMigen gateware in a specific folder	blob \| commitdiff \| raw \| diff to current
2020-06-30	Jean THOMAS	Remove LED code in CRG	blob \| commitdiff \| raw \| diff to current
2020-06-30	Jean THOMAS	Remove Minerva dependency	blob \| commitdiff \| raw \| diff to current
2020-06-29	Jean THOMAS	Define PLL's PHASELOADREG input	blob \| commitdiff \| raw \| diff to current
2020-06-29	Jean THOMAS	Fix CRG, revert to resetful sync domain	blob \| commitdiff \| raw \| diff to current
2020-06-26	Jean THOMAS	Add DDRSoC simulation	blob \| commitdiff \| raw \| diff to current

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