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[gram.git] / gram / simulation / simsoctb.v

2020-08-04	Jean THOMAS	Fix simulation to support diff pairs	blob \| commitdiff \| raw
2020-07-30	Jean THOMAS	Set default value for dram_rst	blob \| commitdiff \| raw \| diff to current
2020-07-28	Jean THOMAS	Make R/W tests more intense	blob \| commitdiff \| raw \| diff to current
2020-07-28	Jean THOMAS	Add speedtest_write task	blob \| commitdiff \| raw \| diff to current
2020-07-28	Jean THOMAS	Remove simticks	blob \| commitdiff \| raw \| diff to current
2020-07-28	Jean THOMAS	Add speedtest_read task in testbench	blob \| commitdiff \| raw \| diff to current
2020-07-27	Jean THOMAS	Remove reference to UART	blob \| commitdiff \| raw \| diff to current
2020-07-27	Jean THOMAS	Wire directly to the Wishbone bus, making simulations...	blob \| commitdiff \| raw \| diff to current
2020-07-21	Jean THOMAS	Use 0x00BA0BAB instead of 0x12345678 for better readability	blob \| commitdiff \| raw \| diff to current
2020-07-20	Jean THOMAS	Use PinsN when possible (fixes #27)	blob \| commitdiff \| raw \| diff to current
2020-07-17	Jean THOMAS	Reduce delay between wishbone_write	blob \| commitdiff \| raw \| diff to current
2020-07-17	Jean THOMAS	Fix DQS_N errors	blob \| commitdiff \| raw \| diff to current
2020-07-17	Jean THOMAS	Add more read transactions, add checks, ASAP	blob \| commitdiff \| raw \| diff to current
2020-07-16	Jean THOMAS	Use assertions in simsoc testbench	blob \| commitdiff \| raw \| diff to current
2020-07-16	Jean THOMAS	Add logging and delays to the simulation to make it...	blob \| commitdiff \| raw \| diff to current
2020-07-15	Jean THOMAS	Make gram simulations faster	blob \| commitdiff \| raw \| diff to current
2020-07-15	Jean THOMAS	Increase UART bridge speed in simulation, decrease...	blob \| commitdiff \| raw \| diff to current
2020-07-15	Jean THOMAS	Log RAM signals	blob \| commitdiff \| raw \| diff to current
2020-07-13	Jean THOMAS	Fix gearing and UART speed	blob \| commitdiff \| raw \| diff to current
2020-07-10	Jean THOMAS	Fix timings in simulation to prevent tDLLK errors	blob \| commitdiff \| raw \| diff to current
2020-07-10	Jean THOMAS	Add POR start/end logging in simsoc testbench	blob \| commitdiff \| raw \| diff to current
2020-07-08	Jean THOMAS	Fix clock input	blob \| commitdiff \| raw \| diff to current
2020-07-08	Jean THOMAS	cke => clk_en in SoC testbench	blob \| commitdiff \| raw \| diff to current
2020-07-06	Jean THOMAS	Add write transactions in the simulation testbench	blob \| commitdiff \| raw \| diff to current
2020-07-02	Jean THOMAS	Add missing command issue strobe for ZQ calibration	blob \| commitdiff \| raw \| diff to current
2020-07-02	Jean THOMAS	Fix register addresses, add missing command_issue strobe	blob \| commitdiff \| raw \| diff to current
2020-07-01	Jean THOMAS	Fix merge	blob \| commitdiff \| raw \| diff to current
2020-07-01	Jean THOMAS	Rework indentation and add Wishbone tests	blob \| commitdiff \| raw \| diff to current
2020-07-01	Jean THOMAS	Add Wishbone interaction code	blob \| commitdiff \| raw \| diff to current
2020-07-01	Jean THOMAS	Add Wishbone interaction code	blob \| commitdiff \| raw \| diff to current
2020-06-29	Jean THOMAS	Define simulation time as a parameter	blob \| commitdiff \| raw \| diff to current
2020-06-29	Jean THOMAS	Set DRAM's CK_N to low	blob \| commitdiff \| raw \| diff to current
2020-06-29	Jean THOMAS	Set UART RX to 1'b1	blob \| commitdiff \| raw \| diff to current
2020-06-26	Jean THOMAS	Add testbench for SoC simulation	blob \| commitdiff \| raw \| diff to current

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