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fix up simulation to be more like VERSA_ECP5
[gram.git]
/
gram
/
simulation
/
simsoctb.v
2022-03-01
Luke Kenneth Casso...
fix up simulation to be more like VERSA_ECP5
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2022-02-25
Luke Kenneth Casso...
allow DDR3 reset (rst) signal to be controlled by DFI...
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2020-08-04
Jean THOMAS
Fix simulation to support diff pairs
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2020-07-30
Jean THOMAS
Set default value for dram_rst
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2020-07-28
Jean THOMAS
Make R/W tests more intense
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2020-07-28
Jean THOMAS
Add speedtest_write task
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2020-07-28
Jean THOMAS
Remove simticks
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2020-07-28
Jean THOMAS
Add speedtest_read task in testbench
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2020-07-27
Jean THOMAS
Remove reference to UART
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2020-07-27
Jean THOMAS
Wire directly to the Wishbone bus, making simulations...
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2020-07-21
Jean THOMAS
Use 0x00BA0BAB instead of 0x12345678 for better readability
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2020-07-20
Jean THOMAS
Use PinsN when possible (fixes #27)
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2020-07-17
Jean THOMAS
Reduce delay between wishbone_write
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2020-07-17
Jean THOMAS
Fix DQS_N errors
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2020-07-17
Jean THOMAS
Add more read transactions, add checks, ASAP
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2020-07-16
Jean THOMAS
Use assertions in simsoc testbench
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2020-07-16
Jean THOMAS
Add logging and delays to the simulation to make it...
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2020-07-15
Jean THOMAS
Make gram simulations faster
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2020-07-15
Jean THOMAS
Increase UART bridge speed in simulation, decrease...
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2020-07-15
Jean THOMAS
Log RAM signals
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2020-07-13
Jean THOMAS
Fix gearing and UART speed
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2020-07-10
Jean THOMAS
Fix timings in simulation to prevent tDLLK errors
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2020-07-10
Jean THOMAS
Add POR start/end logging in simsoc testbench
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2020-07-08
Jean THOMAS
Fix clock input
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2020-07-08
Jean THOMAS
cke => clk_en in SoC testbench
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2020-07-06
Jean THOMAS
Add write transactions in the simulation testbench
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2020-07-02
Jean THOMAS
Add missing command issue strobe for ZQ calibration
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2020-07-02
Jean THOMAS
Fix register addresses, add missing command_issue strobe
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2020-07-01
Jean THOMAS
Fix merge
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2020-07-01
Jean THOMAS
Rework indentation and add Wishbone tests
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2020-07-01
Jean THOMAS
Add Wishbone interaction code
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2020-07-01
Jean THOMAS
Add Wishbone interaction code
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2020-06-29
Jean THOMAS
Define simulation time as a parameter
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2020-06-29
Jean THOMAS
Set DRAM's CK_N to low
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2020-06-29
Jean THOMAS
Set UART RX to 1'b1
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2020-06-26
Jean THOMAS
Add testbench for SoC simulation
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