Translate put_z verilog case into nmigen
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
2019-02-14 Aleksandar KostovicTranslate put_z verilog case into nmigen
2019-02-14 Luke Kenneth Casso... add and use is_overflowed function
2019-02-14 Luke Kenneth Casso... cleanup
2019-02-14 Luke Kenneth Casso... document guard/round/sticky and tot
2019-02-14 Aleksandar KostovicTranslate case from verilog to nmigen
2019-02-14 Luke Kenneth Casso... add code comments
2019-02-14 Luke Kenneth Casso... add set-to-zero function
2019-02-14 Luke Kenneth Casso... fix bug in nan/inf, exp-bias needed subtracting
2019-02-14 Luke Kenneth Casso... add FPNum comment
2019-02-14 Luke Kenneth Casso... add comments for aleksander
2019-02-14 Luke Kenneth Casso... add comments for aleksander
2019-02-14 Luke Kenneth Casso... use negative slice (now works)
2019-02-14 Luke Kenneth Casso... remove a_s/b_s/z_s
2019-02-14 Luke Kenneth Casso... move align down-shift to separate function
2019-02-14 Luke Kenneth Casso... move +127 for exponent bias into FPNum.create
2019-02-14 Luke Kenneth Casso... remove unneeded code
2019-02-14 Luke Kenneth Casso... comments
2019-02-14 Luke Kenneth Casso... add zero, nan and inf checks
2019-02-14 Luke Kenneth Casso... create and use decode function
2019-02-14 Luke Kenneth Casso... move create, inf and nan to FPNum class
2019-02-14 Luke Kenneth Casso... create FPNum class
2019-02-14 Luke Kenneth Casso... add rounding stage
2019-02-14 Luke Kenneth Casso... add comments
2019-02-14 Luke Kenneth Casso... add normalise_1 stage
2019-02-14 Luke Kenneth Casso... add NaN and INF functions
2019-02-14 Aleksandar KostovicMerge branch 'master' of ssh://libre-riscv.org:922...
2019-02-14 Aleksandar KostovicTurned the normalise_2 verilog state into nmigen
2019-02-14 Luke Kenneth Casso... use function "create_z" which... well... creates a...
2019-02-14 Luke Kenneth Casso... add in comments on add 2nd stage
2019-02-14 Luke Kenneth Casso... off-by-one in slices
2019-02-14 Aleksandar KostovicMerge branch 'master' of ssh://libre-riscv.org:922...
2019-02-14 Aleksandar KostovicTurned the add_1 verilog state into nmigen
2019-02-14 Luke Kenneth Casso... corrections on compile
2019-02-14 Luke Kenneth Casso... add align phase
2019-02-14 Luke Kenneth Casso... whoops accidentally indented too far
2019-02-14 Luke Kenneth Casso... add code comments
2019-02-14 Luke Kenneth Casso... reformat / indent add_0 stage
2019-02-14 Aleksandar KostovicTurned the add_0 verilog state into nmigen
2019-02-14 Luke Kenneth Casso... add zero and denormalised checks
2019-02-14 Luke Kenneth Casso... add special case, b when a is zero
2019-02-14 Luke Kenneth Casso... add b inf special case
2019-02-14 Luke Kenneth Casso... cleanup and comments
2019-02-14 Luke Kenneth Casso... add inf special case
2019-02-14 Luke Kenneth Casso... whitespace (indent)
2019-02-14 Luke Kenneth Casso... add first of special_cases
2019-02-14 Luke Kenneth Casso... invert Cat order, use 3 zeros (3 bits)
2019-02-14 Luke Kenneth Casso... spelling correction
2019-02-14 Luke Kenneth Casso... corrected syntax for unpack block
2019-02-13 Aleksandar KostovicReplicated unpack part of always block into nmigen
2019-02-13 Luke Kenneth Casso... add experiment