ls2.git
2 years agoEnable DDR3 using a 50MHz clock on Versa 85
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:33:18 +0000 (16:33 -0500)]
Enable DDR3 using a 50MHz clock on Versa 85

2 years agoMove simulation HyperRAM pins off of DDR3 pins
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:32:53 +0000 (16:32 -0500)]
Move simulation HyperRAM pins off of DDR3 pins

2 years agoFix DRAM simulation commands
Raptor Engineering Development Team [Thu, 7 Apr 2022 21:32:18 +0000 (16:32 -0500)]
Fix DRAM simulation commands

2 years agoadd QSPI support to arty_a7
Luke Kenneth Casson Leighton [Wed, 6 Apr 2022 11:28:03 +0000 (12:28 +0100)]
add QSPI support to arty_a7

2 years agoallow setting individual directions on QSPI dq0-dq3
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 19:14:10 +0000 (20:14 +0100)]
allow setting individual directions on QSPI dq0-dq3

2 years agowrite out firmware to correct location,
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 17:14:46 +0000 (18:14 +0100)]
write out firmware to correct location,
adapt to 64/32 bit output

2 years agosigh put firmware.hex qspi file in correct place
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 17:09:26 +0000 (18:09 +0100)]
sigh put firmware.hex qspi file in correct place

2 years agoincrease power-on-delay for icarus sim to allow reset to occur
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 17:08:59 +0000 (18:08 +0100)]
increase power-on-delay for icarus sim to allow reset to occur

2 years agore-enable build of firmware in sim
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 16:25:44 +0000 (17:25 +0100)]
re-enable build of firmware in sim

2 years agodisable ethmac for now, pass firmware.hex to cypress qspi model
Luke Kenneth Casson Leighton [Mon, 4 Apr 2022 16:11:46 +0000 (17:11 +0100)]
disable ethmac for now, pass firmware.hex to cypress qspi model

2 years agoredo start address of firmware so it can be specified -DBOOT_INIT_BASE
Luke Kenneth Casson Leighton [Sun, 3 Apr 2022 10:23:46 +0000 (11:23 +0100)]
redo start address of firmware so it can be specified -DBOOT_INIT_BASE

2 years agoFix SPI device simulation model MISO/MOSI wiring
Raptor Engineering Development Team [Mon, 4 Apr 2022 16:06:51 +0000 (11:06 -0500)]
Fix SPI device simulation model MISO/MOSI wiring

2 years agoAdd 10/100 MAC pins for Versa boards and enable MAC
Raptor Engineering Development Team [Sat, 2 Apr 2022 21:53:56 +0000 (16:53 -0500)]
Add 10/100 MAC pins for Versa boards and enable MAC

Tested to not interfere with main SoC in simulation,
not tested further at this point.

2 years agoreduce number of params obtained on QSPI for icarus sim
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 13:42:53 +0000 (14:42 +0100)]
reduce number of params obtained on QSPI for icarus sim

2 years agogot icarus verilog model of QSPI working and it returns the same FFFFFFF
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 13:31:08 +0000 (14:31 +0100)]
got icarus verilog model of QSPI working and it returns the same FFFFFFF

2 years agowhitespace cleanup
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 09:02:39 +0000 (10:02 +0100)]
whitespace cleanup

2 years agoFix Tercel QSPI master connections
Raptor Engineering Development Team [Thu, 31 Mar 2022 07:39:31 +0000 (02:39 -0500)]
Fix Tercel QSPI master connections

Tested to work on Raptor Versa 85 custom board
in both word and byte mode.

2 years agoremove {err} feature from Tercel
Luke Kenneth Casson Leighton [Thu, 31 Mar 2022 01:31:37 +0000 (02:31 +0100)]
remove {err} feature from Tercel

2 years agoadd err wishbone feature to Tercel
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:43:58 +0000 (20:43 +0100)]
add err wishbone feature to Tercel

2 years agoadd config-dump from SPI
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:43:44 +0000 (20:43 +0100)]
add config-dump from SPI

2 years agoremove clk from spi_flash,
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 19:40:27 +0000 (20:40 +0100)]
remove clk from spi_flash,
change cs_n to cs,
de-bork WB access with stall=cyc&~ack thing

2 years agoadd qspi module to arty_a7
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:45:51 +0000 (13:45 +0100)]
add qspi module to arty_a7

2 years agoquick-and-dirty QSPI read test
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:45:32 +0000 (13:45 +0100)]
quick-and-dirty QSPI read test

2 years agouse nmigen_boards naming conventions for SPIFlash
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 12:32:35 +0000 (13:32 +0100)]
use nmigen_boards naming conventions for SPIFlash

2 years agoupdate comments, link/setup of peripherals
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 11:52:11 +0000 (12:52 +0100)]
update comments, link/setup of peripherals
(all done manually at the moment, TODO a dev-env-setup)

2 years agoadd TODO comments about using platform.add_resources
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 11:46:57 +0000 (12:46 +0100)]
add TODO comments about using platform.add_resources

2 years agowhitespace cleanup, 80 char limit
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 11:00:54 +0000 (12:00 +0100)]
whitespace cleanup, 80 char limit

2 years agoadd patch for n25q to fix model using fork/join, should be begin/end
Luke Kenneth Casson Leighton [Tue, 29 Mar 2022 10:58:32 +0000 (11:58 +0100)]
add patch for n25q to fix model using fork/join, should be begin/end

2 years agoAdd initial integration for OpenCores 10/100 Ethernet MAC
Raptor Engineering Development Team [Tue, 29 Mar 2022 01:11:43 +0000 (20:11 -0500)]
Add initial integration for OpenCores 10/100 Ethernet MAC

2 years agoFix instructions in comment
Raptor Engineering Development Team [Mon, 28 Mar 2022 15:58:23 +0000 (10:58 -0500)]
Fix instructions in comment

2 years agoquick memory test increasing by power-2 each time shows all 32 mbytes of
Luke Kenneth Casson Leighton [Mon, 28 Mar 2022 14:16:45 +0000 (15:16 +0100)]
quick memory test increasing by power-2 each time shows all 32 mbytes of
hyperram ICs are accessible

2 years agoset reset from ResetSignal not straight to 1 for HyperRAM
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 15:32:15 +0000 (16:32 +0100)]
set reset from ResetSignal not straight to 1 for HyperRAM
put correct IOPad names into HyperRAMResource for arty a7

2 years agotry latency of 7 for winbond hyperram
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 12:21:48 +0000 (13:21 +0100)]
try latency of 7 for winbond hyperram

2 years agoadd link to Winbond HyperRAM model
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 12:21:25 +0000 (13:21 +0100)]
add link to Winbond HyperRAM model

2 years agoset upper CSns on HyperRAM to zero and set reset_n HI
Luke Kenneth Casson Leighton [Sun, 27 Mar 2022 11:07:50 +0000 (12:07 +0100)]
set upper CSns on HyperRAM to zero and set reset_n HI
fix CSn pin-pad names

2 years agoadd clock output on hyperram sim
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:40:47 +0000 (22:40 +0000)]
add clock output on hyperram sim

2 years agoadd all 4 CSn lines for Quad HyperRAM PMOD
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:40:33 +0000 (22:40 +0000)]
add all 4 CSn lines for Quad HyperRAM PMOD

2 years agogrr
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:18:15 +0000 (22:18 +0000)]
grr

2 years agoreduce power-on-delay bits to 2 for icarus sim ecp5
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 22:16:27 +0000 (22:16 +0000)]
reduce power-on-delay bits to 2 for icarus sim ecp5

2 years agoremove switches from hyperram iverilog test
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:49:14 +0000 (21:49 +0000)]
remove switches from hyperram iverilog test

2 years agoremove unneeded model variable
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:39:58 +0000 (21:39 +0000)]
remove unneeded model variable

2 years agoadd missing ECP5 model OBZ.v and rename testbench
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:36:59 +0000 (21:36 +0000)]
add missing ECP5 model OBZ.v and rename testbench

2 years agosort out platform IO pads for iverilog hyperram sim
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 21:21:48 +0000 (21:21 +0000)]
sort out platform IO pads for iverilog hyperram sim

2 years agoadd hyperram iverilog runner including s27kl0641.v model
Luke Kenneth Casson Leighton [Sat, 26 Mar 2022 20:58:45 +0000 (20:58 +0000)]
add hyperram iverilog runner including s27kl0641.v model

2 years agorename ECP5 CRG, move source, remove duplicate version
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 14:55:03 +0000 (14:55 +0000)]
rename ECP5 CRG, move source, remove duplicate version

2 years agoup arty a7 frequency to 40 mhz
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 14:53:14 +0000 (14:53 +0000)]
up arty a7 frequency to 40 mhz

2 years agoincrease time for power-on-delay to 2^25 in ECP5
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 14:53:01 +0000 (14:53 +0000)]
increase time for power-on-delay to 2^25 in ECP5

2 years agoloop-test on hyperram read/write which needs carriage-return to activate
Luke Kenneth Casson Leighton [Fri, 25 Mar 2022 14:50:22 +0000 (14:50 +0000)]
loop-test on hyperram read/write which needs carriage-return to activate

2 years agoincrease delay on ECP5 ulx3s
Luke Kenneth Casson Leighton [Thu, 24 Mar 2022 22:13:13 +0000 (22:13 +0000)]
increase delay on ECP5 ulx3s

2 years agocheck ulx3s, add CRG support for ulx3s
Luke Kenneth Casson Leighton [Thu, 24 Mar 2022 20:35:46 +0000 (20:35 +0000)]
check ulx3s, add CRG support for ulx3s

2 years agoestablish power-on reset stabilisation for Arty A7 and ECP5
Luke Kenneth Casson Leighton [Thu, 24 Mar 2022 13:28:12 +0000 (13:28 +0000)]
establish power-on reset stabilisation for Arty A7 and ECP5

2 years agoadd hack to modify VERSA_ECP5 85F platform to speed grade 7
Luke Kenneth Casson Leighton [Tue, 22 Mar 2022 17:00:39 +0000 (17:00 +0000)]
add hack to modify VERSA_ECP5 85F platform to speed grade 7

2 years agoadding hyperram for arty a7 and also adding a workaround for some stupid issues
Luke Kenneth Casson Leighton [Tue, 22 Mar 2022 16:59:31 +0000 (16:59 +0000)]
adding hyperram for arty a7 and also adding a workaround for some stupid issues

2 years agoadd microwatt hello_world source
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:40:58 +0000 (13:40 +0000)]
add microwatt hello_world source

2 years agocrank A7 FPGA speed down to experiment
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:40:47 +0000 (13:40 +0000)]
crank A7 FPGA speed down to experiment

2 years agocode-comments
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:19:14 +0000 (13:19 +0000)]
code-comments

2 years agofix Arty A7-100t PLL with quick demo
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 13:18:21 +0000 (13:18 +0000)]
fix Arty A7-100t PLL with quick demo

2 years agofirst cut at Arty A7 Clock-Reset-Generator with S7 PLL
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 11:34:42 +0000 (11:34 +0000)]
first cut at Arty A7 Clock-Reset-Generator with S7 PLL

2 years agobeginnings of arty a7 clock-reset-generator
Luke Kenneth Casson Leighton [Sun, 20 Mar 2022 09:56:46 +0000 (09:56 +0000)]
beginnings of arty a7 clock-reset-generator

2 years agoadd VERSA_ECP5 85F custom board
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 22:44:36 +0000 (22:44 +0000)]
add VERSA_ECP5 85F custom board

2 years agomove quick read/write test for hyperram in coldboot.c
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 20:46:31 +0000 (20:46 +0000)]
move quick read/write test for hyperram in coldboot.c

2 years agoset IO_TYPE 3.3v attribute on HyperRAM not IOSTANDARD
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 19:00:19 +0000 (19:00 +0000)]
set IO_TYPE 3.3v attribute on HyperRAM not IOSTANDARD
disable DDR3 temporarily with a hack on versa_ecp5 platform

2 years agocorrect pin names for HyperRAMResource, indent spi0 core
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 14:04:57 +0000 (14:04 +0000)]
correct pin names for HyperRAMResource, indent spi0 core

2 years agofixed hyperram pin names which was stopping verilator (and pretty much
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 12:37:33 +0000 (12:37 +0000)]
fixed hyperram pin names which was stopping verilator (and pretty much
everything) from working.  HyperRAMResource had a name "clk" as a pin
which was obviously getting merged with sys_clk, sigh

2 years agodisable hyperram for now (under investigation)
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 11:48:37 +0000 (11:48 +0000)]
disable hyperram for now (under investigation)

2 years agoadding in hyperram peripheral
Luke Kenneth Casson Leighton [Sat, 19 Mar 2022 11:28:37 +0000 (11:28 +0000)]
adding in hyperram peripheral

2 years agowhitespace / module-import / comments / tidyup
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 12:32:42 +0000 (12:32 +0000)]
whitespace / module-import / comments / tidyup

2 years agobeginning to add hyperram module
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 10:51:55 +0000 (10:51 +0000)]
beginning to add hyperram module

2 years agowhitespace cleanup and make SPI core (temporarily) optional
Luke Kenneth Casson Leighton [Fri, 18 Mar 2022 09:26:46 +0000 (09:26 +0000)]
whitespace cleanup and make SPI core (temporarily) optional
based on arctic tern fpga board. TODO: add arctic tern fpga board to
nmigen_boards

2 years agowork-in-progress on DDR3 firmware. sigh
Luke Kenneth Casson Leighton [Thu, 17 Mar 2022 13:40:09 +0000 (13:40 +0000)]
work-in-progress on DDR3 firmware. sigh

2 years agocomment about icarus verilog to speed up simulations
Luke Kenneth Casson Leighton [Thu, 17 Mar 2022 12:57:05 +0000 (12:57 +0000)]
comment about icarus verilog to speed up simulations

2 years agoAdd initial Tercel SPI controller
Raptor Engineering Development Team [Mon, 14 Mar 2022 00:33:24 +0000 (19:33 -0500)]
Add initial Tercel SPI controller

NOTE: Still needs testing on physical hardware,
waiting for Arctic Tern support.

2 years agosigh gramWishbone is not WB4-pipeline-burst-compliant
Luke Kenneth Casson Leighton [Thu, 10 Mar 2022 12:41:09 +0000 (12:41 +0000)]
sigh gramWishbone is not WB4-pipeline-burst-compliant
compensate for this with the "usual" WB3 classic trick stall=cyc&~ack;

2 years agofix WB6to32 downconverter with stall signalling
Luke Kenneth Casson Leighton [Wed, 9 Mar 2022 19:44:13 +0000 (19:44 +0000)]
fix WB6to32 downconverter with stall signalling

2 years agoadd stall signal to arbiter, assume nmigen-soc takes
Luke Kenneth Casson Leighton [Wed, 9 Mar 2022 12:12:51 +0000 (12:12 +0000)]
add stall signal to arbiter, assume nmigen-soc takes
care of adaptation from WB4-pipeline-burst to WB3-classic

2 years agoadd experimental stall-capable 64-to-32 wishbone converter
Luke Kenneth Casson Leighton [Fri, 4 Mar 2022 14:58:28 +0000 (14:58 +0000)]
add experimental stall-capable 64-to-32 wishbone converter
based on microwatt soc.vhdl

2 years agolots of comments in the yosys script file
Luke Kenneth Casson Leighton [Wed, 2 Mar 2022 13:59:26 +0000 (13:59 +0000)]
lots of comments in the yosys script file

2 years agoinvert reset and chip-select on dram, and initialise uart input
Luke Kenneth Casson Leighton [Wed, 2 Mar 2022 13:56:55 +0000 (13:56 +0000)]
invert reset and chip-select on dram, and initialise uart input
in iverilog sim

2 years agoforgot to include firmware in build for new icarus sim platform
Luke Kenneth Casson Leighton [Wed, 2 Mar 2022 13:56:15 +0000 (13:56 +0000)]
forgot to include firmware in build for new icarus sim platform

2 years agoadd new icarus-versa-ecp5 platform in ls2.py
Luke Kenneth Casson Leighton [Tue, 1 Mar 2022 17:09:07 +0000 (17:09 +0000)]
add new icarus-versa-ecp5 platform  in ls2.py

2 years agoincrease timescale of icarus simulation
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 21:51:56 +0000 (21:51 +0000)]
increase timescale of icarus simulation
to cover the period for coldboot.bin to initialise DRAM and perform
read/write tests

2 years agofix undefined uart_tx in icarus simulation, icarus is damn smart,
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 18:12:16 +0000 (18:12 +0000)]
fix undefined uart_tx in icarus simulation, icarus is damn smart,
it respects undefined values and propagates them. kinda cool

2 years agouse a slightly different yosys initialisation sequence for memory
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 18:10:57 +0000 (18:10 +0000)]
use a slightly different yosys initialisation sequence for memory

2 years agofix memory issue in yosys synth for icarus
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 17:43:59 +0000 (17:43 +0000)]
fix memory issue in yosys synth for icarus

2 years agoadd icarus simulation of ls2 with DDR3 and ECP5 models
Luke Kenneth Casson Leighton [Mon, 28 Feb 2022 17:25:04 +0000 (17:25 +0000)]
add icarus simulation of ls2 with DDR3 and ECP5 models

2 years agoinvert CRG reset on PLL see if it makes any difference
Luke Kenneth Casson Leighton [Wed, 23 Feb 2022 14:14:53 +0000 (14:14 +0000)]
invert CRG reset on PLL see if it makes any difference
also reduce power-on-reset delay

2 years agoadd comments about DRAM sync clock being identical to main clock
Luke Kenneth Casson Leighton [Wed, 23 Feb 2022 13:14:52 +0000 (13:14 +0000)]
add comments about DRAM sync clock being identical to main clock

2 years agoxdr=4 missing on ddr3 platform request for VERSA_ECP5
Luke Kenneth Casson Leighton [Tue, 22 Feb 2022 10:54:11 +0000 (10:54 +0000)]
xdr=4 missing on ddr3 platform request for VERSA_ECP5

2 years agolengthen cdelay pauses by a factor of 10
Luke Kenneth Casson Leighton [Mon, 21 Feb 2022 22:05:07 +0000 (22:05 +0000)]
lengthen cdelay pauses by a factor of 10

2 years ago* use readl and writel for accessing memory
Luke Kenneth Casson Leighton [Mon, 21 Feb 2022 18:40:25 +0000 (18:40 +0000)]
* use readl and writel for accessing memory
* add #defines for timer loops to make it possible to shorten
  time taken in simulations when running firmware in verilator
* try pulling DRAM DFII reset HI under software control
* split out DomainRenamer for DRAM Core
* add strange-looking way to expose DFII pads on FakePHY (simulated PH)
  which ensures that, under simulation, a batch of HDL does not get
  deleted: the clk_en, reset and odt parameters deep in the DFII
  interface connected to CSRs are *not* actually connected to anything
  "real" and consequently get deleted... oh and anything connecting
  to them)
* add some firmware debug print statements that need to go some time

2 years agouse microwatt mmu powerpc.lds with better stack space
Luke Kenneth Casson Leighton [Mon, 21 Feb 2022 18:34:13 +0000 (18:34 +0000)]
use microwatt mmu powerpc.lds with better stack space

2 years agofix dfi initialisation and calibration to use
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 13:55:32 +0000 (13:55 +0000)]
fix dfi initialisation and calibration to use
microwatt memory-io read/write (stwcix/lwzcix)

2 years agoset RAM base to #defined DRAM_BASE not hard-coded value
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 13:54:03 +0000 (13:54 +0000)]
set RAM base to #defined DRAM_BASE not hard-coded value

2 years agofor simulatio keep the simulated dram in the
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 00:06:56 +0000 (00:06 +0000)]
for simulatio keep the simulated dram in the
same clock domain as the main sim, for now

2 years agoadd fake (sim) DRAM from gram library
Luke Kenneth Casson Leighton [Sun, 20 Feb 2022 00:00:01 +0000 (00:00 +0000)]
add fake (sim) DRAM from gram library

2 years agomatch up dram initialisation parameters
Luke Kenneth Casson Leighton [Sat, 19 Feb 2022 15:54:05 +0000 (15:54 +0000)]
match up dram initialisation parameters

2 years agoput together coldboot startup firmware
Luke Kenneth Casson Leighton [Sat, 19 Feb 2022 15:32:17 +0000 (15:32 +0000)]
put together coldboot startup firmware

2 years agohm -abc9 seems to be working, and without -nowidelut
Luke Kenneth Casson Leighton [Sat, 19 Feb 2022 15:07:48 +0000 (15:07 +0000)]
hm -abc9 seems to be working, and without -nowidelut

2 years agoadd DRAM class to DDR3Soc
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 21:01:51 +0000 (21:01 +0000)]
add DRAM class to DDR3Soc

2 years agoadd FPGA argument to DDR3SoC
Luke Kenneth Casson Leighton [Fri, 18 Feb 2022 21:01:11 +0000 (21:01 +0000)]
add FPGA argument to DDR3SoC