allow setting individual directions on QSPI dq0-dq3

diff --git a/src/ls2.py b/src/ls2.py
index 91d37797a6dc0c6fc69ecbfac7abf49717b33334..b3b9e62a525e0d151279795761f9915ca04355e3 100644 (file)
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -684,13 +684,18 @@ def build_platform(fpga, firmware):
         # direct access to the SPI flash
         spi_0_ios = [
             Resource("spi_0", 0,
-                     Subsignal("dq",   Pins("W2 V2 Y2 W1", dir="io")),
+                     Subsignal("dq0",   Pins("W2", dir="io")),
+                     Subsignal("dq1",   Pins("V2", dir="io")),
+                     Subsignal("dq2",   Pins("Y2", dir="io")),
+                     Subsignal("dq3",   Pins("W1", dir="io")),
                      Subsignal("cs_n", Pins("R2", dir="o")),
                      Attrs(PULLMODE="NONE", DRIVE="4", IO_TYPE="LVCMOS33"))
         ]
         platform.add_resources(spi_0_ios)
-        spi_0_pins = platform.request("spi_0", 0, dir={"dq":"io", "cs_n":"o"},
-                                                  xdr={"dq":1, "cs_n":0})
+        spi_0_pins = platform.request("spi_0", 0, dir={"cs_n":"o"},
+                                                  xdr={"dq0":1, "dq1": 1,
+                                                       "dq2":1, "dq3": 1,
+                                                       "cs_n":0})
 
     print ("spiflash pins", spi_0_pins)
 

diff --git a/src/simsoc_hyperram_tb.v b/src/simsoc_hyperram_tb.v
index 3e267c50f0cec495aa8636983686d629a1295728..ddcad1a28b033e1710f35df232af2445cc117b91 100644 (file)
--- a/src/simsoc_hyperram_tb.v
+++ b/src/simsoc_hyperram_tb.v
@@ -89,7 +89,10 @@ s27kl0641
     // Quad SPI
     //.spi_flash_4x_0__dq__io(io_spi_dq),
     //.spi_flash_4x_0__cs__io(spi_cs_n),
-    .spi_0_0__dq__io(io_spi_dq),
+    .spi_0_0__dq0__io(io_spi_dq[0]),
+    .spi_0_0__dq1__io(io_spi_dq[1]),
+    .spi_0_0__dq2__io(io_spi_dq[2]),
+    .spi_0_0__dq3__io(io_spi_dq[3]),
     .spi_0_0__cs_n__io(spi_cs_n),
 
     // uart