riscv-isa-sim.git
2013-02-13 Andrew Watermanmigrate to c++11
2013-02-13 Andrew Watermanmake HTIF interactions deterministic; fix race
2013-01-26 Andrew Watermanremove unnecessary #include
2013-01-26 Andrew Watermanchange htif to link against libfesvr
2012-11-13 Yunsup Leefix vector code simulation problem, turn on SR_U64
2012-08-31 Andrew Watermannew tohost/fromhost semantics
2012-08-02 Andrew Watermannew tohost/fromhost semantics
2012-07-23 Andrew Watermancorrect HTIF reset behavior
2012-05-16 Andrew Watermanfix htif interaction with interactive mode
2012-05-09 Andrew Watermanper-core tohost/fromhost registers
2012-03-24 Andrew Watermannew supervisor mode
2012-03-24 Yunsup Leeadd disasm functions for vector
2012-03-20 Andrew Watermanmake NaN behavior consistent with hardfloat
2012-03-20 Andrew Watermanfix double-precision NaNs
2012-03-20 Andrew Watermanabstract regfile write port
2012-03-20 Andrew Watermanabstract regfile behind object
2012-03-19 Andrew Watermanupdate vector fences
2012-03-18 Yunsup Leeclean up vector exception instructions
2012-03-14 Yunsup Leeadd more instructions for vector exception handling
2012-03-14 Yunsup Leeadd vvcfg,vtcfg
2012-03-13 Yunsup Leeopcodes cleanup
2012-03-13 Andrew Watermanalways propagate default NaN (all bits set)
2012-03-10 Yunsup Leeslight change to vector supervisor instructions
2012-03-03 Yunsup Leeadd place holders for instructions to handle vector...
2012-03-03 Yunsup Leenew instructions to handle vector exceptions
2012-02-20 Andrew Watermannew HTIF protocol. update your fesvr.
2012-02-20 Andrew Watermanfixed a bug in remu[w]
2012-02-18 Andrew Watermanimplement lighter-weight htif packet header
2012-02-16 Andrew Watermanreimplement div[u][w]/rem[u][w]
2012-02-13 Andrew Watermanfix sltu disassembly
2012-02-09 Yunsup Leeinitialize tohost and fromhost
2012-02-01 Andrew Watermanremove debug printf
2012-02-01 Andrew Watermanpoll HTIF occasionally
2012-01-31 Andrew Watermandon't set badvaddr for instruction access faults
2012-01-30 Yunsup Leefix divide by zero bugs
2012-01-24 Andrew Watermancheck that virtual addresses are sign-extended
2012-01-23 Andrew Watermandisentangle decode.h from other headers
2012-01-23 Andrew Watermanwork around gcc 4.4 bug
2012-01-12 Andrew Watermanfix compilation for gcc 4.6.1
2011-12-11 Yunsup Leefix utidx assign bug, make ut code execute faster
2011-12-11 Yunsup Leefix the fpr abi names
2011-11-12 Your NameRemove dependence on binutils
2011-11-11 Andrew WatermanUse new compiler toolchain's disassembler
2011-11-11 Andrew WatermanChanged MFTX to use rs1 for its source
2011-11-11 Andrew WatermanChanged supervisor mode
2011-11-01 Andrew WatermanFixed tight coupling of host and target page size
2011-10-27 Andrew Watermanchanged page size to 8KB
2011-10-19 Yunsup LeeMerge branch 'master' of github.com:ucb-bar/riscv-isa-sim
2011-10-19 Yunsup Leefix vf
2011-10-19 Yunsup Leeyunsup made this fix..ask him
2011-08-18 Andrew Watermandon't forget to commit configure after autoconf!
2011-07-13 Rimas Avizienisadded #include <stdlib.h> to get rid of errors building...
2011-07-08 Rimas Avizienisbugfix to riscv.ac
2011-07-08 Rimas Avizienisfixes to make disassembly work under macos (with macpor...
2011-06-27 Andrew WatermanBuilds and runs on Mac OS 10.6.7
2011-06-20 Andrew Watermanpost-repo-split cleanup
2011-06-20 Andrew Watermantemporary undoing of renaming
2011-06-13 Andrew Waterman[sim] renamed to riscv-isa-run
2011-06-12 Andrew Waterman[xcc] minor performance tweaks
2011-06-12 Andrew Waterman[xcc] fixed simulator build time
2011-06-12 Andrew Waterman[xcc] tlb now stores host addresses
2011-06-11 Andrew Waterman[xcc] cleaned up mmu code
2011-06-11 Andrew Waterman[xcc] fix configure scripts
2011-06-11 Andrew Waterman[xcc] instructions now set PC explicitly
2011-06-11 Andrew Waterman[sim, opcodes] made sim more decoupled from opcodes
2011-06-06 Andrew Waterman[sim] fix writeback after ipi clearing
2011-06-05 Andrew Waterman[sim] add ability to clear IPIs
2011-06-01 Andrew Waterman[sim] fault on failed addr translations
2011-05-31 Andrew Waterman[sim] minor sim cleanup
2011-05-29 Andrew Waterman[sim,opcodes] improved sim build and run performance
2011-05-29 Andrew Waterman[fesvr,xcc,sim] fixed multicore sim for akaros
2011-05-23 Andrew Waterman[sim,xcc] add rdcycle/rdtime/rdinstret
2011-05-19 Andrew Waterman[sim] more fp<->int fixes
2011-05-19 Andrew Waterman[sim] more fp conversion bugs fixed
2011-05-19 Yunsup Lee[sim] change default hwvl
2011-05-19 Yunsup Lee[sim] vlen calc reflects the hardware
2011-05-18 Andrew Waterman[sim] fixed fcvt rounding bugs
2011-05-18 Yunsup Lee[opcodes,pk,sim] add more vector traps (for #banks...
2011-05-16 Andrew Waterman[sim,pk] cleanups & initial virtual memory support
2011-05-16 Yunsup Lee[sim,xcc] change cond. mov inst format, add implementation
2011-05-16 Yunsup Lee[opcodes,pk,sim,xcc] resolve a conflict
2011-05-16 Yunsup Lee[libs,opcodes,pk,sim,xcc] add mov*,fmov*, shuffle vec...
2011-05-14 Andrew Waterman[sim] initial support for virtual memory
2011-05-14 Andrew Waterman[sim] stubs for perfctr instructions
2011-05-13 Andrew Watermantweaked encoding of rdcycle & cousins
2011-05-06 Andrew Waterman[sim] fixed building sim without cache simulators
2011-05-01 Andrew Waterman[sim] hacked in a dcache simulator
2011-04-25 Andrew Waterman[xcc,sim,opcodes] added c.addiw
2011-04-24 Andrew Waterman[xcc,sim,opcodes] added more RVC instructions
2011-04-24 Andrew Waterman[sim] fixed divw/remw crashing simulator
2011-04-19 Andrew Waterman[xcc,sim] rv64 'w' instruction semantics changed
2011-04-19 Andrew Waterman[xcc,sim,opcodes] added rvc conditional branches
2011-04-17 Andrew Waterman[sim] removed undefined behavior for non-canonical...
2011-04-17 Andrew Waterman[sim] added "str" debug command
2011-04-15 Andrew Waterman[sim] fixed jalr immediate bug
2011-04-15 Andrew Waterman[sim] added icache simulator (disabled by default)
2011-04-13 Andrew Waterman[xcc,pk,sim] added privileged cflush instruction
2011-04-13 Andrew Waterman[xcc,sim] fixed RM field
2011-04-12 Andrew Waterman[xcc,sim] rvc loads and stores
2011-04-12 Andrew Waterman[sim,pk] fixed minor pk bugs and trap codes
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