riscv-tests.git
2014-02-06 Andrew WatermanClean up benchmarks; support uarch-specific counters
2014-02-06 Yunsup Leepush env
2014-02-05 Quan NguyenAdd Stephen's vector FFT code
2014-02-04 Quan NguyenAdd vfmsv instruction test, change vsetprec to vsetucfg
2014-02-01 Andrew WatermanShrink hex dumps
2014-02-01 Andrew WatermanAdd rv32si tests, including illegality of shamt[5]
2014-02-01 Henry CookMinor Makefile improvements
2014-01-31 Andrew WatermanMake CSR test much more robust
2014-01-31 Andrew WatermanReference TESTNUM instead of x28 directly
2014-01-24 Eric LoveDone with rv32ui asm test ports
2014-01-24 Eric LoveFixed srl, srli
2014-01-24 Eric Lovesrl and srai
2014-01-23 Eric LoveFirst round of rv32ui asm tests
2014-01-22 Andrew WatermanAdd CSRRx/CSRRxI test
2014-01-21 Quan NguyenAdd packed vvadd test for confprec Hwacha
2014-01-21 Quan NguyenPush env
2014-01-16 Andrew WatermanMake LR/SC test more thorough
2014-01-14 Andrew WatermanUpdate v env
2013-11-29 Albert OuFix load offsets for the vvadd_fw test
2013-11-25 Andrew WatermanUpdate benchmarks to new privileged ISA
2013-11-24 Andrew WatermanUpdate to new privileged ISA
2013-11-20 Quan NguyenAdd rv64uv-p-amoxor_{w,d} tests
2013-11-20 Yunsup Leefix rv64uv/vvadd_fd test to correctly check results
2013-11-14 Yunsup Leeadded riscv-test-env as a submodule
2013-11-14 Yunsup Leesplit out envs from riscv-tests
2013-11-06 Yunsup Leeadd accelerator disabled cause
2013-11-06 Yunsup Leecorrectly set SR_EA bit for all vector physical supervi...
2013-11-06 Yunsup Leecorrectly set SR_EA bit for all vector physical tests
2013-10-19 Yunsup Leerevamp pt tests as well
2013-10-19 Yunsup Leehwacha virtual tests working
2013-10-18 Yunsup Leeadd hwacha exception support
2013-10-17 Yunsup Leedisable vector bank tests
2013-10-17 Yunsup Leeadd passing physical vector tests back in
2013-10-17 Yunsup Leeupdate out-of-date floating-point test in rv64uv
2013-10-17 Yunsup Leefix broken amoor_w rv64uv test
2013-10-10 Christopher... Merge branch 'master' of github.com:ucb-bar/riscv-tests
2013-10-10 Christopher... Benchmarks now run in user-mode.
2013-10-10 Yunsup Leerevamp hwacha tests
2013-09-21 Andrew WatermanRe-enable virtual memory tests
2013-09-21 Andrew WatermanNew AUIPC semantics
2013-09-15 Andrew WatermanDon't emit vector instructions for now
2013-09-11 Andrew WatermanAdd AMOXOR test
2013-08-25 Andrew WatermanDon't build vector benchmarks for now
2013-08-25 Andrew Watermandon't emit vvcfg for now
2013-08-24 Andrew WatermanAdd autoconf-generated configure
2013-08-24 Andrew WatermanReflect changes to ISA
2013-08-24 Sebastien MiroloMerge pull request #1 from smirolo/configure
2013-08-12 Sebastien MiroloMerge branch 'master' of git://github.com/ucb-bar/riscv...
2013-07-26 Andrew WatermanRemove JALR static hints
2013-07-24 Sebastien Mirolofeature: add autoconf
2013-06-14 Henry Cookremoved bad mt test
2013-06-13 Henry Cookmultithreading tests from 152 lab 5
2013-06-10 Andrew WatermanDon't disassemble zeros
2013-05-16 Yunsup Leeadd failing multiply test
2013-05-14 Yunsup Leechange riscv-isa-run to spike
2013-05-02 Andrew Watermanuse RVTEST_RV64UF macro for FPU tests
2013-05-02 Andrew Watermanpass all FP tests if FPU not present
2013-04-30 Andrew Watermanadd first RV32 tests
2013-04-30 Yunsup Leeadd benchmarks gitignore
2013-04-30 Yunsup Leebenchmarks initial commit
2013-04-24 Yunsup Leeadd gitignore
2013-04-24 Yunsup Leecleanup Makefiles in isa
2013-04-24 Yunsup Leeadd missing RVTEST_CODE_END macros
2013-04-24 Yunsup Leeadd more header information to test_macros
2013-04-24 Yunsup Leechange label names to avoid conflicts with test code
2013-04-22 Yunsup Leeget rid of RVTEST_PASS_NOFP
2013-04-22 Yunsup Leeinitial commit