yosys.git
2021-07-20 whitequarkcxxrtl: treat wires with multiple defs as not inlinable.
2021-07-20 whitequarkcxxrtl: treat assignable internal wires used only for...
2021-07-20 whitequarkMerge pull request #2881 from whitequark/cxxrtl-sideway...
2021-07-19 whitequarkcxxrtl: escape colon in variable names in VCD writer.
2021-07-18 whitequarkMerge pull request #2880 from whitequark/cxxrtl-fix...
2021-07-18 whitequarkcxxrtl: add debug_item::{get,set}.
2021-07-17 whitequarkMerge pull request #2879 from whitequark/cxxrtl-fix...
2021-07-17 whitequarkcxxrtl: treat internal wires used only for debug as...
2021-07-16 Rupert SwarbrickAdd support for parsing the SystemVerilog 'bind' construct
2021-07-16 whitequarkMerge pull request #2874 from whitequark/cxxrtl-fix...
2021-07-16 whitequarkMerge pull request #2873 from whitequark/cxxrtl-fix...
2021-07-16 whitequarkMerge pull request #2872 from whitequark/cxxrtl-fix...
2021-07-16 whitequarkcxxrtl: run hierarchy pass regardless of (*top*) attrib...
2021-07-16 whitequarkcxxrtl: emit debug items for unused public wires.
2021-07-16 whitequarkcxxrtl: don't expect user cell inputs to be wires.
2021-07-16 whitequarkMerge pull request #2871 from whitequark/cxxrtl-fix...
2021-07-16 whitequarkcxxrtl: don't mark buffered internal wires as UNUSED...
2021-07-16 whitequarkMerge pull request #2870 from whitequark/cxxrtl-fix...
2021-07-15 whitequarkcxxrtl: mark dead local wires as unused even with inlin...
2021-07-15 Zachary Snowsv: fix two struct access bugs
2021-07-15 Rupert SwarbrickAdd a test for interfaces on modules loaded on-demand
2021-07-15 Rupert SwarbrickExtract missing module support in hierarchy.cc to a...
2021-07-14 whitequarkMerge pull request #2866 from rswarbrick/found-init
2021-07-14 Rupert SwarbrickDelete unused found_init variable
2021-07-13 Marcelina Kościelnickakernel/mem: Add a coalesce_inits helper.
2021-07-12 GCHQDeveloper560Add support for the Bitwuzla solver
2021-07-12 Marcelina Kościelnickakernel/mem: Use delayed removal for inits as well.
2021-07-12 Marcelina Kościelnickakernel/mem: Add documentation for more helper functions.
2021-07-12 Marcelina Kościelnickacxxrtl: Support memory writes in processes.
2021-07-12 Marcelina Kościelnickacxxrtl: Add support for memory read port reset.
2021-07-12 Marcelina Kościelnickacxxrtl: Add support for mem read port initial data.
2021-07-12 Marcelina Kościelnickacxxrtl: Convert to Mem helpers.
2021-07-12 Marcelina Kościelnickakernel/mem: Commit new values of attributes in emit.
2021-07-12 Marcelina Kościelnickakernel/mem: Make the Mem helpers inherit from AttrObject.
2021-07-11 Marcelina Kościelnickartlil: Make Process handling more uniform with Cell...
2021-07-10 Marcelina Kościelnickaice40: Fix LUT input indices in opt_lut -dlogic (again).
2021-07-09 Miodrag MilanovicUpdate to latest Verific with extensions for initial...
2021-07-06 Zachary Snowsv: fix a few struct and enum memory leaks
2021-07-06 gatecatecp5: Add DCSC blackbox
2021-07-05 Claire XenMerge pull request #2835 from YosysHQ/verific_command
2021-07-05 XiretzaMakefile: allow running multiple sanitizers at once
2021-07-05 XiretzaMakefile: use git/make -C instead of cd
2021-07-05 XiretzaMakefile: pass PRETTY=0 to ABC
2021-07-05 XiretzaMakefile: don't bake DESTDIR into libyosys DT_SONAME
2021-07-05 XiretzaMakefile: clean up PYOSYS configuration
2021-07-05 Miodrag MilanovicAdd additional help
2021-06-19 whitequarkMerge pull request #2842 from whitequark/fix-wasi-build
2021-06-19 whitequarkFix WASI build after commit 1d88bea1.
2021-06-18 Miodrag MilanovićMerge pull request #2836 from YosysHQ/gatecat/pyosys...
2021-06-17 Rupert SwarbrickMove interface expansion in hierarchy.cc into a helper...
2021-06-17 Zachary Snowsv: fix up end label checking
2021-06-16 Ashton SnelgroveInclude blif reader header in public facing extension...
2021-06-16 gatecatpyosys: Clear SIGINT handler after Python loads
2021-06-16 Miodrag MilanovicSupport command files in Verific
2021-06-14 Xiretzaverilog: fix leaking of type names in parser
2021-06-14 Xiretzaverilog: fix wildcard port connections leaking memory
2021-06-14 Xiretzaast: delete wires and localparams after finishing const...
2021-06-14 Xiretzaverilog: fix leaking ASTNodes
2021-06-14 Xiretzaast: fix error condition causing assert to fail
2021-06-14 Zachary Snowmacos: fix leak in proc_self_dirname()
2021-06-14 Rupert SwarbrickSimplify some RTLIL destructors
2021-06-14 Marcelina Kościelnickaverilog: Squash a memory leak.
2021-06-11 Marcelina KościelnickaAdd regression test for #2824.
2021-06-11 gatecatopt_muxtree: Update port_off and port_idx even for...
2021-06-09 Marcelina Kościelnickaopt_expr: Fix mul/div/mod by POT patterns to support...
2021-06-09 Marcelina Kościelnickaopt_expr: Optimize div/mod by const 1.
2021-06-09 Claire XenMerge pull request #2817 from YosysHQ/claire/fixemails
2021-06-09 Claire Xenia... Fix deadname SVN links
2021-06-09 Claire Xenia... Intersynth URL
2021-06-09 Claire Xenia... More deadname stuff
2021-06-09 Claire Xenia... Fix icestorm links
2021-06-09 Claire Xenia... More deadname stuff
2021-06-09 Claire Xenia... Use HTTPS for website links, gatecat email
2021-06-09 Claire Xenia... Fix files with CRLF line endings
2021-06-08 Zachary Snowverilog: check for module scope identifiers during...
2021-06-08 Zachary Snowmem2reg: tolerate out of bounds constant accesses
2021-06-08 Zachary Snowautoname: simple perf optimizations
2021-06-07 Claire Xenia... Fixing old e-mail addresses and deadnames
2021-06-07 Claire Xenia... Add claire deadname stuff to .mailmap
2021-06-01 Zachary Snowsv: support tasks and functions within packages
2021-06-01 Marcelina Kościelnickakernel/mem: Recognize some deprecated memory port configs.
2021-05-31 Marcelina Kościelnickamemory_map: Improve start_offset handling.
2021-05-29 Marcelina Kościelnickamemory_share: Add read port merging.
2021-05-28 Marcelina Kościelnickamemory_share: Improve sat-based port sharing.
2021-05-27 Marcelina KościelnickaMake a few passes auto-call Mem::narrow instead of...
2021-05-27 Marcelina Kościelnickabackends/verilog: Add support for memory read port...
2021-05-27 Marcelina Kościelnickabackends/verilog: Add wide port support.
2021-05-27 Marcelina Kościelnickamemory_share: Improve same-address merging, recognize...
2021-05-27 Marcelina Kościelnickakernel/mem: Add helpers for write port widening.
2021-05-26 Marcelina Kościelnickakernel/mem: Add sub_addr helpers.
2021-05-26 Marcelina Kościelnickakernel/mem: Add prepare_wr_merge helper.
2021-05-25 Marcelina Kościelnickabackends/verilog: Try to preserve mem write port priori...
2021-05-25 Marcelina Kościelnickamem/extract_rdff: Fix "no FF made" edge case.
2021-05-25 Marcelina Kościelnickamemory_bram: Reuse extract_rdff helper for make_outreg.
2021-05-25 Zachary Snowverilog: fix case expression sign and width handling
2021-05-25 Zachary Snowsv: support remaining assignment operators
2021-05-25 Marcelina Kościelnickamem/extract_rdff: Add alternate transparency handling.
2021-05-25 Marcelina Kościelnickaopt_mem: Add reset/init value support.
2021-05-25 Marcelina Kościelnickakernel/mem: Add model support for read port init value...
2021-05-25 Marcelina Kościelnickamem/extract_rdff: Fix wire naming and wide port support.
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