updates/021_2019dec29_nlnet_grants_approved.mdwn

   1 Across several projects, nearly EUR 400,000 worth of additional funding
   2 applications were put in, and around EUR 200,000 to 250,000 of those have
   3 been approved.  The RISC-V Foundation's continued extreme unethical
   4 actions have led us to consider using Power ISA.
   5
   6 ### NLNet Grants
   7
   8 [NLNet](http://nlnet.nl) were first approached eighteen months ago, with
   9 an initial application to develop the core of a privacy-respecting trustable
  10 processor.  Whilst NLNet's primary focus of the past fifteen years has been
  11 software, they have funded reverse-engineering for
  12 [Osmocon BB](https://nlnet.nl/project/sdr-phy/) and for
  13 [OpenBSC](https://nlnet.nl/project/iuh-openbsc/) so are no strangers to
  14 hardware.  The problem with software is: if the hardware cannot be trusted,
  15 then no amount of trustable, open and transparent software will help.
  16
  17 The [additional proposals](https://libre-riscv.org/nlnet_proposals/)
  18 expand on the core, to cover:
  19
  20 * formal mathematical correctness proofs for the entire processor, including
  21   the FPU (no more Intel Pentium FPDIV bugs...)
  22 * a special video acceleration focus, adding video decode instructions
  23 * an additional 3D driver based on AMDVLK or MESA
  24 * some funding to be able to properly develop and document ISA standards
  25 * a Wishbone streaming enhancement to add A/V timecode stamps to Wishbone B4,
  26   and to develop independent libre-licensed peripherals as examples
  27 * two interrelated proposals to develop libre cell Libraries
  28   ([Chips4Makers](http://chips4makers.be)), to be used by a team at
  29   [LIP6.fr](http://lip6.fr) using the Alliance / Coriolis2 ASIC layout
  30   tools; Additional funding will go to the nmigen team for ASIC
  31   improvements and special integration with Coriolis2
  32
  33 The goal here is to get to a working, commercially viable 180 nm single-core
  34 ASIC at around 300 to 350 MHz, suitable for use as a high-end embedded
  35 controller.  Staf from Chips4Makers will act as the "NDA firebreak" between
  36 us and TSMC.
  37
  38 All of these have been approved by NLNet, and, crucially, the external
  39 independent review process successfully completed for each.  The exact
  40 amounts of each grant is to be confirmed, with each being possible to be
  41 up to the limit of EUR 50,000 for each sub-project.
  42
  43 Part of the process was a little tricky, initially: the independent reviewers
  44 expressed surprise at the amounts being requested for *sub*-tasks when the
  45 initial application was so small.  The reason was very simple: both Jacob
  46 and I have unique low-income circumstances that simply do not need European /
  47 Western style living expenses.  Whereas, when we get to much more specialist
  48 tasks (such as formal mathematical proofs, video assembly-level drivers,
  49 and so on), these fields are so specialized that finding people who are good
  50 *and* who are able to exist on student or southeast-asia-level funding is just not
  51 practical.
  52
  53 Therefore, we made sure that the calculations were based around an approximate
  54 EUR 3,000 per month budget per person, bearing in mind that due to NLNet's
  55 international tax agreements, this being donations, that's equivalent to a
  56 "wage" of approximately nearly twice that amount (three times if, as a
  57 business, you have to take into consideration corporation tax / employee
  58 insurance as well).
  59
  60 We now need to find people willing to help do the work. What is
  61 really nice is that NLNet will donate money to them for completion of that work!
  62 Therefore, if you've always wanted to work on a 3D processor, its drivers
  63 and its source code, do get in touch.
  64
  65 ### PowerPC
  66
  67 This is a
  68 [long story](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-October/003035.html)
  69 that was picked up by
  70 [Phoronix](https://www.phoronix.com/scan.php?page=news_item&px=Libre-RISC-V-Eyeing-POWER)
  71 before we had a chance to make any kind of real "announcement."  However,
  72 we're always really grateful to Michael for his coverage of the Libre SoC,
  73 as it always sparks some insightful, useful, and engaging discussions.
  74
  75 The summary is this: Libre and Open contributors to RISC-V have been
  76 disregarded for several years.  **Long** before I joined the RISC-V
  77 mailing lists, it was *well-known* within that small and tightly-knit
  78 community that if you were not associated directly with UC Berkeley, you were
  79 basically not welcome.  Caveat: if you signed the NDA-like agreement
  80 which conflicts directly with, for example, the Debian Charter and
  81 the whole purpose of libre licenses, then you got a "voice" and you
  82 got access to the closed and secretive RISC-V resources and mailing
  83 lists.
  84
  85 Michael puts it extremely well: I have absolutely no problem with the
  86 ISA itself, it's the abuse of power and the flagrant ignoring and abuse
  87 of basic tenets of trademark law that are just completely untenable.
  88 Not only that: one well-paid employee of SiFive has *repeatedly* engaged
  89 in defamation attacks for over eighteen months, even raising a formal
  90 complaint through the newly-established relationship with the Linux
  91 Foundation failed to keep that individual under control.  Also adversely
  92 impacted was the newly-established Open Graphics Alliance initiative,
  93 which was independently started by Pixilica back in October,
  94 proposed at SIGGRAPH 2019 and welcomed by world-leading 3D industry
  95 experts.
  96
  97 At some point you just have to appreciate that to continue to support
  98 an unethical organisation is itself unethical, and thus I made the
  99 decision to reach out to MIPS and Power.  The MIPS website didn't even
 100 work, so I gave up there immediately.  The Open Power Foundation on
 101 the other hand, I was both delighted and surprised to hear back from
 102 a former colleague when I was in Canberra, 20 years ago: Hugh Blemings.
 103
 104 Hugh is extremely knowledgeable, highly intelligent, and completely
 105 understands Libre and Open principles.  We had only 15 minutes to
 106 talk before he had to focus on preparing for the upcoming Open Power
 107 Conference: in that short time, we covered:
 108
 109 * the need for ISANS / ISAMUX "breakout" system.  Hugh even said,
 110   without prompting, that the scheme I quickly described would
 111   allow full software-level ISA emulation and that that was a really
 112   good and necessary thing.  With this **formally** in place as part
 113   of an officially-approved Power ISA Standard, not only could our team
 114   expand the Power ISA in a safe and controlled fashion, so could other
 115   adopters.
 116 * that the core OpenPower members had *already been discussing* how to make
 117   sure that new Libre teams with a commercial focus could join and not
 118   have any transparency / patent / NDA / royalty / licensing conflicts
 119   of interest.  The only major thing that the other members wanted was
 120   a "public relations blackout period," right around the time of announcement of
 121   new standards, which sounds perfectly reasonable to me.
 122 * that IBM will be providing a royalty-free unlimited license grant
 123   for *all* of its patents, as long as firstly the licensees do not
 124   make any effort to assert patents **against** IBM, and secondly,
 125   as long as implementations are fully-compliant with the OpenPower
 126   standards.
 127 * that there is discussion underway as to the creation and maintenance
 128   of formal compliance test suites, just as there is today with the
 129   RISC-V ISA.
 130 * that the use of a certification mark - not a service mark or a trade mark -
 131   is the most appropriate thing for ISA standards.  I mentioned this
 132   only briefly however it takes a lot more than 15 minutes to properly
 133   explain, so I am not going to push it: Hugh is doing so much already.
 134
 135 It was a very busy and positive conversation, where it is clear that
 136 we caught them right at the beginning of the process.  Consequently,
 137 my discussion with Hugh was just at the right time.  Without that,
 138 the existing OpenPower members might never have really truly believed
 139 that any Libre **commercial** project would ever in fact come forward
 140 and that the steps the OpenPower members were taking were purely hypothetical.
 141 Out of the blue (pun intended), I contact Hugh and highlight that no,
 142 it's not hypothetical.
 143
 144 The next step, then, will be to wait until mid-january when people come
 145 back from holiday, and wait for the announcement of the OpenPower
 146 license agreement.  Hugh reassures me that there's nothing spectacularly
 147 controversial in it, and given his long-standing experience of several
 148 decades with the Libre and Open Communities, I cannot think of a reason
 149 why it would not be possible to sign it.  We just have to see.
 150
 151 The timing here with NLNet is just on the edge: we have to create a
 152 full list of milestones and assign a fixed budget to each (then later
 153 subdivide them into sub-tasks under that milestone).  This is a leeeetle
 154 bit challenging when we have not yet reviewed the OpenPower agreement,
 155 however, given that the majority of the tasks are ISA-independent, it
 156 will actually work out fine.
 157
 158 The only other major thing: what the heck do we do with the libre-riscv.org
 159 domain?  As you can see on the mailing list decision, we decided to go
 160 with a *userspace* RV64GC dual-ISA front-end.  **Userspace** RISC-V POSIX
 161 (Linux / Android) applications will work perfectly well, as will **userspace**
 162 PowerISA POSIX applications, however the **kernel** (supervisor) space will
 163 be entirely PowerISA.
 164
 165 The video and 3D acceleration opcodes will be **entirely in the Power ISA**.
 166 We are sick and tired of the RISC-V Foundation's blatant mismanagement.
 167 Therefore, we will comply to the absolute minimal letter with RV64GC for
 168 the benefit of our users, backers, and sponsors. However, RISC-V and the
 169 RISC-V ISA itself
 170 will no longer receive the benefit of the advancements and innovation
 171 that we have received funding and support to develop.
 172
 173 So, the assembly-code being written by hand for the video acceleration
 174 side, as well as the 3D drivers for Kazan and MESA, will "flip" from RV64GC
 175 RISC-V over to the Power ISA, which will be fully 3D accelerated with advanced
 176 Simple-V Vector operations, then return back to userspace RISC-V RV64GC ISA
 177 to continue serving the user application.
 178
 179 Next steps for us include setting up a foundation under which the processor
 180 can be developed, and to look towards the next major funding step: USD 10M
 181 to 20M.