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Remove verilog header files built from Chisel .prm file.
author
Richard Xia
<rxia@sifive.com>
Wed, 30 Nov 2016 22:30:05 +0000
(14:30 -0800)
committer
Richard Xia
<rxia@sifive.com>
Wed, 30 Nov 2016 22:30:05 +0000
(14:30 -0800)
common.mk
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fpga/e300artydevkit/Makefile
patch
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fpga/e300artydevkit/script/prologue.tcl
patch
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fpga/e300artydevkit/src/system.v
patch
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blob
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fpga/u500vc707devkit/Makefile
patch
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blob
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history
fpga/u500vc707devkit/script/prologue.tcl
patch
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blob
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history
fpga/u500vc707devkit/src/system.v
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diff --git
a/common.mk
b/common.mk
index e09cc29a1483485a241437d929269f8dfcf2a3f9..74f74de59c40891b8f4ea9af77366e8cfc772363 100644
(file)
--- a/
common.mk
+++ b/
common.mk
@@
-47,20
+47,13
@@
ifneq ($(PATCHVERILOG),"")
endif
endif
-verilog_consts_vh := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).vh
-$(verilog_consts_vh): $(firrtl_prm)
- echo "\`ifndef CONST_VH" > $@
- echo "\`define CONST_VH" >> $@
- sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $< >> $@
- echo "\`endif // CONST_VH" >> $@
-
.PHONY: verilog
.PHONY: verilog
-verilog: $(verilog)
$(verilog_consts_vh)
+verilog: $(verilog)
# Build .mcs
mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs
# Build .mcs
mcs := $(BUILD_DIR)/$(CONFIG_PROJECT).$(CONFIG).mcs
-$(mcs): $(verilog)
$(verilog_consts_vh)
- VSRC_TOP=$(verilog)
VSRC_CONSTS=$(verilog_consts_vh)
EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
+$(mcs): $(verilog)
+ VSRC_TOP=$(verilog) EXTRA_VSRCS="$(EXTRA_FPGA_VSRCS)" $(MAKE) -C $(FPGA_DIR) mcs
cp $(FPGA_DIR)/obj/system.mcs $@
.PHONY: mcs
cp $(FPGA_DIR)/obj/system.mcs $@
.PHONY: mcs
diff --git
a/fpga/e300artydevkit/Makefile
b/fpga/e300artydevkit/Makefile
index b4e9bd41310e9985e8e7177d3a23a7c433f9bac3..a815f6f013e5bcb077f3b6ee3c60928a16f76da1 100644
(file)
--- a/
fpga/e300artydevkit/Makefile
+++ b/
fpga/e300artydevkit/Makefile
@@
-6,7
+6,7
@@
VIVADOFLAGS := \
bit := obj/system.bit
$(bit): script/impl.tcl script/init.tcl
bit := obj/system.bit
$(bit): script/impl.tcl script/init.tcl
- VSRC_TOP=$(VSRC_TOP)
VSRC_CONSTS=$(VSRC_CONSTS)
EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
+ VSRC_TOP=$(VSRC_TOP) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
.PHONY: bit
bit: $(bit)
.PHONY: bit
bit: $(bit)
diff --git
a/fpga/e300artydevkit/script/prologue.tcl
b/fpga/e300artydevkit/script/prologue.tcl
index 91fdf974d73fbb101a11a75eced8281f7d1e290b..0fca22835eeb9f5e12c70275096b135898dbb9b7 100644
(file)
--- a/
fpga/e300artydevkit/script/prologue.tcl
+++ b/
fpga/e300artydevkit/script/prologue.tcl
@@
-50,15
+50,10
@@
if {[info exists ::env(EXTRA_VSRCS)]} {
#}
set vsrc_top $::env(VSRC_TOP)
#}
set vsrc_top $::env(VSRC_TOP)
-set vsrc_consts $::env(VSRC_CONSTS)
-set_property verilog_define [list \
- "VSRC_CONSTS=${vsrc_consts}" \
- "VSRC_TOP=${vsrc_top}" \
- ] $obj
+set_property verilog_define [list "VSRC_TOP=${vsrc_top}"] $obj
add_files -norecurse -fileset $obj $vsrc_top
add_files -norecurse -fileset $obj $vsrc_top
-add_files -norecurse -fileset $obj $vsrc_consts
if {[get_filesets -quiet sim_1] eq ""} {
create_fileset -simset sim_1
if {[get_filesets -quiet sim_1] eq ""} {
create_fileset -simset sim_1
diff --git
a/fpga/e300artydevkit/src/system.v
b/fpga/e300artydevkit/src/system.v
index 1c45c43e40da1a3fcf14e25b2598fa08b95a217d..afb40d5d59cc562e51097b1b3a4f4ebc712fb27f 100644
(file)
--- a/
fpga/e300artydevkit/src/system.v
+++ b/
fpga/e300artydevkit/src/system.v
@@
-1,8
+1,5
@@
`timescale 1ns/1ps
`timescale 1ns/1ps
-`define STRINGIFY(x) `"x`"
-`include `STRINGIFY(`VSRC_CONSTS)
-
module system
(
input wire CLK100MHZ,
module system
(
input wire CLK100MHZ,
diff --git
a/fpga/u500vc707devkit/Makefile
b/fpga/u500vc707devkit/Makefile
index b4e9bd41310e9985e8e7177d3a23a7c433f9bac3..a815f6f013e5bcb077f3b6ee3c60928a16f76da1 100644
(file)
--- a/
fpga/u500vc707devkit/Makefile
+++ b/
fpga/u500vc707devkit/Makefile
@@
-6,7
+6,7
@@
VIVADOFLAGS := \
bit := obj/system.bit
$(bit): script/impl.tcl script/init.tcl
bit := obj/system.bit
$(bit): script/impl.tcl script/init.tcl
- VSRC_TOP=$(VSRC_TOP)
VSRC_CONSTS=$(VSRC_CONSTS)
EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
+ VSRC_TOP=$(VSRC_TOP) EXTRA_VSRCS="$(EXTRA_VSRCS)" $(VIVADO) $(VIVADOFLAGS) -source script/init.tcl -source script/impl.tcl
.PHONY: bit
bit: $(bit)
.PHONY: bit
bit: $(bit)
diff --git
a/fpga/u500vc707devkit/script/prologue.tcl
b/fpga/u500vc707devkit/script/prologue.tcl
index 91fdf974d73fbb101a11a75eced8281f7d1e290b..0fca22835eeb9f5e12c70275096b135898dbb9b7 100644
(file)
--- a/
fpga/u500vc707devkit/script/prologue.tcl
+++ b/
fpga/u500vc707devkit/script/prologue.tcl
@@
-50,15
+50,10
@@
if {[info exists ::env(EXTRA_VSRCS)]} {
#}
set vsrc_top $::env(VSRC_TOP)
#}
set vsrc_top $::env(VSRC_TOP)
-set vsrc_consts $::env(VSRC_CONSTS)
-set_property verilog_define [list \
- "VSRC_CONSTS=${vsrc_consts}" \
- "VSRC_TOP=${vsrc_top}" \
- ] $obj
+set_property verilog_define [list "VSRC_TOP=${vsrc_top}"] $obj
add_files -norecurse -fileset $obj $vsrc_top
add_files -norecurse -fileset $obj $vsrc_top
-add_files -norecurse -fileset $obj $vsrc_consts
if {[get_filesets -quiet sim_1] eq ""} {
create_fileset -simset sim_1
if {[get_filesets -quiet sim_1] eq ""} {
create_fileset -simset sim_1
diff --git
a/fpga/u500vc707devkit/src/system.v
b/fpga/u500vc707devkit/src/system.v
index e81edcb99bd2e861b1f399a10c1433a09d3da362..fb6ae5b6a4c10e0d35525160ca978ccd06a536b7 100644
(file)
--- a/
fpga/u500vc707devkit/src/system.v
+++ b/
fpga/u500vc707devkit/src/system.v
@@
-2,9
+2,6
@@
`timescale 1ns/1ps
`default_nettype none
`timescale 1ns/1ps
`default_nettype none
-`define STRINGIFY(x) `"x`"
-`include `STRINGIFY(`VSRC_CONSTS)
-
module system
(
//200Mhz differential sysclk
module system
(
//200Mhz differential sysclk