ca218a65

   1 \e[1mdiff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py\e[m
   2 \e[1mindex 2604262..00eecc3 100644\e[m
   3 \e[1m--- a/src/add/example_buf_pipe.py\e[m
   4 \e[1m+++ b/src/add/example_buf_pipe.py\e[m
   5 \e[36m@@ -203,7 +203,7 @@\e[m \e[mclass BufferedPipeline:\e[m
   6                 ]\e[m
   7  \e[m
   8  \e[m
   9 \e[31m-class BufPipe(BufferedPipeline):\e[m
  10 \e[32m+\e[m\e[32mclass ExampleBufPipe(BufferedPipeline):\e[m
  11  \e[m
  12      def __init__(self):\e[m
  13          BufferedPipeline.__init__(self)\e[m
  14 \e[1mdiff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py\e[m
  15 \e[1mindex eb0c935..e074c5c 100644\e[m
  16 \e[1m--- a/src/add/nmigen_div_experiment.py\e[m
  17 \e[1m+++ b/src/add/nmigen_div_experiment.py\e[m
  18 \e[36m@@ -6,7 +6,7 @@\e[m \e[mfrom nmigen import Module, Signal, Const, Cat\e[m
  19  from nmigen.cli import main, verilog\e[m
  20  \e[m
  21  from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase\e[m
  22 \e[31m-from nmigen_add_experiment import FPState\e[m
  23 \e[32m+\e[m\e[32mfrom nmigen_add_experiment import FPState, FPGetOp\e[m
  24  \e[m
  25  class Div:\e[m
  26      def __init__(self, width):\e[m
  27 \e[36m@@ -66,14 +66,26 @@\e[m \e[mclass FPDIV(FPBase):\e[m
  28              # ******\e[m
  29              # gets operand a\e[m
  30  \e[m
  31 \e[32m+\e[m\e[32m            geta = FPGetOp("get_a", "get_b", self.in_a, self.width)\e[m
  32 \e[32m+\e[m\e[32m            geta.setup(m, self.in_a)\e[m
  33 \e[32m+\e[m
  34              with m.State("get_a"):\e[m
  35 \e[31m-                self.get_op(m, self.in_a, a, "get_b")\e[m
  36 \e[32m+\e[m\e[32m                geta.action(m)\e[m
  37 \e[32m+\e[m\e[32m                with m.If(geta.out_decode):\e[m
  38 \e[32m+\e[m\e[32m                    m.d.sync += a.decode(self.in_a.v)\e[m
  39 \e[32m+\e[m\e[32m                #self.get_op(m, self.in_a, a, "get_b")\e[m
  40  \e[m
  41              # ******\e[m
  42              # gets operand b\e[m
  43  \e[m
  44 \e[32m+\e[m\e[32m            getb = FPGetOp("get_b", "special_cases", self.in_b, self.width)\e[m
  45 \e[32m+\e[m\e[32m            getb.setup(m, self.in_b)\e[m
  46 \e[32m+\e[m
  47              with m.State("get_b"):\e[m
  48 \e[31m-                self.get_op(m, self.in_b, b, "special_cases")\e[m
  49 \e[32m+\e[m\e[32m                getb.action(m)\e[m
  50 \e[32m+\e[m\e[32m                with m.If(getb.out_decode):\e[m
  51 \e[32m+\e[m\e[32m                    m.d.sync += b.decode(self.in_b.v)\e[m
  52 \e[32m+\e[m\e[32m                #self.get_op(m, self.in_b, b, "special_cases")\e[m
  53  \e[m
  54              # ******\e[m
  55              # special cases: NaNs, infs, zeros, denormalised\e[m
  56 \e[1mdiff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py\e[m
  57 \e[1mindex 2a06893..fa23eac 100644\e[m
  58 \e[1m--- a/src/add/test_buf_pipe.py\e[m
  59 \e[1m+++ b/src/add/test_buf_pipe.py\e[m
  60 \e[36m@@ -1,6 +1,6 @@\e[m
  61  from nmigen import Module, Signal\e[m
  62  from nmigen.compat.sim import run_simulation\e[m
  63 \e[31m-from example_buf_pipe import BufPipe\e[m
  64 \e[32m+\e[m\e[32mfrom example_buf_pipe import ExampleBufPipe\e[m
  65  from random import randint\e[m
  66  \e[m
  67  \e[m
  68 \e[36m@@ -171,7 +171,7 @@\e[m \e[mdef testbench4(dut):\e[m
  69                  break\e[m
  70  \e[m
  71  \e[m
  72 \e[31m-class BufPipe2:\e[m
  73 \e[32m+\e[m\e[32mclass ExampleBufPipe2:\e[m
  74      """\e[m
  75          connect these:  ------|---------------|\e[m
  76                                v               v\e[m
  77 \e[36m@@ -180,8 +180,8 @@\e[m \e[mclass BufPipe2:\e[m
  78          stage.i_data   >>in  pipe1 o_data   out>> stage.i_data   >>in  pipe2\e[m
  79      """\e[m
  80      def __init__(self):\e[m
  81 \e[31m-        self.pipe1 = BufPipe()\e[m
  82 \e[31m-        self.pipe2 = BufPipe()\e[m
  83 \e[32m+\e[m\e[32m        self.pipe1 = ExampleBufPipe()\e[m
  84 \e[32m+\e[m\e[32m        self.pipe2 = ExampleBufPipe()\e[m
  85  \e[m
  86          # input\e[m
  87          self.i_p_valid = Signal()    # >>in - comes in from PREVIOUS stage\e[m
  88 \e[36m@@ -217,18 +217,18 @@\e[m \e[mclass BufPipe2:\e[m
  89  \e[m
  90  if __name__ == '__main__':\e[m
  91      print ("test 1")\e[m
  92 \e[31m-    dut = BufPipe()\e[m
  93 \e[32m+\e[m\e[32m    dut = ExampleBufPipe()\e[m
  94      run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")\e[m
  95  \e[m
  96      print ("test 2")\e[m
  97 \e[31m-    dut = BufPipe2()\e[m
  98 \e[32m+\e[m\e[32m    dut = ExampleBufPipe2()\e[m
  99      run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")\e[m
 100  \e[m
 101      print ("test 3")\e[m
 102 \e[31m-    dut = BufPipe()\e[m
 103 \e[32m+\e[m\e[32m    dut = ExampleBufPipe()\e[m
 104      test = Test3(dut)\e[m
 105      run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")\e[m
 106  \e[m
 107      print ("test 4")\e[m
 108 \e[31m-    dut = BufPipe2()\e[m
 109 \e[32m+\e[m\e[32m    dut = ExampleBufPipe2()\e[m
 110      run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")\e[m
 111 \e[1mdiff --git a/src/add/test_inputgroup.py b/src/add/test_inputgroup.py\e[m
 112 \e[1mindex ca8523d..bb68861 100644\e[m
 113 \e[1m--- a/src/add/test_inputgroup.py\e[m
 114 \e[1m+++ b/src/add/test_inputgroup.py\e[m
 115 \e[36m@@ -99,9 +99,81 @@\e[m \e[mdef testbench(dut):\e[m
 116      assert out_mid == 3, "out mid %d" % out_mid\e[m
 117  \e[m
 118  \e[m
 119 \e[32m+\e[m\e[32mclass InputTest:\e[m
 120 \e[32m+\e[m\e[32m    def __init__(self, dut):\e[m
 121 \e[32m+\e[m\e[32m        self.dut = dut\e[m
 122 \e[32m+\e[m\e[32m        self.di = {}\e[m
 123 \e[32m+\e[m\e[32m        self.do = {}\e[m
 124 \e[32m+\e[m\e[32m        self.tlen = 10\e[m
 125 \e[32m+\e[m\e[32m        for mid in range(dut.num_rows):\e[m
 126 \e[32m+\e[m\e[32m            self.di[mid] = {}\e[m
 127 \e[32m+\e[m\e[32m            self.do[mid] = {}\e[m
 128 \e[32m+\e[m\e[32m            for i in range(self.tlen):\e[m
 129 \e[32m+\e[m\e[32m                self.di[mid][i] = randint(0, 100)\e[m
 130 \e[32m+\e[m\e[32m                self.do[mid][i] = self.di[mid][i]\e[m
 131 \e[32m+\e[m
 132 \e[32m+\e[m\e[32m    def send(self, mid):\e[m
 133 \e[32m+\e[m\e[32m        for i in range(self.tlen):\e[m
 134 \e[32m+\e[m\e[32m            op2 = self.di[mid][i]\e[m
 135 \e[32m+\e[m\e[32m            rs = dut.rs[mid]\e[m
 136 \e[32m+\e[m\e[32m            ack = yield rs.ack\e[m
 137 \e[32m+\e[m\e[32m            while not ack:\e[m
 138 \e[32m+\e[m\e[32m                yield\e[m
 139 \e[32m+\e[m\e[32m                ack = yield rs.ack\e[m
 140 \e[32m+\e[m\e[32m            yield rs.in_op[0].eq(i)\e[m
 141 \e[32m+\e[m\e[32m            yield rs.in_op[1].eq(op2)\e[m
 142 \e[32m+\e[m\e[32m            yield rs.stb.eq(0b11) # strobe indicate 1st op ready\e[m
 143 \e[32m+\e[m\e[32m            ack = yield rs.ack\e[m
 144 \e[32m+\e[m\e[32m            while ack:\e[m
 145 \e[32m+\e[m\e[32m                yield\e[m
 146 \e[32m+\e[m\e[32m                ack = yield rs.ack\e[m
 147 \e[32m+\e[m\e[32m            yield rs.stb.eq(0)\e[m
 148 \e[32m+\e[m
 149 \e[32m+\e[m\e[32m            # wait random period of time before queueing another value\e[m
 150 \e[32m+\e[m\e[32m            for i in range(randint(0, 12)):\e[m
 151 \e[32m+\e[m\e[32m                yield\e[m
 152 \e[32m+\e[m
 153 \e[32m+\e[m\e[32m    def recv(self):\e[m
 154 \e[32m+\e[m\e[32m        while True:\e[m
 155 \e[32m+\e[m\e[32m            stb = yield dut.out_op.stb\e[m
 156 \e[32m+\e[m\e[32m            yield dut.out_op.ack.eq(0)\e[m
 157 \e[32m+\e[m\e[32m            while not stb:\e[m
 158 \e[32m+\e[m\e[32m                yield\e[m
 159 \e[32m+\e[m\e[32m                stb = yield dut.out_op.stb\e[m
 160 \e[32m+\e[m
 161 \e[32m+\e[m\e[32m            yield dut.out_op.ack.eq(1)\e[m
 162 \e[32m+\e[m\e[32m            stb = yield dut.out_op.stb\e[m
 163 \e[32m+\e[m\e[32m            while stb:\e[m
 164 \e[32m+\e[m\e[32m                yield\e[m
 165 \e[32m+\e[m\e[32m                stb = yield dut.out_op.stb\e[m
 166 \e[32m+\e[m\e[32m            mid = yield dut.mid\e[m
 167 \e[32m+\e[m\e[32m            out_i = yield dut.out_op.v[0]\e[m
 168 \e[32m+\e[m\e[32m            out_v = yield dut.out_op.v[1]\e[m
 169 \e[32m+\e[m
 170 \e[32m+\e[m\e[32m            # see if this output has occurred already, delete it if it has\e[m
 171 \e[32m+\e[m\e[32m            assert out_i in self.do[mid]\e[m
 172 \e[32m+\e[m\e[32m            assert self.do[mid][out_i] == out_v\e[m
 173 \e[32m+\e[m\e[32m            del self.do[mid][out_i]\e[m
 174 \e[32m+\e[m
 175 \e[32m+\e[m\e[32m            # check if there's any more outputs\e[m
 176 \e[32m+\e[m\e[32m            zerolen = True\e[m
 177 \e[32m+\e[m\e[32m            for (k, v) in self.do.items():\e[m
 178 \e[32m+\e[m\e[32m                if v:\e[m
 179 \e[32m+\e[m\e[32m                    zerolen = False\e[m
 180 \e[32m+\e[m\e[32m            if zerolen:\e[m
 181 \e[32m+\e[m\e[32m                break\e[m
 182 \e[32m+\e[m
 183  if __name__ == '__main__':\e[m
 184      dut = InputGroup(width=32)\e[m
 185      vl = rtlil.convert(dut, ports=dut.ports())\e[m
 186      with open("test_inputgroup.il", "w") as f:\e[m
 187          f.write(vl)\e[m
 188      run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")\e[m
 189 \e[32m+\e[m
 190 \e[32m+\e[m\e[32m    dut = InputGroup(width=16)\e[m
 191 \e[32m+\e[m\e[32m    test = InputTest(dut)\e[m
 192 \e[32m+\e[m\e[32m    run_simulation(dut, [test.send(3), test.send(2),\e[m
 193 \e[32m+\e[m\e[32m                         test.send(1), test.send(0),\e[m
 194 \e[32m+\e[m\e[32m                  \e[1mdiff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py\e[m
 195 \e[1mindex 2604262..00eecc3 100644\e[m
 196 \e[1m--- a/src/add/example_buf_pipe.py\e[m
 197 \e[1m+++ b/src/add/example_buf_pipe.py\e[m
 198 \e[36m@@ -203,7 +203,7 @@\e[m \e[mclass BufferedPipeline:\e[m
 199                 ]\e[m
 200  \e[m
 201  \e[m
 202 \e[31m-class BufPipe(BufferedPipeline):\e[m
 203 \e[32m+\e[m\e[32mclass ExampleBufPipe(BufferedPipeline):\e[m
 204  \e[m
 205      def __init__(self):\e[m
 206          BufferedPipeline.__init__(self)\e[m
 207 \e[1mdiff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py\e[m
 208 \e[1mindex eb0c935..e074c5c 100644\e[m
 209 \e[1m--- a/src/add/nmigen_div_experiment.py\e[m
 210 \e[1m+++ b/src/add/nmigen_div_experiment.py\e[m
 211 \e[36m@@ -6,7 +6,7 @@\e[m \e[mfrom nmigen import Module, Signal, Const, Cat\e[m
 212  from nmigen.cli import main, verilog\e[m
 213  \e[m
 214  from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase\e[m
 215 \e[31m-from nmigen_add_experiment import FPState\e[m
 216 \e[32m+\e[m\e[32mfrom nmigen_add_experiment import FPState, FPGetOp\e[m
 217  \e[m
 218  class Div:\e[m
 219      def __init__(self, width):\e[m
 220 \e[36m@@ -66,14 +66,26 @@\e[m \e[mclass FPDIV(FPBase):\e[m
 221              # ******\e[m
 222              # gets operand a\e[m
 223  \e[m
 224 \e[32m+\e[m\e[32m            geta = FPGetOp("get_a", "get_b", self.in_a, self.width)\e[m
 225 \e[32m+\e[m\e[32m            geta.setup(m, self.in_a)\e[m
 226 \e[32m+\e[m
 227              with m.State("get_a"):\e[m
 228 \e[31m-                self.get_op(m, self.in_a, a, "get_b")\e[m
 229 \e[32m+\e[m\e[32m                geta.action(m)\e[m
 230 \e[32m+\e[m\e[32m                with m.If(geta.out_decode):\e[m
 231 \e[32m+\e[m\e[32m                    m.d.sync += a.decode(self.in_a.v)\e[m
 232 \e[32m+\e[m\e[32m                #self.get_op(m, self.in_a, a, "get_b")\e[m
 233  \e[m
 234              # ******\e[m
 235              # gets operand b\e[m
 236  \e[m
 237 \e[32m+\e[m\e[32m            getb = FPGetOp("get_b", "special_cases", self.in_b, self.width)\e[m
 238 \e[32m+\e[m\e[32m            getb.setup(m, self.in_b)\e[m
 239 \e[32m+\e[m
 240              with m.State("get_b"):\e[m
 241 \e[31m-                self.get_op(m, self.in_b, b, "special_cases")\e[m
 242 \e[32m+\e[m\e[32m                getb.action(m)\e[m
 243 \e[32m+\e[m\e[32m                with m.If(getb.out_decode):\e[m
 244 \e[32m+\e[m\e[32m                    m.d.sync += b.decode(self.in_b.v)\e[m
 245 \e[32m+\e[m\e[32m                #self.get_op(m, self.in_b, b, "special_cases")\e[m
 246  \e[m
 247              # ******\e[m
 248              # special cases: NaNs, infs, zeros, denormalised\e[m
 249 \e[1mdiff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py\e[m
 250 \e[1mindex 2a06893..fa23eac 100644\e[m
 251 \e[1m--- a/src/add/test_buf_pipe.py\e[m
 252 \e[1m+++ b/src/add/test_buf_pipe.py\e[m
 253 \e[36m@@ -1,6 +1,6 @@\e[m
 254  from nmigen import Module, Signal\e[m
 255  from nmigen.compat.sim import run_simulation\e[m
 256 \e[31m-from example_buf_pipe import BufPipe\e[m
 257 \e[32m+\e[m\e[32mfrom example_buf_pipe import ExampleBufPipe\e[m
 258  from random import randint\e[m
 259  \e[m
 260  \e[m
 261 \e[36m@@ -171,7 +171,7 @@\e[m \e[mdef testbench4(dut):\e[m
 262                  break\e[m
 263  \e[m
 264  \e[m
 265 \e[31m-class BufPipe2:\e[m
 266 \e[32m+\e[m\e[32mclass ExampleBufPipe2:\e[m
 267      """\e[m
 268          connect these:  ------|---------------|\e[m
 269                                v               v\e[m
 270 \e[36m@@ -180,8 +180,8 @@\e[m \e[mclass BufPipe2:\e[m
 271          stage.i_data   >>in  pipe1 o_data   out>> stage.i_data   >>in  pipe2\e[m
 272      """\e[m
 273      def __init__(self):\e[m
 274 \e[31m-        self.pipe1 = BufPipe()\e[m
 275 \e[31m-        self.pipe2 = BufPipe()\e[m
 276 \e[32m+\e[m\e[32m        self.pipe1 = ExampleBufPipe()\e[m
 277 \e[32m+\e[m\e[32m        self.pipe2 = ExampleBufPipe()\e[m
 278  \e[m
 279          # input\e[m
 280          self.i_p_valid = Signal()    # >>in - comes in from PREVIOUS stage\e[m
 281 \e[36m@@ -217,18 +217,18 @@\e[m \e[mclass BufPipe2:\e[m
 282  \e[m
 283  if __name__ == '__main__':\e[m
 284      print ("test 1")\e[m
 285 \e[31m-    dut = BufPipe()\e[m
 286 \e[32m+\e[m\e[32m    dut = ExampleBufPipe()\e[m
 287      run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")\e[m
 288  \e[m
 289      print ("test 2")\e[m
 290 \e[31m-    dut = BufPipe2()\e[m
 291 \e[32m+\e[m\e[32m    dut = ExampleBufPipe2()\e[m
 292      run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")\e[m
 293  \e[m
 294      print ("test 3")\e[m
 295 \e[31m-    dut = BufPipe()\e[m
 296 \e[32m+\e[m\e[32m    dut = ExampleBufPipe()\e[m
 297      test = Test3(dut)\e[m
 298      run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")\e[m
 299  \e[m
 300      print ("test 4")\e[m
 301 \e[31m-    dut = BufPipe2()\e[m
 302 \e[32m+\e[m\e[32m    dut = ExampleBufPipe2()\e[m
 303      run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")\e[m
 304 \e[1mdiff --git a/src/add/test_inputgroup.py b/src/add/test_inputgroup.py\e[m
 305 \e[1mindex ca8523d..bb68861 100644\e[m
 306 \e[1m--- a/src/add/test_inputgroup.py\e[m
 307 \e[1m+++ b/src/add/test_inputgroup.py\e[m
 308 \e[36m@@ -99,9 +99,81 @@\e[m \e[mdef testbench(dut):\e[m
 309      assert out_mid == 3, "out mid %d" % out_mid\e[m
 310  \e[m
 311  \e[m
 312 \e[32m+\e[m\e[32mclass InputTest:\e[m
 313 \e[32m+\e[m\e[32m    def __init__(self, dut):\e[m
 314 \e[32m+\e[m\e[32m        self.dut = dut\e[m
 315 \e[32m+\e[m\e[32m        self.di = {}\e[m
 316 \e[32m+\e[m\e[32m        self.do = {}\e[m
 317 \e[32m+\e[m\e[32m        self.tlen = 10\e[m
 318 \e[32m+\e[m\e[32m        for mid in range(dut.num_rows):\e[m
 319 \e[32m+\e[m\e[32m            self.di[mid] = {}\e[m
 320 \e[32m+\e[m\e[32m            self.do[mid] = {}\e[m
 321 \e[32m+\e[m\e[32m            for i in range(self.tlen):\e[m
 322 \e[32m+\e[m\e[32m                self.di[mid][i] = randint(0, 100)\e[m
 323 \e[32m+\e[m\e[32m                self.do[mid][i] = self.di[mid][i]\e[m
 324 \e[32m+\e[m
 325 \e[32m+\e[m\e[32m    def send(self, mid):\e[m
 326 \e[32m+\e[m\e[32m        for i in range(self.tlen):\e[m
 327 \e[32m+\e[m\e[32m            op2 = self.di[mid][i]\e[m
 328 \e[32m+\e[m\e[32m            rs = dut.rs[mid]\e[m
 329 \e[32m+\e[m\e[32m            ack = yield rs.ack\e[m
 330 \e[32m+\e[m\e[32m            while not ack:\e[m
 331 \e[32m+\e[m\e[32m                yield\e[m
 332 \e[32m+\e[m\e[32m                ack = yield rs.ack\e[m
 333 \e[32m+\e[m\e[32m            yield rs.in_op[0].eq(i)\e[m
 334 \e[32m+\e[m\e[32m            yield rs.in_op[1].eq(op2)\e[m
 335 \e[32m+\e[m\e[32m            yield rs.stb.eq(0b11) # strobe indicate 1st op ready\e[m
 336 \e[32m+\e[m\e[32m            ack = yield rs.ack\e[m
 337 \e[32m+\e[m\e[32m            while ack:\e[m
 338 \e[32m+\e[m\e[32m                yield\e[m
 339 \e[32m+\e[m\e[32m                ack = yield rs.ack\e[m
 340 \e[32m+\e[m\e[32m            yield rs.stb.eq(0)\e[m
 341 \e[32m+\e[m
 342 \e[32m+\e[m\e[32m            # wait random period of time before queueing another value\e[m
 343 \e[32m+\e[m\e[32m            for i in range(randint(0, 12)):\e[m
 344 \e[32m+\e[m\e[32m                yield\e[m
 345 \e[32m+\e[m
 346 \e[32m+\e[m\e[32m    def recv(self):\e[m
 347 \e[32m+\e[m\e[32m        while True:\e[m
 348 \e[32m+\e[m\e[32m            stb = yield dut.out_op.stb\e[m
 349 \e[32m+\e[m\e[32m            yield dut.out_op.ack.eq(0)\e[m
 350 \e[32m+\e[m\e[32m            while not stb:\e[m
 351 \e[32m+\e[m\e[32m                yield\e[m
 352 \e[32m+\e[m\e[32m                stb = yield dut.out_op.stb\e[m
 353 \e[32m+\e[m
 354 \e[32m+\e[m\e[32m            yield dut.out_op.ack.eq(1)\e[m
 355 \e[32m+\e[m\e[32m            stb = yield dut.out_op.stb\e[m
 356 \e[32m+\e[m\e[32m            while stb:\e[m
 357 \e[32m+\e[m\e[32m                yield\e[m
 358 \e[32m+\e[m\e[32m                stb = yield dut.out_op.stb\e[m
 359 \e[32m+\e[m\e[32m            mid = yield dut.mid\e[m
 360 \e[32m+\e[m\e[32m            out_i = yield dut.out_op.v[0]\e[m
 361 \e[32m+\e[m\e[32m            out_v = yield dut.out_op.v[1]\e[m
 362 \e[32m+\e[m
 363 \e[32m+\e[m\e[32m            # see if this output has occurred already, delete it if it has\e[m
 364 \e[32m+\e[m\e[32m            assert out_i in self.do[mid]\e[m
 365 \e[32m+\e[m\e[32m            assert self.do[mid][out_i] == out_v\e[m
 366 \e[32m+\e[m\e[32m            del self.do[mid][out_i]\e[m
 367 \e[32m+\e[m
 368 \e[32m+\e[m\e[32m            # check if there's any more outputs\e[m
 369 \e[32m+\e[m\e[32m            zerolen = True\e[m
 370 \e[32m+\e[m\e[32m            for (k, v) in self.do.items():\e[m
 371 \e[32m+\e[m\e[32m                if v:\e[m
 372 \e[32m+\e[m\e[32m                    zerolen = False\e[m
 373 \e[32m+\e[m\e[32m            if zerolen:\e[m
 374 \e[32m+\e[m\e[32m                break\e[m
 375 \e[32m+\e[m
 376  if __name__ == '__main__':\e[m
 377      dut = InputGroup(width=32)\e[m
 378      vl = rtlil.convert(dut, ports=dut.ports())\e[m
 379      with open("test_inputgroup.il", "w") as f:\e[m
 380          f.write(vl)\e[m
 381      run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")\e[m
 382 \e[32m+\e[m
 383 \e[32m+\e[m\e[32m    dut = InputGroup(width=16)\e[m
 384 \e[32m+\e[m\e[32m    test = InputTest(dut)\e[m
 385 \e[32m+\e[m\e[32m    run_simulation(dut, [test.send(3), test.send(2),\e[m
 386 \e[32m+\e[m\e[32m                         test.send(1), test.send(0),\e[m
 387 \e[32m+\e[m\e[32m                         test.recv()],\e[m
 388 \e[32m+\e[m\e[32m                   vcd_name="test_inputgroup_parallel.vcd")\e[m
 389 \e[41m+\e[m
 390 \e[1mdiff --git a/src/add/example_buf_pipe.py b/src/add/example_buf_pipe.py\e[m
 391 \e[1mindex 2604262..00eecc3 100644\e[m
 392 \e[1m--- a/src/add/example_buf_pipe.py\e[m
 393 \e[1m+++ b/src/add/example_buf_pipe.py\e[m
 394 \e[36m@@ -203,7 +203,7 @@\e[m \e[mclass BufferedPipeline:\e[m
 395                 ]\e[m
 396  \e[m
 397  \e[m
 398 \e[31m-class BufPipe(BufferedPipeline):\e[m
 399 \e[32m+\e[m\e[32mclass ExampleBufPipe(BufferedPipeline):\e[m
 400  \e[m
 401      def __init__(self):\e[m
 402          BufferedPipeline.__init__(self)\e[m
 403 \e[1mdiff --git a/src/add/fmul.py b/src/add/fmul.py\e[m
 404 \e[1mindex 130d49e..5b6da94 100644\e[m
 405 \e[1m--- a/src/add/fmul.py\e[m
 406 \e[1m+++ b/src/add/fmul.py\e[m
 407 \e[36m@@ -2,7 +2,8 @@\e[m \e[mfrom nmigen import Module, Signal, Cat, Mux, Array, Const\e[m
 408  from nmigen.cli import main, verilog\e[m
 409  \e[m
 410  from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase\e[m
 411 \e[31m-from nmigen_add_experiment import FPState\e[m
 412 \e[32m+\e[m\e[32m+from nmigen_add_experiment import FPState, FPGetOp\e[m
 413 \e[32m+\e[m
 414  \e[m
 415  class FPMUL(FPBase):\e[m
 416  \e[m
 417 \e[1mdiff --git a/src/add/nmigen_div_experiment.py b/src/add/nmigen_div_experiment.py\e[m
 418 \e[1mindex eb0c935..e074c5c 100644\e[m
 419 \e[1m--- a/src/add/nmigen_div_experiment.py\e[m
 420 \e[1m+++ b/src/add/nmigen_div_experiment.py\e[m
 421 \e[36m@@ -6,7 +6,7 @@\e[m \e[mfrom nmigen import Module, Signal, Const, Cat\e[m
 422  from nmigen.cli import main, verilog\e[m
 423  \e[m
 424  from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase\e[m
 425 \e[31m-from nmigen_add_experiment import FPState\e[m
 426 \e[32m+\e[m\e[32mfrom nmigen_add_experiment import FPState, FPGetOp\e[m
 427  \e[m
 428  class Div:\e[m
 429      def __init__(self, width):\e[m
 430 \e[36m@@ -66,14 +66,26 @@\e[m \e[mclass FPDIV(FPBase):\e[m
 431              # ******\e[m
 432              # gets operand a\e[m
 433  \e[m
 434 \e[32m+\e[m\e[32m            geta = FPGetOp("get_a", "get_b", self.in_a, self.width)\e[m
 435 \e[32m+\e[m\e[32m            geta.setup(m, self.in_a)\e[m
 436 \e[32m+\e[m
 437              with m.State("get_a"):\e[m
 438 \e[31m-                self.get_op(m, self.in_a, a, "get_b")\e[m
 439 \e[32m+\e[m\e[32m                geta.action(m)\e[m
 440 \e[32m+\e[m\e[32m                with m.If(geta.out_decode):\e[m
 441 \e[32m+\e[m\e[32m                    m.d.sync += a.decode(self.in_a.v)\e[m
 442 \e[32m+\e[m\e[32m                #self.get_op(m, self.in_a, a, "get_b")\e[m
 443  \e[m
 444              # ******\e[m
 445              # gets operand b\e[m
 446  \e[m
 447 \e[32m+\e[m\e[32m            getb = FPGetOp("get_b", "special_cases", self.in_b, self.width)\e[m
 448 \e[32m+\e[m\e[32m            getb.setup(m, self.in_b)\e[m
 449 \e[32m+\e[m
 450              with m.State("get_b"):\e[m
 451 \e[31m-                self.get_op(m, self.in_b, b, "special_cases")\e[m
 452 \e[32m+\e[m\e[32m                getb.action(m)\e[m
 453 \e[32m+\e[m\e[32m                with m.If(getb.out_decode):\e[m
 454 \e[32m+\e[m\e[32m                    m.d.sync += b.decode(self.in_b.v)\e[m
 455 \e[32m+\e[m\e[32m                #self.get_op(m, self.in_b, b, "special_cases")\e[m
 456  \e[m
 457              # ******\e[m
 458              # special cases: NaNs, infs, zeros, denormalised\e[m
 459 \e[1mdiff --git a/src/add/test_buf_pipe.py b/src/add/test_buf_pipe.py\e[m
 460 \e[1mindex 2a06893..fa23eac 100644\e[m
 461 \e[1m--- a/src/add/test_buf_pipe.py\e[m
 462 \e[1m+++ b/src/add/test_buf_pipe.py\e[m
 463 \e[36m@@ -1,6 +1,6 @@\e[m
 464  from nmigen import Module, Signal\e[m
 465  from nmigen.compat.sim import run_simulation\e[m
 466 \e[31m-from example_buf_pipe import BufPipe\e[m
 467 \e[32m+\e[m\e[32mfrom example_buf_pipe import ExampleBufPipe\e[m
 468  from random import randint\e[m
 469  \e[m
 470  \e[m
 471 \e[36m@@ -171,7 +171,7 @@\e[m \e[mdef testbench4(dut):\e[m
 472                  break\e[m
 473  \e[m
 474  \e[m
 475 \e[31m-class BufPipe2:\e[m
 476 \e[32m+\e[m\e[32mclass ExampleBufPipe2:\e[m
 477      """\e[m
 478          connect these:  ------|---------------|\e[m
 479                                v               v\e[m
 480 \e[36m@@ -180,8 +180,8 @@\e[m \e[mclass BufPipe2:\e[m
 481          stage.i_data   >>in  pipe1 o_data   out>> stage.i_data   >>in  pipe2\e[m
 482      """\e[m
 483      def __init__(self):\e[m
 484 \e[31m-        self.pipe1 = BufPipe()\e[m
 485 \e[31m-        self.pipe2 = BufPipe()\e[m
 486 \e[32m+\e[m\e[32m        self.pipe1 = ExampleBufPipe()\e[m
 487 \e[32m+\e[m\e[32m        self.pipe2 = ExampleBufPipe()\e[m
 488  \e[m
 489          # input\e[m
 490          self.i_p_valid = Signal()    # >>in - comes in from PREVIOUS stage\e[m
 491 \e[36m@@ -217,18 +217,18 @@\e[m \e[mclass BufPipe2:\e[m
 492  \e[m
 493  if __name__ == '__main__':\e[m
 494      print ("test 1")\e[m
 495 \e[31m-    dut = BufPipe()\e[m
 496 \e[32m+\e[m\e[32m    dut = ExampleBufPipe()\e[m
 497      run_simulation(dut, testbench(dut), vcd_name="test_bufpipe.vcd")\e[m
 498  \e[m
 499      print ("test 2")\e[m
 500 \e[31m-    dut = BufPipe2()\e[m
 501 \e[32m+\e[m\e[32m    dut = ExampleBufPipe2()\e[m
 502      run_simulation(dut, testbench2(dut), vcd_name="test_bufpipe2.vcd")\e[m
 503  \e[m
 504      print ("test 3")\e[m
 505 \e[31m-    dut = BufPipe()\e[m
 506 \e[32m+\e[m\e[32m    dut = ExampleBufPipe()\e[m
 507      test = Test3(dut)\e[m
 508      run_simulation(dut, [test.send, test.rcv], vcd_name="test_bufpipe3.vcd")\e[m
 509  \e[m
 510      print ("test 4")\e[m
 511 \e[31m-    dut = BufPipe2()\e[m
 512 \e[32m+\e[m\e[32m    dut = ExampleBufPipe2()\e[m
 513      run_simulation(dut, testbench4(dut), vcd_name="test_bufpipe4.vcd")\e[m
 514 \e[1mdiff --git a/src/add/test_inputgroup.py b/src/add/test_inputgroup.py\e[m
 515 \e[1mindex ca8523d..bb68861 100644\e[m
 516 \e[1m--- a/src/add/test_inputgroup.py\e[m
 517 \e[1m+++ b/src/add/test_inputgroup.py\e[m
 518 \e[36m@@ -99,9 +99,81 @@\e[m \e[mdef testbench(dut):\e[m
 519      assert out_mid == 3, "out mid %d" % out_mid\e[m
 520  \e[m
 521  \e[m
 522 \e[32m+\e[m\e[32mclass InputTest:\e[m
 523 \e[32m+\e[m\e[32m    def __init__(self, dut):\e[m
 524 \e[32m+\e[m\e[32m        self.dut = dut\e[m
 525 \e[32m+\e[m\e[32m        self.di = {}\e[m
 526 \e[32m+\e[m\e[32m        self.do = {}\e[m
 527 \e[32m+\e[m\e[32m        self.tlen = 10\e[m
 528 \e[32m+\e[m\e[32m        for mid in range(dut.num_rows):\e[m
 529 \e[32m+\e[m\e[32m            self.di[mid] = {}\e[m
 530 \e[32m+\e[m\e[32m            self.do[mid] = {}\e[m
 531 \e[32m+\e[m\e[32m            for i in range(self.tlen):\e[m
 532 \e[32m+\e[m\e[32m                self.di[mid][i] = randint(0, 100)\e[m
 533 \e[32m+\e[m\e[32m                self.do[mid][i] = self.di[mid][i]\e[m
 534 \e[32m+\e[m
 535 \e[32m+\e[m\e[32m    def send(self, mid):\e[m
 536 \e[32m+\e[m\e[32m        for i in range(self.tlen):\e[m
 537 \e[32m+\e[m\e[32m            op2 = self.di[mid][i]\e[m
 538 \e[32m+\e[m\e[32m            rs = dut.rs[mid]\e[m
 539 \e[32m+\e[m\e[32m            ack = yield rs.ack\e[m
 540 \e[32m+\e[m\e[32m            while not ack:\e[m
 541 \e[32m+\e[m\e[32m                yield\e[m
 542 \e[32m+\e[m\e[32m                ack = yield rs.ack\e[m
 543 \e[32m+\e[m\e[32m            yield rs.in_op[0].eq(i)\e[m
 544 \e[32m+\e[m\e[32m            yield rs.in_op[1].eq(op2)\e[m
 545 \e[32m+\e[m\e[32m            yield rs.stb.eq(0b11) # strobe indicate 1st op ready\e[m
 546 \e[32m+\e[m\e[32m            ack = yield rs.ack\e[m
 547 \e[32m+\e[m\e[32m            while ack:\e[m
 548 \e[32m+\e[m\e[32m                yield\e[m
 549 \e[32m+\e[m\e[32m                ack = yield rs.ack\e[m
 550 \e[32m+\e[m\e[32m            yield rs.stb.eq(0)\e[m
 551 \e[32m+\e[m
 552 \e[32m+\e[m\e[32m            # wait random period of time before queueing another value\e[m
 553 \e[32m+\e[m\e[32m            for i in range(randint(0, 12)):\e[m
 554 \e[32m+\e[m\e[32m                yield\e[m
 555 \e[32m+\e[m
 556 \e[32m+\e[m\e[32m    def recv(self):\e[m
 557 \e[32m+\e[m\e[32m        while True:\e[m
 558 \e[32m+\e[m\e[32m            stb = yield dut.out_op.stb\e[m
 559 \e[32m+\e[m\e[32m            yield dut.out_op.ack.eq(0)\e[m
 560 \e[32m+\e[m\e[32m            while not stb:\e[m
 561 \e[32m+\e[m\e[32m                yield\e[m
 562 \e[32m+\e[m\e[32m                stb = yield dut.out_op.stb\e[m
 563 \e[32m+\e[m
 564 \e[32m+\e[m\e[32m            yield dut.out_op.ack.eq(1)\e[m
 565 \e[32m+\e[m\e[32m            stb = yield dut.out_op.stb\e[m
 566 \e[32m+\e[m\e[32m            while stb:\e[m
 567 \e[32m+\e[m\e[32m                yield\e[m
 568 \e[32m+\e[m\e[32m                stb = yield dut.out_op.stb\e[m
 569 \e[32m+\e[m\e[32m            mid = yield dut.mid\e[m
 570 \e[32m+\e[m\e[32m            out_i = yield dut.out_op.v[0]\e[m
 571 \e[32m+\e[m\e[32m            out_v = yield dut.out_op.v[1]\e[m
 572 \e[32m+\e[m
 573 \e[32m+\e[m\e[32m            # see if this output has occurred already, delete it if it has\e[m
 574 \e[32m+\e[m\e[32m            assert out_i in self.do[mid]\e[m
 575 \e[32m+\e[m\e[32m            assert self.do[mid][out_i] == out_v\e[m
 576 \e[32m+\e[m\e[32m            del self.do[mid][out_i]\e[m
 577 \e[32m+\e[m
 578 \e[32m+\e[m\e[32m            # check if there's any more outputs\e[m
 579 \e[32m+\e[m\e[32m            zerolen = True\e[m
 580 \e[32m+\e[m\e[32m            for (k, v) in self.do.items():\e[m
 581 \e[32m+\e[m\e[32m                if v:\e[m
 582 \e[32m+\e[m\e[32m                    zerolen = False\e[m
 583 \e[32m+\e[m\e[32m            if zerolen:\e[m
 584 \e[32m+\e[m\e[32m                break\e[m
 585 \e[32m+\e[m
 586  if __name__ == '__main__':\e[m
 587      dut = InputGroup(width=32)\e[m
 588      vl = rtlil.convert(dut, ports=dut.ports())\e[m
 589      with open("test_inputgroup.il", "w") as f:\e[m
 590          f.write(vl)\e[m
 591      run_simulation(dut, testbench(dut), vcd_name="test_inputgroup.vcd")\e[m
 592 \e[32m+\e[m
 593 \e[32m+\e[m\e[32m    dut = InputGroup(width=16)\e[m
 594 \e[32m+\e[m\e[32m    test = InputTest(dut)\e[m
 595 \e[32m+\e[m\e[32m    run_simulation(dut, [test.send(3), test.send(2),\e[m
 596 \e[32m+\e[m\e[32m                         test.send(1), test.send(0),\e[m
 597 \e[32m+\e[m\e[32m                         test.recv()],\e[m
 598 \e[32m+\e[m\e[32m                   vcd_name="test_inputgroup_parallel.vcd")\e[m
 599 \e[41m+\e[m