git diff a36447fc^

   1 \e[33mcommit f02c6f4bbf463472d3d68e52bd5ededd3c937f58\e[m\e[33m (\e[m\e[1;36mHEAD -> \e[m\e[1;32mmaster\e[m\e[33m, \e[m\e[1;31morigin/master\e[m\e[33m, \e[m\e[1;31morigin/HEAD\e[m\e[33m)\e[m
   2 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 Date:   Fri Mar 15 12:37:14 2019 +0000
   4
   5     add parallel InputGroup unit test
   6
   7 \e[33mcommit b13c8a7a5368a53bedc71e5b8969c721103144c4\e[m
   8 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   9 Date:   Fri Mar 15 10:59:44 2019 +0000
  10
  11     rename BufPipe example to ExampleBufPipe
  12
  13 \e[33mcommit a36447fcd4d4f049b7127e1fc02dc1390d05fa75\e[m
  14 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  15 Date:   Fri Mar 15 09:59:07 2019 +0000
  16
  17     instantiate 2 FPGetOp instances and use them.  a little awkwardly.
  18
  19 \e[33mcommit 092d2d78fa19a5c73863cb89c5d680cbd2afe027\e[m
  20 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  21 Date:   Fri Mar 15 09:33:44 2019 +0000
  22
  23     update comments
  24
  25 \e[33mcommit 8989cd3452869d43a8a3655acffd3eb3288f5d9a\e[m
  26 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  27 Date:   Fri Mar 15 09:22:58 2019 +0000
  28
  29     remove unnecessary code
  30
  31 \e[33mcommit b90c533476affe63a34292bfe54dde62a105bed8\e[m
  32 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  33 Date:   Fri Mar 15 08:47:21 2019 +0000
  34
  35     add extra comment block explaining pipe stage example
  36
  37 \e[33mcommit 28a8ede4a797a76e83410fb42a9aaa02b44fb2ef\e[m
  38 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  39 Date:   Fri Mar 15 08:37:18 2019 +0000
  40
  41     inverted busy signal and named it "ready"
  42
  43 \e[33mcommit 0ebc09c0a7b74e4807ccdb60ca0a10cbb605666a\e[m
  44 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  45 Date:   Fri Mar 15 08:29:56 2019 +0000
  46
  47     rename stb to "valid"
  48
  49 \e[33mcommit 0bfbc8ff919f0cd9c7f01b4c711b1b91a53ad480\e[m
  50 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  51 Date:   Fri Mar 15 08:28:18 2019 +0000
  52
  53     create classes for STB/BUSY, split in from out
  54
  55 \e[33mcommit ca218a65dc9af73965a5c4f105a780ed04b588e0\e[m
  56 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  57 Date:   Fri Mar 15 00:31:30 2019 +0000
  58
  59     add use of FPState, not being used yet
  60
  61 \e[33mcommit ce7a1d5c48e987cbfb40236f13b17ffcea55b585\e[m
  62 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  63 Date:   Thu Mar 14 13:32:06 2019 +0000
  64
  65     split pipeline test into 2 functions, one send, one receive
  66
  67 \e[33mcommit 481d00c37b31e7908e624235e6e9c93b12baeebb\e[m
  68 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  69 Date:   Thu Mar 14 06:33:10 2019 +0000
  70
  71     got fpdiv up and running again
  72
  73 \e[33mcommit 286fdefc4bbe8c7b4bb34ae33b513e8bb81b3d7e\e[m
  74 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  75 Date:   Thu Mar 14 05:41:02 2019 +0000
  76
  77     forgot to add submodules
  78
  79 \e[33mcommit 43c53078d577aa33d28ba0eb2af782b7d348a517\e[m
  80 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  81 Date:   Thu Mar 14 05:09:36 2019 +0000
  82
  83     got rounding working again for fmul
  84
  85 \e[33mcommit 892d640f8224e6a52907c6899ab6ab671f5f53af\e[m
  86 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  87 Date:   Thu Mar 14 04:42:53 2019 +0000
  88
  89     remove extra arg from old roundz function
  90
  91 \e[33mcommit ccd4d65a7bd2985edb5547daf7df623cda5ab9da\e[m
  92 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  93 Date:   Thu Mar 14 04:33:01 2019 +0000
  94
  95     make a bit of a mess of the unit tests, getting mul up and running again
  96     taking a copy (sigh) of the old version of check_case and get_case
  97
  98 \e[33mcommit 9b9732e1c96d085bc9c7b696e7c86dd0c4a4ae49\e[m
  99 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 100 Date:   Thu Mar 14 04:17:28 2019 +0000
 101
 102     get roundz working again, needed for mul stage
 103
 104 \e[33mcommit 38452d7fb64752a897b26e1da96a27d3a5979a76\e[m
 105 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 106 Date:   Thu Mar 14 04:16:28 2019 +0000
 107
 108     add new FPNormaliseSingleMod, not tested
 109
 110 \e[33mcommit 3e994c6039c3cce1dbecc6dddd1b6be23af390fb\e[m
 111 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 112 Date:   Thu Mar 14 03:18:06 2019 +0000
 113
 114     start to get fpmul back up and running
 115
 116 \e[33mcommit 5ca9e3ee685a261fbff9998ab37940aa3255b9fa\e[m
 117 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 118 Date:   Thu Mar 14 03:04:33 2019 +0000
 119
 120     replace copy of FPState with import of FPState
 121
 122 \e[33mcommit af3ae7902ba4e5a26556eb4442c8351c95b267a4\e[m
 123 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 124 Date:   Thu Mar 14 02:54:57 2019 +0000
 125
 126     update comments
 127
 128 \e[33mcommit 95cd53141ace92120fccb83a96af96323dea9c0d\e[m
 129 Author: Aleksandar Kostovic <alexandar.kostovic@gmail.com>
 130 Date:   Wed Mar 13 18:39:14 2019 +0100
 131
 132     Started to update fmul.py to new conventions
 133
 134 \e[33mcommit edf77dc7ee9fa94e1ec07e1ae4616e87c9f7298c\e[m
 135 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 136 Date:   Wed Mar 13 12:39:09 2019 +0000
 137
 138     increase data set to throw at pipeline in tests
 139
 140 \e[33mcommit 2ec9fee974fe500ff4e3375d35f6148ef3560e36\e[m
 141 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 142 Date:   Wed Mar 13 11:48:10 2019 +0000
 143
 144     add random-busy, random-send single and dual buffered pipeline tests
 145
 146 \e[33mcommit 1abb4da885f1e66f800c310766924918a3b1474c\e[m
 147 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 148 Date:   Wed Mar 13 11:01:22 2019 +0000
 149
 150     split out actual pipeline stage into separate class
 151
 152 \e[33mcommit 9de2c40d3c1051650dd6f29b2ea5a0bd4e67b366\e[m
 153 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 154 Date:   Wed Mar 13 07:26:23 2019 +0000
 155
 156     add 2 stage buffered pipeline unit test, reduce to 16-bit to make vcd clearer
 157
 158 \e[33mcommit b58c1a8f96dfaa63e89c7f3d7fd65f0fec9c1932\e[m
 159 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 160 Date:   Wed Mar 13 04:26:24 2019 +0000
 161
 162     only process data if the input strobe is valid
 163
 164 \e[33mcommit b32f06d6ed5f6639b929d21453c09dee1296db96\e[m
 165 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 166 Date:   Wed Mar 13 04:24:50 2019 +0000
 167
 168     add in some assertions to check pipe output
 169
 170 \e[33mcommit 14559d0d0edaee06af261a04ed0a33a5bd1e0479\e[m
 171 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 172 Date:   Wed Mar 13 03:49:48 2019 +0000
 173
 174     split out unit test in buf pipe example
 175
 176 \e[33mcommit c10d9619880099356e760c4ae45c8a0b18d1aeac\e[m
 177 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 178 Date:   Wed Mar 13 03:47:49 2019 +0000
 179
 180     combine blocks to add list of statements, add comments
 181
 182 \e[33mcommit c60a4997aa35ebc32e121d401af06d3bfee9c5c3\e[m
 183 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 184 Date:   Wed Mar 13 03:35:41 2019 +0000
 185
 186     update comments
 187
 188 \e[33mcommit e605dd06dae1fb584a25a526125179da8a6eac2e\e[m
 189 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 190 Date:   Wed Mar 13 03:11:05 2019 +0000
 191
 192     store inv-strobe in temp signal
 193
 194 \e[33mcommit 9432c1a8a962879685df5b4810ccf97db439c1a9\e[m
 195 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 196 Date:   Wed Mar 13 03:10:44 2019 +0000
 197
 198     clean up code
 199
 200 \e[33mcommit 5ecfe07d6d3fde658df517ab48bb515dfae32f26\e[m
 201 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 202 Date:   Tue Mar 12 15:14:13 2019 +0000
 203
 204     store processed input in intermediary
 205
 206 \e[33mcommit 0e70fec7c3df1ee97020aa5be6f358c85898a5fb\e[m
 207 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 208 Date:   Tue Mar 12 13:22:20 2019 +0000
 209
 210     add (but comment out) reset signal
 211
 212 \e[33mcommit cfc989aa8b0d4c19a15c6e0d7210dde46bb480e8\e[m
 213 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 214 Date:   Tue Mar 12 13:14:17 2019 +0000
 215
 216     add example buffered pipe
 217
 218 \e[33mcommit e1336d2ad072dc6661c9af1b0460a69ff1bf588f\e[m
 219 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 220 Date:   Tue Mar 12 13:13:33 2019 +0000
 221
 222     add example buffered pipe
 223
 224 \e[33mcommit 289c5cf9f7510a9e9bc3239155db27bdbd982e70\e[m
 225 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 226 Date:   Mon Mar 11 19:09:39 2019 +0000
 227
 228     get InputGroup running
 229
 230 \e[33mcommit 33b30ebf9210e7a3c03d3babc73ad4ed12b8685e\e[m
 231 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 232 Date:   Mon Mar 11 12:54:57 2019 +0000
 233
 234     add inputgroup test
 235
 236 \e[33mcommit bc8abd924298a632e586b34d072c5437844e8aea\e[m
 237 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 238 Date:   Mon Mar 11 12:54:32 2019 +0000
 239
 240     Trigger needs to be combinatorial (saves clock cycles)
 241
 242 \e[33mcommit d0c5c2d71fb122797f6a02a6da30c404c0ff90b9\e[m
 243 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 244 Date:   Mon Mar 11 12:32:48 2019 +0000
 245
 246     return mid as part of ports
 247
 248 \e[33mcommit 9245c808cb817d0054b6c9fd9d510a4a722db308\e[m
 249 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 250 Date:   Mon Mar 11 12:32:09 2019 +0000
 251
 252     whoops, forgot to make input an Array, can use array indexing now
 253
 254 \e[33mcommit 79192af4fd00e42156463bf2a32744a3f4f458ee\e[m
 255 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 256 Date:   Mon Mar 11 11:26:45 2019 +0000
 257
 258     create an FPOps output class to clean up the InputGroup
 259
 260 \e[33mcommit 1fda7bf6bad5c48a295726a9a9cd0df0fc598114\e[m
 261 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 262 Date:   Mon Mar 11 11:15:29 2019 +0000
 263
 264     add capability to pass through operands and muxid to output
 265
 266 \e[33mcommit 3eeb871f5920bdbb365f513440ee3bf57a491e08\e[m
 267 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 268 Date:   Mon Mar 11 09:37:19 2019 +0000
 269
 270     make a start on an InputGroup module
 271
 272 \e[33mcommit dced2d8e93d5653a723fe77eec4f2cf87f004098\e[m
 273 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 274 Date:   Mon Mar 11 08:42:21 2019 +0000
 275
 276     add a multi-input stb/ack module
 277
 278     to be used for acknowledging and passing on multiple inputs once all ready
 279
 280 \e[33mcommit a6e7f74fa24d010999e6963ee33d3e078f83cfd2\e[m
 281 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 282 Date:   Mon Mar 11 07:06:51 2019 +0000
 283
 284     add result array module
 285
 286 \e[33mcommit bc8d3b3d11ae8e748e12bbb0b985d9ba54f11419\e[m
 287 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 288 Date:   Sun Mar 10 08:42:43 2019 +0000
 289
 290     create array of in/outs however set muxid to zero temporarily
 291
 292 \e[33mcommit 93da24dcd72c6a7a39146c4dba6b5a882e7ef6ca\e[m
 293 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 294 Date:   Sun Mar 10 07:05:55 2019 +0000
 295
 296     store fpadd result in putz, next phase: direct to array of output results
 297
 298 \e[33mcommit 9678f15f0c77d58649d1064e5d7268905da16937\e[m
 299 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 300 Date:   Sun Mar 10 03:37:36 2019 +0000
 301
 302     allow code-creation
 303
 304 \e[33mcommit 9926a532bb3fdd1a7715f5ee3b68847e566e4f0b\e[m
 305 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 306 Date:   Sun Mar 10 03:34:38 2019 +0000
 307
 308     create array of in_a, in_b and out_z
 309
 310 \e[33mcommit 52a3d3916b905d3e9e7e7e606c77aa9ab58a4f3d\e[m
 311 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 312 Date:   Sun Mar 10 03:22:31 2019 +0000
 313
 314     move ids to member variable
 315
 316 \e[33mcommit 7522c2b5594486cba0e07df28bb74d0733d0ed1b\e[m
 317 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 318 Date:   Sat Mar 9 11:23:05 2019 +0000
 319
 320     chain add stage 0 and 1 together with align in combinatorial block
 321
 322 \e[33mcommit 5d1234824040d0903048476297a9be850ee08c54\e[m
 323 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 324 Date:   Sat Mar 9 11:11:27 2019 +0000
 325
 326     create combined combinatorial align and add0
 327
 328 \e[33mcommit 677577b32e8323b0265aa16610f278e019692b97\e[m
 329 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 330 Date:   Sat Mar 9 11:01:29 2019 +0000
 331
 332     merge specialcases and denorm into single combinatorial chain
 333
 334 \e[33mcommit ad26042b4e313d8f1273ff8bac9bac317440bffc\e[m
 335 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 336 Date:   Sat Mar 9 10:46:54 2019 +0000
 337
 338     create specialcasesmod setup fn
 339
 340 \e[33mcommit 5efb9e47fa9eb0529c142b175e0937b64de68d91\e[m
 341 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 342 Date:   Sat Mar 9 10:03:49 2019 +0000
 343
 344     whoops forgot self.width
 345
 346 \e[33mcommit 698601cec4a9d46dbc4f0a92b66ad5d50a66bc26\e[m
 347 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 348 Date:   Sat Mar 9 10:03:28 2019 +0000
 349
 350     add comments
 351
 352 \e[33mcommit 2c05d1d4507e0e50e36a02e08a0458b315be0ab3\e[m
 353 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 354 Date:   Sat Mar 9 10:00:37 2019 +0000
 355
 356     move localiseable variables to local function
 357
 358 \e[33mcommit f067330d9c1686e114a93480c3ffb781aac6d6a6\e[m
 359 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 360 Date:   Sat Mar 9 09:54:03 2019 +0000
 361
 362     connect corrections to pack with combinatorial logic
 363
 364 \e[33mcommit f14133ebce3e79e67ff35ff0720b51a3fb6a335c\e[m
 365 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 366 Date:   Sat Mar 9 09:34:04 2019 +0000
 367
 368     connect round directly to corrections with combinatorial logic
 369
 370 \e[33mcommit a641d2526a2d1e2fc7d04b40d41d10e114f0e7f9\e[m
 371 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 372 Date:   Sat Mar 9 09:24:50 2019 +0000
 373
 374     connect normalisation directly to round with combinatorial logic
 375
 376 \e[33mcommit ef144a6f35cf7d9bfc0268d50f1572be1ddf2e13\e[m
 377 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 378 Date:   Sat Mar 9 09:13:47 2019 +0000
 379
 380     big reorganisation
 381
 382     splitting out Normalisation Single/Multi
 383     adding beginnings of combinatorial-chained normalisation thru pack
 384
 385 \e[33mcommit 71d97d936d73e8a47cdcc12d1e0888293c90c41e\e[m
 386 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 387 Date:   Sat Mar 9 07:25:28 2019 +0000
 388
 389     split out into 2 functions, longer and compact fragment
 390
 391 \e[33mcommit 56bd686dd363a532a9b4843c5c8ff710c24a24bc\e[m
 392 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 393 Date:   Sat Mar 9 07:18:47 2019 +0000
 394
 395     move in_t_ack into FPGet2Op setup
 396
 397 \e[33mcommit 0f141d1586b5865638db9626da05c1448578d9aa\e[m
 398 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 399 Date:   Sat Mar 9 07:18:01 2019 +0000
 400
 401     add "compact" option
 402
 403 \e[33mcommit 5e20d7a6fb0f8b623634951b64a932e5f2e97a0f\e[m
 404 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 405 Date:   Fri Mar 8 12:59:11 2019 +0000
 406
 407     main on FPADD not on FPADDBase
 408
 409 \e[33mcommit 4527b5644ba6e6c8d7ee8d1990775ff266011433\e[m
 410 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 411 Date:   Fri Mar 8 12:53:15 2019 +0000
 412
 413     big reorg, got FPADD to work using new FPADDBase
 414
 415 \e[33mcommit 25a892466594952291f03b50c5daf29a1335c11f\e[m
 416 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 417 Date:   Wed Mar 6 21:46:01 2019 +0000
 418
 419     add some comments to FPAddBase
 420
 421 \e[33mcommit f39188c47f81343121785bad1366a831d115a924\e[m
 422 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 423 Date:   Wed Mar 6 12:14:47 2019 +0000
 424
 425     in the middle of rewiring FPADD to use FPADDBase
 426
 427 \e[33mcommit e768533532bb2035e9cbc78e2db86affc694e290\e[m
 428 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 429 Date:   Wed Mar 6 06:09:15 2019 +0000
 430
 431     split out main stages of add to separate class, FPADDBase
 432
 433 \e[33mcommit 63cd263891fb851e2585add543f9138f7d12710d\e[m
 434 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 435 Date:   Wed Mar 6 06:08:20 2019 +0000
 436
 437     add function unit module
 438
 439 \e[33mcommit 3e5ecb581d6b93019e088878231a9d871a2d686b\e[m
 440 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 441 Date:   Wed Mar 6 06:08:09 2019 +0000
 442
 443     correct syntax error
 444
 445 \e[33mcommit cbfd9aa5a65e7c0270e0d9fe1fc1667779a4742b\e[m
 446 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 447 Date:   Tue Mar 5 03:06:04 2019 +0000
 448
 449     add reservation station row module
 450
 451 \e[33mcommit b8d39c3d5295e7fdeb0e769c2bd84fe929457ef0\e[m
 452 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 453 Date:   Tue Mar 5 02:50:36 2019 +0000
 454
 455     add MID testing
 456
 457 \e[33mcommit cd5a425849b29b810b6ff16216296e286f1dcd27\e[m
 458 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 459 Date:   Tue Mar 5 02:36:50 2019 +0000
 460
 461     add id to pack and putz
 462
 463 \e[33mcommit 4a10d39f2cb4eda127034a8f021eee6ccdf6de74\e[m
 464 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 465 Date:   Tue Mar 5 02:33:16 2019 +0000
 466
 467     add id to FPPack
 468
 469 \e[33mcommit 52eb96de2fddee430954899471d10c012b5fd1d2\e[m
 470 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 471 Date:   Tue Mar 5 02:30:20 2019 +0000
 472
 473     add id to FPCorrections
 474
 475 \e[33mcommit 80faa8e2714b5417b40db99294bec8710bb8ec17\e[m
 476 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 477 Date:   Tue Mar 5 02:28:48 2019 +0000
 478
 479     add id to FPRound
 480
 481 \e[33mcommit 8f9071b7d0a205b6dda40da28c358f1e26e007a0\e[m
 482 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 483 Date:   Tue Mar 5 02:26:13 2019 +0000
 484
 485     add id to norm1
 486
 487 \e[33mcommit e3197c61ce5de2cab4b36fe07b913c526844d328\e[m
 488 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 489 Date:   Tue Mar 5 02:24:54 2019 +0000
 490
 491     add id to stage1
 492
 493 \e[33mcommit 3956a968ae847f27b3e46ff805dc75c259e1c544\e[m
 494 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 495 Date:   Tue Mar 5 02:22:19 2019 +0000
 496
 497     add id to stage0
 498
 499 \e[33mcommit 074236f303578939f925f3668c88b7e6cd929c75\e[m
 500 Author: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
 501 Date:   Tue Mar 5 02:18:39 2019 +0000
 502
 503     add id to align
 504
 505 \e[33mcommit 3597dda29683c1b06bd70edc88