src/add/example_buf_pipe.py

   1 """ nmigen implementation of buffered pipeline stage, based on zipcpu:
   2     https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
   3
   4     this module requires quite a bit of thought to understand how it works
   5     (and why it is needed in the first place).  reading the above is
   6     *strongly* recommended.
   7
   8     unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
   9     the STB / ACK signals to raise and lower (on separate clocks) before
  10     data may proceeed (thus only allowing one piece of data to proceed
  11     on *ALTERNATE* cycles), the signalling here is a true pipeline
  12     where data will flow on *every* clock when the conditions are right.
  13
  14     input acceptance conditions are when:
  15         * incoming previous-stage strobe (i.p_valid) is HIGH
  16         * outgoing previous-stage ready   (o.p_ready) is LOW
  17
  18     output transmission conditions are when:
  19         * outgoing next-stage strobe (o.n_valid) is HIGH
  20         * outgoing next-stage ready   (i.n_ready) is LOW
  21
  22     the tricky bit is when the input has valid data and the output is not
  23     ready to accept it.  if it wasn't for the clock synchronisation, it
  24     would be possible to tell the input "hey don't send that data, we're
  25     not ready".  unfortunately, it's not possible to "change the past":
  26     the previous stage *has no choice* but to pass on its data.
  27
  28     therefore, the incoming data *must* be accepted - and stored: that
  29     is the responsibility / contract that this stage *must* accept.
  30     on the same clock, it's possible to tell the input that it must
  31     not send any more data.  this is the "stall" condition.
  32
  33     we now effectively have *two* possible pieces of data to "choose" from:
  34     the buffered data, and the incoming data.  the decision as to which
  35     to process and output is based on whether we are in "stall" or not.
  36     i.e. when the next stage is no longer ready, the output comes from
  37     the buffer if a stall had previously occurred, otherwise it comes
  38     direct from processing the input.
  39
  40     this allows us to respect a synchronous "travelling STB" with what
  41     dan calls a "buffered handshake".
  42
  43     it's quite a complex state machine!
  44 """
  45
  46 from nmigen import Signal, Cat, Const, Mux, Module
  47 from nmigen.cli import verilog, rtlil
  48 from collections.abc import Sequence
  49
  50
  51 class IOAckIn:
  52
  53     def __init__(self):
  54         self.p_valid = Signal() # >>in - comes in from PREVIOUS stage
  55         self.n_ready = Signal() # in<< - comes in from the NEXT stage
  56
  57
  58 class IOAckOut:
  59
  60     def __init__(self):
  61         self.n_valid = Signal() # out>> - goes out to the NEXT stage
  62         self.p_ready = Signal() # <<out - goes out to the PREVIOUS stage
  63
  64
  65 def eq(o, i):
  66     if not isinstance(o, Sequence):
  67         o, i = [o], [i]
  68     res = []
  69     for (ao, ai) in zip(o, i):
  70         res.append(ao.eq(ai))
  71     return res
  72
  73
  74 class BufferedPipeline:
  75     """ buffered pipeline stage.  data and strobe signals travel in sync.
  76         if ever the input is ready and the output is not, processed data
  77         is stored in a temporary register.
  78
  79         stage-1   i.p_valid >>in   stage   o.n_valid out>>   stage+1
  80         stage-1   o.p_ready <<out  stage   i.n_ready <<in    stage+1
  81         stage-1   i.data    >>in   stage   o.data    out>>   stage+1
  82                               |             |
  83                             process --->----^
  84                               |             |
  85                               +-- r_data ->-+
  86
  87         input data i_data is read (only), is processed and goes into an
  88         intermediate result store [process()].  this is updated combinatorially.
  89
  90         in a non-stall condition, the intermediate result will go into the
  91         output (update_output).  however if ever there is a stall, it goes
  92         into r_data instead [update_buffer()].
  93
  94         when the non-stall condition is released, r_data is the first
  95         to be transferred to the output [flush_buffer()], and the stall
  96         condition cleared.
  97
  98         on the next cycle (as long as stall is not raised again) the
  99         input may begin to be processed and transferred directly to output.
 100     """
 101     def __init__(self, stage):
 102         """ pass in a "stage" which may be either a static class or a class
 103             instance, which has three functions:
 104             * ispec: returns input signals according to the input specification
 105             * ispec: returns output signals to the output specification
 106             * process: takes an input instance and returns processed data
 107
 108             i_data -> process() -> result --> o.data
 109                                      |           ^
 110                                      |           |
 111                                      +-> r_data -+
 112         """
 113         self.stage = stage
 114
 115         # set up input and output IO ACK (prev/next ready/valid)
 116         self.i = IOAckIn()
 117         self.o = IOAckOut()
 118
 119         # set up the input and output data
 120         self.i.data = stage.ispec() # input type
 121         self.r_data = stage.ospec() # all these are output type
 122         self.result = stage.ospec()
 123         self.o.data = stage.ospec()
 124
 125     def connect_next(self, nxt):
 126         """ helper function to connect to the next stage data/valid/ready.
 127             data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
 128         """
 129         return [nxt.i.p_valid.eq(self.o.n_valid),
 130                 self.i.n_ready.eq(nxt.o.p_ready),
 131                 eq(nxt.i.data, self.o.data),
 132                ]
 133
 134     def connect_in(self, prev):
 135         """ helper function to connect stage to an input source.  do not
 136             use to connect stage-to-stage!
 137         """
 138         return [self.i.p_valid.eq(prev.i.p_valid),
 139                 prev.o.p_ready.eq(self.o.p_ready),
 140                 eq(self.i.data, prev.i.data),
 141                ]
 142
 143     def connect_out(self, nxt):
 144         """ helper function to connect stage to an output source.  do not
 145             use to connect stage-to-stage!
 146         """
 147         return [nxt.o.n_valid.eq(self.o.n_valid),
 148                 self.i.n_ready.eq(nxt.i.n_ready),
 149                 eq(nxt.o.data, self.o.data),
 150                ]
 151
 152     def set_input(self, i):
 153         """ helper function to set the input data
 154         """
 155         return eq(self.i.data, i)
 156
 157     def update_buffer(self):
 158         """ copies the result into the intermediate register r_data,
 159             which will need to be outputted on a subsequent cycle
 160             prior to allowing "normal" operation.
 161         """
 162         return eq(self.r_data, self.result)
 163
 164     def update_output(self):
 165         """ copies the (combinatorial) result into the output
 166         """
 167         return eq(self.o.data, self.result)
 168
 169     def flush_buffer(self):
 170         """ copies the *intermediate* register r_data into the output
 171         """
 172         return eq(self.o.data, self.r_data)
 173
 174     def ports(self):
 175         return [self.i.data, self.o.data]
 176
 177     def elaborate(self, platform):
 178         m = Module()
 179
 180         # establish some combinatorial temporaries
 181         o_n_validn = Signal(reset_less=True)
 182         i_p_valid_o_p_ready = Signal(reset_less=True)
 183         m.d.comb += [o_n_validn.eq(~self.o.n_valid),
 184                      i_p_valid_o_p_ready.eq(self.i.p_valid & self.o.p_ready),
 185         ]
 186
 187         # store result of processing in combinatorial temporary
 188         with m.If(self.i.p_valid): # input is valid: process it
 189             m.d.comb += eq(self.result, self.stage.process(self.i.data))
 190         # if not in stall condition, update the temporary register
 191         with m.If(self.o.p_ready): # not stalled
 192             m.d.sync += self.update_buffer()
 193
 194         #with m.If(self.i.p_rst): # reset
 195         #    m.d.sync += self.o.n_valid.eq(0)
 196         #    m.d.sync += self.o.p_ready.eq(0)
 197         with m.If(self.i.n_ready): # next stage is ready
 198             with m.If(self.o.p_ready): # not stalled
 199                 # nothing in buffer: send (processed) input direct to output
 200                 m.d.sync += [self.o.n_valid.eq(self.i.p_valid),
 201                              self.update_output(),
 202                             ]
 203             with m.Else(): # o.p_ready is false, and something is in buffer.
 204                 # Flush the [already processed] buffer to the output port.
 205                 m.d.sync += [self.o.n_valid.eq(1),
 206                              self.flush_buffer(),
 207                              # clear stall condition, declare register empty.
 208                              self.o.p_ready.eq(1),
 209                             ]
 210                 # ignore input, since o.p_ready is also false.
 211
 212         # (i.n_ready) is false here: next stage is ready
 213         with m.Elif(o_n_validn): # next stage being told "ready"
 214             m.d.sync += [self.o.n_valid.eq(self.i.p_valid),
 215                          self.o.p_ready.eq(1), # Keep the buffer empty
 216                          # set the output data (from comb result)
 217                          self.update_output(),
 218                         ]
 219         # (i.n_ready) false and (o.n_valid) true:
 220         with m.Elif(i_p_valid_o_p_ready):
 221             # If next stage *is* ready, and not stalled yet, accept input
 222             m.d.sync += self.o.p_ready.eq(~(self.i.p_valid & self.o.n_valid))
 223
 224         return m
 225
 226     def ports(self):
 227         return [self.i.p_valid, self.i.n_ready,
 228                 self.o.n_valid, self.o.p_ready,
 229                ]
 230
 231
 232 class ExampleAddStage:
 233     """ an example of how to use the buffered pipeline, as a class instance
 234     """
 235
 236     def ispec(self):
 237         """ returns a tuple of input signals which will be the incoming data
 238         """
 239         return (Signal(16), Signal(16))
 240
 241     def ospec(self):
 242         """ returns an output signal which will happen to contain the sum
 243             of the two inputs
 244         """
 245         return Signal(16)
 246
 247     def process(self, i):
 248         """ process the input data (sums the values in the tuple) and returns it
 249         """
 250         return i[0] + i[1]
 251
 252
 253 class ExampleBufPipeAdd(BufferedPipeline):
 254     """ an example of how to use the buffered pipeline, using a class instance
 255     """
 256
 257     def __init__(self):
 258         addstage = ExampleAddStage()
 259         BufferedPipeline.__init__(self, addstage)
 260
 261
 262 class ExampleStage:
 263     """ an example of how to use the buffered pipeline, in a static class
 264         fashion
 265     """
 266
 267     def ispec():
 268         return Signal(16)
 269
 270     def ospec():
 271         return Signal(16)
 272
 273     def process(i):
 274         """ process the input data and returns it (adds 1)
 275         """
 276         return i + 1
 277
 278
 279 class ExampleBufPipe(BufferedPipeline):
 280     """ an example of how to use the buffered pipeline.
 281     """
 282
 283     def __init__(self):
 284         BufferedPipeline.__init__(self, ExampleStage)
 285
 286
 287 if __name__ == '__main__':
 288     dut = ExampleBufPipe()
 289     vl = rtlil.convert(dut, ports=dut.ports())
 290     with open("test_bufpipe.il", "w") as f:
 291         f.write(vl)