src/add/example_buf_pipe.py

   1 """ nmigen implementation of buffered pipeline stage, based on zipcpu:
   2     https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
   3
   4     this module requires quite a bit of thought to understand how it works
   5     (and why it is needed in the first place).  reading the above is
   6     *strongly* recommended.
   7
   8     unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
   9     the STB / ACK signals to raise and lower (on separate clocks) before
  10     data may proceeed (thus only allowing one piece of data to proceed
  11     on *ALTERNATE* cycles), the signalling here is a true pipeline
  12     where data will flow on *every* clock when the conditions are right.
  13
  14     input acceptance conditions are when:
  15         * incoming previous-stage strobe (i_p_stb) is HIGH
  16         * outgoing previous-stage busy   (o_p_busy) is LOW
  17
  18     output transmission conditions are when:
  19         * outgoing next-stage strobe (o_n_stb) is HIGH
  20         * outgoing next-stage busy   (i_n_busy) is LOW
  21
  22     the tricky bit is when the input has valid data and the output is not
  23     ready to accept it.  if it wasn't for the clock synchronisation, it
  24     would be possible to tell the input "hey don't send that data, we're
  25     not ready".  unfortunately, it's not possible to "change the past":
  26     the previous stage *has no choice* but to pass on its data.
  27
  28     therefore, the incoming data *must* be accepted - and stored: that
  29     is the responsibility / contract that this stage *must* accept.
  30     on the same clock, it's possible to tell the input that it must
  31     not send any more data.  this is the "stall" condition.
  32
  33     we now effectively have *two* possible pieces of data to "choose" from:
  34     the buffered data, and the incoming data.  the decision as to which
  35     to process and output is based on whether we are in "stall" or not.
  36     i.e. when the next stage is no longer busy, the output comes from
  37     the buffer if a stall had previously occurred, otherwise it comes
  38     direct from processing the input.
  39
  40     this allows us to respect a synchronous "travelling STB" with what
  41     dan calls a "buffered handshake".
  42
  43     it's quite a complex state machine!
  44 """
  45
  46 from nmigen import Signal, Cat, Const, Mux, Module
  47 from nmigen.cli import verilog, rtlil
  48
  49
  50 class ExampleStage:
  51     """ an example of how to use the buffered pipeline.  actual names of
  52         variables (i_data, r_data, o_data, result) below do not matter:
  53         the functions however do.
  54
  55         input data i_data is read (only), is processed and goes into an
  56         intermediate result store [process()].  this is updated combinatorially.
  57
  58         in a non-stall condition, the intermediate result will go into the
  59         output (update_output).  however if ever there is a stall, it goes
  60         into r_data instead [update_buffer()].
  61
  62         when the non-stall condition is released, r_data is the first
  63         to be transferred to the output [flush_buffer()], and the stall
  64         condition cleared.
  65
  66         on the next cycle (as long as stall is not raised again) the
  67         input may begin to be processed and transferred directly to output.
  68     """
  69
  70     def __init__(self):
  71         """ i_data can be a DIFFERENT type from everything else
  72             o_data, r_data and result must be of the same type
  73         """
  74         self.i_data = Signal(16)
  75         self.r_data = Signal(16)
  76         self.o_data = Signal(16)
  77         self.result = Signal(16)
  78
  79     def process(self):
  80         """ process the input data and store it in result.
  81             (not needed to be known: result is combinatorial)
  82         """
  83         return self.result.eq(self.i_data + 1)
  84
  85     def update_buffer(self):
  86         """ copies the result into the intermediate register r_data
  87         """
  88         return self.r_data.eq(self.result)
  89
  90     def update_output(self):
  91         """ copies the (combinatorial) result into the output
  92         """
  93         return self.o_data.eq(self.result)
  94
  95     def flush_buffer(self):
  96         """ copies the *intermediate* register r_data into the output
  97         """
  98         return self.o_data.eq(self.r_data)
  99
 100     def ports(self):
 101         return [self.i_data, self.o_data]
 102
 103
 104 class BufferedPipeline:
 105     """ buffered pipeline stage
 106
 107         stage-1   i_p_stb  >>in   stage   o_n_stb  out>>   stage+1
 108         stage-1   o_p_busy <<out  stage   i_n_busy <<in    stage+1
 109         stage-1   i_data   >>in   stage   o_data   out>>   stage+1
 110                               |             |
 111                               +------->  process
 112                               |             |
 113                               +-- r_data ---+
 114     """
 115     def __init__(self):
 116         # input: strobe comes in from previous stage, busy comes in from next
 117         #self.i_p_rst = Signal()    # >>in - comes in from PREVIOUS stage
 118         self.i_p_stb = Signal()    # >>in - comes in from PREVIOUS stage
 119         self.i_n_busy = Signal()   # in<< - comes in from the NEXT stage
 120
 121         # output: strobe goes out to next stage, busy comes in from previous
 122         self.o_n_stb = Signal()    # out>> - goes out to the NEXT stage
 123         self.o_p_busy = Signal()   # <<out - goes out to the PREVIOUS stage
 124
 125     def elaborate(self, platform):
 126         m = Module()
 127
 128         # establish some combinatorial temporaries
 129         o_p_busyn = Signal(reset_less=True)
 130         o_n_stbn = Signal(reset_less=True)
 131         i_n_busyn = Signal(reset_less=True)
 132         i_p_stb_o_p_busyn = Signal(reset_less=True)
 133         m.d.comb += [i_n_busyn.eq(~self.i_n_busy),
 134                      o_n_stbn.eq(~self.o_n_stb),
 135                      o_p_busyn.eq(~self.o_p_busy),
 136                      i_p_stb_o_p_busyn.eq(self.i_p_stb & o_p_busyn),
 137         ]
 138
 139         # store result of processing in combinatorial temporary
 140         with m.If(self.i_p_stb): # input is valid: process it
 141             m.d.comb += self.stage.process()
 142         # if not in stall condition, update the temporary register
 143         with m.If(o_p_busyn): # not stalled
 144             m.d.sync += self.stage.update_buffer()
 145
 146         #with m.If(self.i_p_rst): # reset
 147         #    m.d.sync += self.o_n_stb.eq(0)
 148         #    m.d.sync += self.o_p_busy.eq(0)
 149         with m.If(i_n_busyn): # next stage is not busy
 150             with m.If(o_p_busyn): # not stalled
 151                 # nothing in buffer: send (processed) input direct to output
 152                 m.d.sync += [self.o_n_stb.eq(self.i_p_stb),
 153                              self.stage.update_output(),
 154                             ]
 155             with m.Else(): # o_p_busy is true, and something is in our buffer.
 156                 # Flush the [already processed] buffer to the output port.
 157                 m.d.sync += [self.o_n_stb.eq(1),
 158                              self.stage.flush_buffer(),
 159                              # clear stall condition, declare register empty.
 160                              self.o_p_busy.eq(0),
 161                             ]
 162                 # ignore input, since o_p_busy is also true.
 163
 164         # (i_n_busy) is true here: next stage is busy
 165         with m.Elif(o_n_stbn): # next stage being told "not busy"
 166             m.d.sync += [self.o_n_stb.eq(self.i_p_stb),
 167                          self.o_p_busy.eq(0), # Keep the buffer empty
 168                          # set the output data (from comb result)
 169                          self.stage.update_output(),
 170                         ]
 171         # (i_n_busy) and (o_n_stb) both true:
 172         with m.Elif(i_p_stb_o_p_busyn):
 173             # If next stage *is* busy, and not stalled yet, accept input
 174             m.d.sync += self.o_p_busy.eq(self.i_p_stb & self.o_n_stb)
 175
 176         return m
 177
 178     def ports(self):
 179         return [self.i_p_stb, self.i_n_busy,
 180                 self.o_n_stb, self.o_p_busy,
 181                ]
 182
 183
 184 class BufPipe(BufferedPipeline):
 185
 186     def __init__(self):
 187         BufferedPipeline.__init__(self)
 188         self.stage = ExampleStage()
 189
 190     def ports(self):
 191         return self.stage.ports() + BufferedPipeline.ports(self)
 192
 193
 194 if __name__ == '__main__':
 195     dut = BufPipe()
 196     vl = rtlil.convert(dut, ports=dut.ports())
 197     with open("test_bufpipe.il", "w") as f:
 198         f.write(vl)