src/add/example_buf_pipe.py

   1 """ nmigen implementation of buffered pipeline stage, based on zipcpu:
   2     https://zipcpu.com/blog/2017/08/14/strategies-for-pipelining.html
   3
   4     this module requires quite a bit of thought to understand how it works
   5     (and why it is needed in the first place).  reading the above is
   6     *strongly* recommended.
   7
   8     unlike john dawson's IEEE754 FPU STB/ACK signalling, which requires
   9     the STB / ACK signals to raise and lower (on separate clocks) before
  10     data may proceeed (thus only allowing one piece of data to proceed
  11     on *ALTERNATE* cycles), the signalling here is a true pipeline
  12     where data will flow on *every* clock when the conditions are right.
  13
  14     input acceptance conditions are when:
  15         * incoming previous-stage strobe (p.i_valid) is HIGH
  16         * outgoing previous-stage ready   (p.o_ready) is LOW
  17
  18     output transmission conditions are when:
  19         * outgoing next-stage strobe (n.o_valid) is HIGH
  20         * outgoing next-stage ready   (n.i_ready) is LOW
  21
  22     the tricky bit is when the input has valid data and the output is not
  23     ready to accept it.  if it wasn't for the clock synchronisation, it
  24     would be possible to tell the input "hey don't send that data, we're
  25     not ready".  unfortunately, it's not possible to "change the past":
  26     the previous stage *has no choice* but to pass on its data.
  27
  28     therefore, the incoming data *must* be accepted - and stored: that
  29     is the responsibility / contract that this stage *must* accept.
  30     on the same clock, it's possible to tell the input that it must
  31     not send any more data.  this is the "stall" condition.
  32
  33     we now effectively have *two* possible pieces of data to "choose" from:
  34     the buffered data, and the incoming data.  the decision as to which
  35     to process and output is based on whether we are in "stall" or not.
  36     i.e. when the next stage is no longer ready, the output comes from
  37     the buffer if a stall had previously occurred, otherwise it comes
  38     direct from processing the input.
  39
  40     this allows us to respect a synchronous "travelling STB" with what
  41     dan calls a "buffered handshake".
  42
  43     it's quite a complex state machine!
  44 """
  45
  46 from nmigen import Signal, Cat, Const, Mux, Module
  47 from nmigen.cli import verilog, rtlil
  48 from nmigen.hdl.rec import Record, Layout
  49
  50 from collections.abc import Sequence
  51
  52
  53 class PrevControl:
  54     """ contains signals that come *from* the previous stage (both in and out)
  55         * i_valid: previous stage indicating all incoming data is valid.
  56                    may be a multi-bit signal, where all bits are required
  57                    to be asserted to indicate "valid".
  58         * o_ready: output to next stage indicating readiness to accept data
  59         * i_data : an input - added by the user of this class
  60     """
  61
  62     def __init__(self, i_width=1):
  63         self.i_valid = Signal(i_width, name="p_i_valid") # prev   >>in  self
  64         self.o_ready = Signal(name="p_o_ready") # prev   <<out self
  65
  66     def connect_in(self, prev):
  67         """ helper function to connect stage to an input source.  do not
  68             use to connect stage-to-stage!
  69         """
  70         return [self.i_valid.eq(prev.i_valid),
  71                 prev.o_ready.eq(self.o_ready),
  72                 eq(self.i_data, prev.i_data),
  73                ]
  74
  75     def i_valid_logic(self):
  76         vlen = len(self.i_valid)
  77         if vlen > 1: # multi-bit case: valid only when i_valid is all 1s
  78             all1s = Const(-1, (len(self.i_valid), False))
  79             return self.i_valid == all1s
  80         # single-bit i_valid case
  81         return self.i_valid
  82
  83
  84 class NextControl:
  85     """ contains the signals that go *to* the next stage (both in and out)
  86         * o_valid: output indicating to next stage that data is valid
  87         * i_ready: input from next stage indicating that it can accept data
  88         * o_data : an output - added by the user of this class
  89     """
  90     def __init__(self):
  91         self.o_valid = Signal(name="n_o_valid") # self out>>  next
  92         self.i_ready = Signal(name="n_i_ready") # self <<in   next
  93
  94     def connect_to_next(self, nxt):
  95         """ helper function to connect to the next stage data/valid/ready.
  96             data/valid is passed *TO* nxt, and ready comes *IN* from nxt.
  97         """
  98         return [nxt.i_valid.eq(self.o_valid),
  99                 self.i_ready.eq(nxt.o_ready),
 100                 eq(nxt.i_data, self.o_data),
 101                ]
 102
 103     def connect_out(self, nxt):
 104         """ helper function to connect stage to an output source.  do not
 105             use to connect stage-to-stage!
 106         """
 107         return [nxt.o_valid.eq(self.o_valid),
 108                 self.i_ready.eq(nxt.i_ready),
 109                 eq(nxt.o_data, self.o_data),
 110                ]
 111
 112
 113 def eq(o, i):
 114     """ makes signals equal: a helper routine which identifies if it is being
 115         passed a list (or tuple) of objects, or signals, or Records, and calls
 116         the objects' eq function.
 117
 118         complex objects (classes) can be used: they must follow the
 119         convention of having an eq member function, which takes the
 120         responsibility of further calling eq and returning a list of
 121         eq assignments
 122
 123         Record is a special (unusual, recursive) case, where the input
 124         is specified as a dictionary (which may contain further dictionaries,
 125         recursively), where the field names of the dictionary must match
 126         the Record's field spec.
 127     """
 128     if not isinstance(o, Sequence):
 129         o, i = [o], [i]
 130     res = []
 131     for (ao, ai) in zip(o, i):
 132         #print ("eq", ao, ai)
 133         if isinstance(ao, Record):
 134             for idx, (field_name, field_shape, _) in enumerate(ao.layout):
 135                 if isinstance(field_shape, Layout):
 136                     rres = eq(ao.fields[field_name], ai.fields[field_name])
 137                 else:
 138                     rres = eq(ao.fields[field_name], ai[field_name])
 139                 res += rres
 140         else:
 141             rres = ao.eq(ai)
 142             if not isinstance(rres, Sequence):
 143                 rres = [rres]
 144             res += rres
 145     return res
 146
 147
 148 class StageChain:
 149     """ pass in a list of stages, and they will automatically be
 150         chained together via their input and output specs into a
 151         combinatorial chain.
 152
 153         * input to this class will be the input of the first stage
 154         * output of first stage goes into input of second
 155         * output of second goes into input into third (etc. etc.)
 156         * the output of this class will be the output of the last stage
 157     """
 158     def __init__(self, chain):
 159         self.chain = chain
 160
 161     def ispec(self):
 162         return self.chain[0].ispec()
 163
 164     def ospec(self):
 165         return self.chain[-1].ospec()
 166
 167     def setup(self, m, i):
 168         for (idx, c) in enumerate(self.chain):
 169             if hasattr(c, "setup"):
 170                 c.setup(m, i)               # stage may have some module stuff
 171             o = self.chain[idx].ospec()     # only the last assignment survives
 172             m.d.comb += eq(o, c.process(i)) # process input into "o"
 173             if idx != len(self.chain)-1:
 174                 i = self.chain[idx+1]       # becomes new input on next loop
 175         self.o = o                          # last loop is the output
 176
 177     def process(self, i):
 178         return self.o
 179
 180
 181 class PipelineBase:
 182     """ Common functions for Pipeline API
 183     """
 184     def __init__(self, stage, in_multi=None):
 185         """ pass in a "stage" which may be either a static class or a class
 186             instance, which has four functions (one optional):
 187             * ispec: returns input signals according to the input specification
 188             * ispec: returns output signals to the output specification
 189             * process: takes an input instance and returns processed data
 190             * setup: performs any module linkage if the stage uses one.
 191
 192             User must also:
 193             * add i_data member to PrevControl and
 194             * add o_data member to NextControl
 195         """
 196         self.stage = stage
 197
 198         # set up input and output IO ACK (prev/next ready/valid)
 199         self.p = PrevControl(in_multi)
 200         self.n = NextControl()
 201
 202     def connect_to_next(self, nxt):
 203         """ helper function to connect to the next stage data/valid/ready.
 204         """
 205         return self.n.connect_to_next(nxt.p)
 206
 207     def connect_in(self, prev):
 208         """ helper function to connect stage to an input source.  do not
 209             use to connect stage-to-stage!
 210         """
 211         return self.p.connect_in(prev.p)
 212
 213     def connect_out(self, nxt):
 214         """ helper function to connect stage to an output source.  do not
 215             use to connect stage-to-stage!
 216         """
 217         return self.n.connect_out(nxt.n)
 218
 219     def set_input(self, i):
 220         """ helper function to set the input data
 221         """
 222         return eq(self.p.i_data, i)
 223
 224     def ports(self):
 225         return [self.p.i_valid, self.n.i_ready,
 226                 self.n.o_valid, self.p.o_ready,
 227                 self.p.i_data, self.n.o_data   # XXX need flattening!
 228                ]
 229
 230
 231 class BufferedPipeline(PipelineBase):
 232     """ buffered pipeline stage.  data and strobe signals travel in sync.
 233         if ever the input is ready and the output is not, processed data
 234         is stored in a temporary register.
 235
 236         stage-1   p.i_valid >>in   stage   n.o_valid out>>   stage+1
 237         stage-1   p.o_ready <<out  stage   n.i_ready <<in    stage+1
 238         stage-1   p.i_data  >>in   stage   n.o_data  out>>   stage+1
 239                               |             |
 240                             process --->----^
 241                               |             |
 242                               +-- r_data ->-+
 243
 244         input data p.i_data is read (only), is processed and goes into an
 245         intermediate result store [process()].  this is updated combinatorially.
 246
 247         in a non-stall condition, the intermediate result will go into the
 248         output (update_output).  however if ever there is a stall, it goes
 249         into r_data instead [update_buffer()].
 250
 251         when the non-stall condition is released, r_data is the first
 252         to be transferred to the output [flush_buffer()], and the stall
 253         condition cleared.
 254
 255         on the next cycle (as long as stall is not raised again) the
 256         input may begin to be processed and transferred directly to output.
 257     """
 258     def __init__(self, stage):
 259         PipelineBase.__init__(self, stage)
 260
 261         # set up the input and output data
 262         self.p.i_data = stage.ispec() # input type
 263         self.n.o_data = stage.ospec()
 264
 265     def elaborate(self, platform):
 266         m = Module()
 267
 268         result = self.stage.ospec()
 269         r_data = self.stage.ospec()
 270         if hasattr(self.stage, "setup"):
 271             self.stage.setup(m, self.p.i_data)
 272
 273         # establish some combinatorial temporaries
 274         o_n_validn = Signal(reset_less=True)
 275         i_p_valid_o_p_ready = Signal(reset_less=True)
 276         p_i_valid = Signal(reset_less=True)
 277         m.d.comb += [p_i_valid.eq(self.p.i_valid_logic()),
 278                      o_n_validn.eq(~self.n.o_valid),
 279                      i_p_valid_o_p_ready.eq(p_i_valid & self.p.o_ready),
 280         ]
 281
 282         # store result of processing in combinatorial temporary
 283         #with m.If(self.p.i_valid): # input is valid: process it
 284         m.d.comb += eq(result, self.stage.process(self.p.i_data))
 285         # if not in stall condition, update the temporary register
 286         with m.If(self.p.o_ready): # not stalled
 287             m.d.sync += eq(r_data, result) # update buffer
 288
 289         #with m.If(self.p.i_rst): # reset
 290         #    m.d.sync += self.n.o_valid.eq(0)
 291         #    m.d.sync += self.p.o_ready.eq(0)
 292         with m.If(self.n.i_ready): # next stage is ready
 293             with m.If(self.p.o_ready): # not stalled
 294                 # nothing in buffer: send (processed) input direct to output
 295                 m.d.sync += [self.n.o_valid.eq(p_i_valid),
 296                              eq(self.n.o_data, result), # update output
 297                             ]
 298             with m.Else(): # p.o_ready is false, and something is in buffer.
 299                 # Flush the [already processed] buffer to the output port.
 300                 m.d.sync += [self.n.o_valid.eq(1),
 301                              eq(self.n.o_data, r_data), # flush buffer
 302                              # clear stall condition, declare register empty.
 303                              self.p.o_ready.eq(1),
 304                             ]
 305                 # ignore input, since p.o_ready is also false.
 306
 307         # (n.i_ready) is false here: next stage is ready
 308         with m.Elif(o_n_validn): # next stage being told "ready"
 309             m.d.sync += [self.n.o_valid.eq(p_i_valid),
 310                          self.p.o_ready.eq(1), # Keep the buffer empty
 311                          # set the output data (from comb result)
 312                          eq(self.n.o_data, result),
 313                         ]
 314         # (n.i_ready) false and (n.o_valid) true:
 315         with m.Elif(i_p_valid_o_p_ready):
 316             # If next stage *is* ready, and not stalled yet, accept input
 317             m.d.sync += self.p.o_ready.eq(~(p_i_valid & self.n.o_valid))
 318
 319         return m
 320
 321
 322 class ExampleAddStage:
 323     """ an example of how to use the buffered pipeline, as a class instance
 324     """
 325
 326     def ispec(self):
 327         """ returns a tuple of input signals which will be the incoming data
 328         """
 329         return (Signal(16), Signal(16))
 330
 331     def ospec(self):
 332         """ returns an output signal which will happen to contain the sum
 333             of the two inputs
 334         """
 335         return Signal(16)
 336
 337     def process(self, i):
 338         """ process the input data (sums the values in the tuple) and returns it
 339         """
 340         return i[0] + i[1]
 341
 342
 343 class ExampleBufPipeAdd(BufferedPipeline):
 344     """ an example of how to use the buffered pipeline, using a class instance
 345     """
 346
 347     def __init__(self):
 348         addstage = ExampleAddStage()
 349         BufferedPipeline.__init__(self, addstage)
 350
 351
 352 class ExampleStage:
 353     """ an example of how to use the buffered pipeline, in a static class
 354         fashion
 355     """
 356
 357     def ispec():
 358         return Signal(16, name="example_input_signal")
 359
 360     def ospec():
 361         return Signal(16, name="example_output_signal")
 362
 363     def process(i):
 364         """ process the input data and returns it (adds 1)
 365         """
 366         return i + 1
 367
 368
 369 class ExampleBufPipe(BufferedPipeline):
 370     """ an example of how to use the buffered pipeline.
 371     """
 372
 373     def __init__(self):
 374         BufferedPipeline.__init__(self, ExampleStage)
 375
 376
 377 class CombPipe(PipelineBase):
 378     """A simple pipeline stage containing combinational logic that can execute
 379     completely in one clock cycle.
 380
 381     Attributes:
 382     -----------
 383     input : StageInput
 384         The pipeline input
 385     output : StageOutput
 386         The pipeline output
 387     r_data : Signal, input_shape
 388         A temporary (buffered) copy of a prior (valid) input
 389     result: Signal, output_shape
 390         The output of the combinatorial logic
 391     """
 392
 393     def __init__(self, stage):
 394         PipelineBase.__init__(self, stage)
 395         self._data_valid = Signal()
 396
 397         # set up the input and output data
 398         self.p.i_data = stage.ispec() # input type
 399         self.n.o_data = stage.ospec() # output type
 400
 401     def elaborate(self, platform):
 402         m = Module()
 403
 404         r_data = self.stage.ispec() # input type
 405         result = self.stage.ospec() # output data
 406         if hasattr(self.stage, "setup"):
 407             self.stage.setup(m, r_data)
 408
 409         p_i_valid = Signal(reset_less=True)
 410         m.d.comb += p_i_valid.eq(self.p.i_valid_logic())
 411         m.d.comb += eq(result, self.stage.process(r_data))
 412         m.d.comb += self.n.o_valid.eq(self._data_valid)
 413         m.d.comb += self.p.o_ready.eq(~self._data_valid | self.n.i_ready)
 414         m.d.sync += self._data_valid.eq(p_i_valid | \
 415                                         (~self.n.i_ready & self._data_valid))
 416         with m.If(self.p.i_valid & self.p.o_ready):
 417             m.d.sync += eq(r_data, self.p.i_data)
 418         m.d.comb += eq(self.n.o_data, result)
 419         return m
 420
 421
 422 class ExampleCombPipe(CombPipe):
 423     """ an example of how to use the combinatorial pipeline.
 424     """
 425
 426     def __init__(self):
 427         CombPipe.__init__(self, ExampleStage)
 428
 429
 430 if __name__ == '__main__':
 431     dut = ExampleBufPipe()
 432     vl = rtlil.convert(dut, ports=dut.ports())
 433     with open("test_bufpipe.il", "w") as f:
 434         f.write(vl)
 435
 436     dut = ExampleCombPipe()
 437     vl = rtlil.convert(dut, ports=dut.ports())
 438     with open("test_combpipe.il", "w") as f:
 439         f.write(vl)