src/add/fadd_state.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase
   9
  10 from singlepipe import eq
  11
  12
  13 class FPADD(FPBase):
  14
  15     def __init__(self, width, single_cycle=False):
  16         FPBase.__init__(self)
  17         self.width = width
  18         self.single_cycle = single_cycle
  19
  20         self.in_a  = FPOp(width)
  21         self.in_b  = FPOp(width)
  22         self.out_z = FPOp(width)
  23
  24     def elaborate(self, platform=None):
  25         """ creates the HDL code-fragment for FPAdd
  26         """
  27         m = Module()
  28
  29         # Latches
  30         a = FPNumIn(self.in_a, self.width)
  31         b = FPNumIn(self.in_b, self.width)
  32         z = FPNumOut(self.width, False)
  33
  34         m.submodules.fpnum_a = a
  35         m.submodules.fpnum_b = b
  36         m.submodules.fpnum_z = z
  37
  38         m.d.comb += a.v.eq(self.in_a.v)
  39         m.d.comb += b.v.eq(self.in_b.v)
  40
  41         w = z.m_width + 4
  42         tot = Signal(w, reset_less=True) # sticky/round/guard, {mantissa} result, 1 overflow
  43
  44         of = Overflow()
  45
  46         m.submodules.overflow = of
  47
  48         with m.FSM() as fsm:
  49
  50             # ******
  51             # gets operand a
  52
  53             with m.State("get_a"):
  54                 res = self.get_op(m, self.in_a, a, "get_b")
  55                 m.d.sync += eq([a, self.in_a.ack], res)
  56
  57             # ******
  58             # gets operand b
  59
  60             with m.State("get_b"):
  61                 res = self.get_op(m, self.in_b, b, "special_cases")
  62                 m.d.sync += eq([b, self.in_b.ack], res)
  63
  64             # ******
  65             # special cases: NaNs, infs, zeros, denormalised
  66             # NOTE: some of these are unique to add.  see "Special Operations"
  67             # https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  68
  69             with m.State("special_cases"):
  70
  71                 s_nomatch = Signal()
  72                 m.d.comb += s_nomatch.eq(a.s != b.s)
  73
  74                 m_match = Signal()
  75                 m.d.comb += m_match.eq(a.m == b.m)
  76
  77                 # if a is NaN or b is NaN return NaN
  78                 with m.If(a.is_nan | b.is_nan):
  79                     m.next = "put_z"
  80                     m.d.sync += z.nan(1)
  81
  82                 # XXX WEIRDNESS for FP16 non-canonical NaN handling
  83                 # under review
  84
  85                 ## if a is zero and b is NaN return -b
  86                 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
  87                 #    m.next = "put_z"
  88                 #    m.d.sync += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
  89
  90                 ## if b is zero and a is NaN return -a
  91                 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
  92                 #    m.next = "put_z"
  93                 #    m.d.sync += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
  94
  95                 ## if a is -zero and b is NaN return -b
  96                 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
  97                 #    m.next = "put_z"
  98                 #    m.d.sync += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
  99
 100                 ## if b is -zero and a is NaN return -a
 101                 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 102                 #    m.next = "put_z"
 103                 #    m.d.sync += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 104
 105                 # if a is inf return inf (or NaN)
 106                 with m.Elif(a.is_inf):
 107                     m.next = "put_z"
 108                     m.d.sync += z.inf(a.s)
 109                     # if a is inf and signs don't match return NaN
 110                     with m.If(b.exp_128 & s_nomatch):
 111                         m.d.sync += z.nan(1)
 112
 113                 # if b is inf return inf
 114                 with m.Elif(b.is_inf):
 115                     m.next = "put_z"
 116                     m.d.sync += z.inf(b.s)
 117
 118                 # if a is zero and b zero return signed-a/b
 119                 with m.Elif(a.is_zero & b.is_zero):
 120                     m.next = "put_z"
 121                     m.d.sync += z.create(a.s & b.s, b.e, b.m[3:-1])
 122
 123                 # if a is zero return b
 124                 with m.Elif(a.is_zero):
 125                     m.next = "put_z"
 126                     m.d.sync += z.create(b.s, b.e, b.m[3:-1])
 127
 128                 # if b is zero return a
 129                 with m.Elif(b.is_zero):
 130                     m.next = "put_z"
 131                     m.d.sync += z.create(a.s, a.e, a.m[3:-1])
 132
 133                 # if a equal to -b return zero (+ve zero)
 134                 with m.Elif(s_nomatch & m_match & (a.e == b.e)):
 135                     m.next = "put_z"
 136                     m.d.sync += z.zero(0)
 137
 138                 # Denormalised Number checks
 139                 with m.Else():
 140                     m.next = "align"
 141                     self.denormalise(m, a)
 142                     self.denormalise(m, b)
 143
 144             # ******
 145             # align.
 146
 147             with m.State("align"):
 148                 if not self.single_cycle:
 149                     # NOTE: this does *not* do single-cycle multi-shifting,
 150                     #       it *STAYS* in the align state until exponents match
 151
 152                     # exponent of a greater than b: shift b down
 153                     with m.If(a.e > b.e):
 154                         m.d.sync += b.shift_down()
 155                     # exponent of b greater than a: shift a down
 156                     with m.Elif(a.e < b.e):
 157                         m.d.sync += a.shift_down()
 158                     # exponents equal: move to next stage.
 159                     with m.Else():
 160                         m.next = "add_0"
 161                 else:
 162                     # This one however (single-cycle) will do the shift
 163                     # in one go.
 164
 165                     # XXX TODO: the shifter used here is quite expensive
 166                     # having only one would be better
 167
 168                     ediff = Signal((len(a.e), True), reset_less=True)
 169                     ediffr = Signal((len(a.e), True), reset_less=True)
 170                     m.d.comb += ediff.eq(a.e - b.e)
 171                     m.d.comb += ediffr.eq(b.e - a.e)
 172                     with m.If(ediff > 0):
 173                         m.d.sync += b.shift_down_multi(ediff)
 174                     # exponent of b greater than a: shift a down
 175                     with m.Elif(ediff < 0):
 176                         m.d.sync += a.shift_down_multi(ediffr)
 177
 178                     m.next = "add_0"
 179
 180             # ******
 181             # First stage of add.  covers same-sign (add) and subtract
 182             # special-casing when mantissas are greater or equal, to
 183             # give greatest accuracy.
 184
 185             with m.State("add_0"):
 186                 m.next = "add_1"
 187                 m.d.sync += z.e.eq(a.e)
 188                 # same-sign (both negative or both positive) add mantissas
 189                 with m.If(a.s == b.s):
 190                     m.d.sync += [
 191                         tot.eq(Cat(a.m, 0) + Cat(b.m, 0)),
 192                         z.s.eq(a.s)
 193                     ]
 194                 # a mantissa greater than b, use a
 195                 with m.Elif(a.m >= b.m):
 196                     m.d.sync += [
 197                         tot.eq(Cat(a.m, 0) - Cat(b.m, 0)),
 198                         z.s.eq(a.s)
 199                     ]
 200                 # b mantissa greater than a, use b
 201                 with m.Else():
 202                     m.d.sync += [
 203                         tot.eq(Cat(b.m, 0) - Cat(a.m, 0)),
 204                         z.s.eq(b.s)
 205                 ]
 206
 207             # ******
 208             # Second stage of add: preparation for normalisation.
 209             # detects when tot sum is too big (tot[27] is kinda a carry bit)
 210
 211             with m.State("add_1"):
 212                 m.next = "normalise_1"
 213                 # tot[27] gets set when the sum overflows. shift result down
 214                 with m.If(tot[-1]):
 215                     m.d.sync += [
 216                         z.m.eq(tot[4:]),
 217                         of.m0.eq(tot[4]),
 218                         of.guard.eq(tot[3]),
 219                         of.round_bit.eq(tot[2]),
 220                         of.sticky.eq(tot[1] | tot[0]),
 221                         z.e.eq(z.e + 1)
 222                 ]
 223                 # tot[27] zero case
 224                 with m.Else():
 225                     m.d.sync += [
 226                         z.m.eq(tot[3:]),
 227                         of.m0.eq(tot[3]),
 228                         of.guard.eq(tot[2]),
 229                         of.round_bit.eq(tot[1]),
 230                         of.sticky.eq(tot[0])
 231                 ]
 232
 233             # ******
 234             # First stage of normalisation.
 235
 236             with m.State("normalise_1"):
 237                 self.normalise_1(m, z, of, "normalise_2")
 238
 239             # ******
 240             # Second stage of normalisation.
 241
 242             with m.State("normalise_2"):
 243                 self.normalise_2(m, z, of, "round")
 244
 245             # ******
 246             # rounding stage
 247
 248             with m.State("round"):
 249                 self.roundz(m, z, of.roundz)
 250                 m.next = "corrections"
 251
 252             # ******
 253             # correction stage
 254
 255             with m.State("corrections"):
 256                 self.corrections(m, z, "pack")
 257
 258             # ******
 259             # pack stage
 260
 261             with m.State("pack"):
 262                 self.pack(m, z, "put_z")
 263
 264             # ******
 265             # put_z stage
 266
 267             with m.State("put_z"):
 268                 self.put_z(m, z, self.out_z, "get_a")
 269
 270         return m
 271
 272
 273 if __name__ == "__main__":
 274     alu = FPADD(width=32)
 275     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 276
 277
 278     # works... but don't use, just do "python fname.py convert -t v"
 279     #print (verilog.convert(alu, ports=[
 280     #                        ports=alu.in_a.ports() + \
 281     #                              alu.in_b.ports() + \
 282     #                              alu.out_z.ports())