src/add/fmul.py

   1 from nmigen import Module, Signal
   2 from nmigen.cli import main, verilog
   3
   4 from fpbase import FPNum, FPOp, Overflow, FPBase
   5
   6
   7 class FPMUL(FPBase):
   8
   9     def __init__(self, width):
  10         FPBase.__init__(self)
  11         self.width = width
  12
  13         self.in_a  = FPOp(width)
  14         self.in_b  = FPOp(width)
  15         self.out_z = FPOp(width)
  16
  17     def get_fragment(self, platform=None):
  18         """ creates the HDL code-fragment for FPMUL
  19         """
  20         m = Module()
  21
  22         # Latches
  23         a = FPNum(self.width)
  24         b = FPNum(self.width)
  25         z = FPNum(self.width, False)
  26
  27         tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow
  28
  29         of = Overflow()
  30
  31         with m.FSM() as fsm:
  32
  33                 with m.State("get_a"):
  34                         m.next += "get_b"
  35                         m.d.sync += s.in_a.ack.eq(1)
  36                         with m.If(s.in_a.ack & in_a.stb):
  37                                 m.d.sync += [
  38                                 a.eq(in_a),
  39                                 s.in_a.ack(0)
  40                         ]
  41
  42                 with m.State("get_b"):
  43                         m.next += "unpack"
  44                         m.d.sync += s.in_b.ack.eq(1)
  45                         with m.If(s.in_b.ack & in_b.stb):
  46                                 m.d.sync += [
  47                                 b.eq(in_b),
  48                                 s.in_b.ack(0)
  49                         ]
  50
  51                 with m.State("unpack"):
  52                         m.next += "special_cases"
  53                         m.d.sync += [
  54                         a.m.eq(a[0:22]),
  55                         b.m.eq(b[0:22]),
  56                         a.e.eq(a[23:31] - 127),
  57                         b.e.eq(b[23:31] - 127),
  58                         a.s.eq(a[31]),
  59                         b.s.eq(b[31])
  60                         ]
  61
  62                 with m.State("special_cases"):
  63                         m.next = "normalise_a"
  64                         #if a or b is NaN return NaN
  65                         with m.If(a.is_nan() | b.is_nan()):
  66                                 m.next += "put_z"
  67                                 m.d.sync += z.nan()
  68 """
  69       special_cases:
  70       begin
  71         //if a is NaN or b is NaN return NaN
  72         if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
  73           z[31] <= 1;
  74           z[30:23] <= 255;
  75           z[22] <= 1;
  76           z[21:0] <= 0;
  77           state <= put_z;
  78         //if a is inf return inf
  79         end else if (a_e == 128) begin
  80           z[31] <= a_s ^ b_s;
  81           z[30:23] <= 255;
  82           z[22:0] <= 0;
  83           //if b is zero return NaN
  84           if (($signed(b_e) == -127) && (b_m == 0)) begin
  85             z[31] <= 1;
  86             z[30:23] <= 255;
  87             z[22] <= 1;
  88             z[21:0] <= 0;
  89           end
  90           state <= put_z;
  91         //if b is inf return inf
  92         end else if (b_e == 128) begin
  93           z[31] <= a_s ^ b_s;
  94           z[30:23] <= 255;
  95           z[22:0] <= 0;
  96           //if a is zero return NaN
  97           if (($signed(a_e) == -127) && (a_m == 0)) begin
  98             z[31] <= 1;
  99             z[30:23] <= 255;
 100             z[22] <= 1;
 101             z[21:0] <= 0;
 102           end
 103           state <= put_z;
 104         //if a is zero return zero
 105         end else if (($signed(a_e) == -127) && (a_m == 0)) begin
 106           z[31] <= a_s ^ b_s;
 107           z[30:23] <= 0;
 108           z[22:0] <= 0;
 109           state <= put_z;
 110         //if b is zero return zero
 111         end else if (($signed(b_e) == -127) && (b_m == 0)) begin
 112           z[31] <= a_s ^ b_s;
 113           z[30:23] <= 0;
 114           z[22:0] <= 0;
 115           state <= put_z;
 116         end else begin
 117           //Denormalised Number
 118           if ($signed(a_e) == -127) begin
 119             a_e <= -126;
 120           end else begin
 121             a_m[23] <= 1;
 122           end
 123           //Denormalised Number
 124           if ($signed(b_e) == -127) begin
 125             b_e <= -126;
 126           end else begin
 127             b_m[23] <= 1;
 128           end
 129           state <= normalise_a;
 130         end
 131       end
 132
 133       normalise_a:
 134       begin
 135         if (a_m[23]) begin
 136           state <= normalise_b;
 137         end else begin
 138           a_m <= a_m << 1;
 139           a_e <= a_e - 1;
 140         end
 141       end
 142
 143       normalise_b:
 144       begin
 145         if (b_m[23]) begin
 146           state <= multiply_0;
 147         end else begin
 148           b_m <= b_m << 1;
 149           b_e <= b_e - 1;
 150         end
 151       end
 152
 153       multiply_0:
 154       begin
 155         z_s <= a_s ^ b_s;
 156         z_e <= a_e + b_e + 1;
 157         product <= a_m * b_m * 4;
 158         state <= multiply_1;
 159       end
 160
 161       multiply_1:
 162       begin
 163         z_m <= product[49:26];
 164         guard <= product[25];
 165         round_bit <= product[24];
 166         sticky <= (product[23:0] != 0);
 167         state <= normalise_1;
 168       end
 169
 170       normalise_1:
 171       begin
 172         if (z_m[23] == 0) begin
 173           z_e <= z_e - 1;
 174           z_m <= z_m << 1;
 175           z_m[0] <= guard;
 176           guard <= round_bit;
 177           round_bit <= 0;
 178         end else begin
 179           state <= normalise_2;
 180         end
 181       end
 182
 183       normalise_2:
 184       begin
 185         if ($signed(z_e) < -126) begin
 186           z_e <= z_e + 1;
 187           z_m <= z_m >> 1;
 188           guard <= z_m[0];
 189           round_bit <= guard;
 190           sticky <= sticky | round_bit;
 191         end else begin
 192           state <= round;
 193         end
 194       end
 195
 196       round:
 197       begin
 198         if (guard && (round_bit | sticky | z_m[0])) begin
 199           z_m <= z_m + 1;
 200           if (z_m == 24'hffffff) begin
 201             z_e <=z_e + 1;
 202           end
 203         end
 204         state <= pack;
 205       end
 206
 207       pack:
 208       begin
 209         z[22 : 0] <= z_m[22:0];
 210         z[30 : 23] <= z_e[7:0] + 127;
 211         z[31] <= z_s;
 212         if ($signed(z_e) == -126 && z_m[23] == 0) begin
 213           z[30 : 23] <= 0;
 214         end
 215         //if overflow occurs, return inf
 216         if ($signed(z_e) > 127) begin
 217           z[22 : 0] <= 0;
 218           z[30 : 23] <= 255;
 219           z[31] <= z_s;
 220         end
 221         state <= put_z;
 222       end
 223
 224       put_z:
 225       begin
 226         s_output_z_stb <= 1;
 227         s_output_z <= z;
 228         if (s_output_z_stb && output_z_ack) begin
 229           s_output_z_stb <= 0;
 230           state <= get_a;
 231         end
 232       end
 233
 234  """