Add more special cases to the module
[ieee754fpu.git] / src / add / fmul.py
1 from nmigen import Module, Signal
2 from nmigen.cli import main, verilog
3
4 from fpbase import FPNum, FPOp, Overflow, FPBase
5
6
7 class FPMUL(FPBase):
8
9 def __init__(self, width):
10 FPBase.__init__(self)
11 self.width = width
12
13 self.in_a = FPOp(width)
14 self.in_b = FPOp(width)
15 self.out_z = FPOp(width)
16
17 def get_fragment(self, platform=None):
18 """ creates the HDL code-fragment for FPMUL
19 """
20 m = Module()
21
22 # Latches
23 a = FPNum(self.width)
24 b = FPNum(self.width)
25 z = FPNum(self.width, False)
26
27 tot = Signal(28) # sticky/round/guard bits, 23 result, 1 overflow
28
29 of = Overflow()
30
31 with m.FSM() as fsm:
32
33 with m.State("get_a"):
34 m.next += "get_b"
35 m.d.sync += s.in_a.ack.eq(1)
36 with m.If(s.in_a.ack & in_a.stb):
37 m.d.sync += [
38 a.eq(in_a),
39 s.in_a.ack(0)
40 ]
41
42 with m.State("get_b"):
43 m.next += "unpack"
44 m.d.sync += s.in_b.ack.eq(1)
45 with m.If(s.in_b.ack & in_b.stb):
46 m.d.sync += [
47 b.eq(in_b),
48 s.in_b.ack(0)
49 ]
50
51 with m.State("unpack"):
52 m.next += "special_cases"
53 m.d.sync += [
54 a.m.eq(a[0:22]),
55 b.m.eq(b[0:22]),
56 a.e.eq(a[23:31] - 127),
57 b.e.eq(b[23:31] - 127),
58 a.s.eq(a[31]),
59 b.s.eq(b[31])
60 ]
61
62 with m.State("special_cases"):
63 m.next = "normalise_a"
64 #if a or b is NaN return NaN
65 with m.If(a.is_nan() | b.is_nan()):
66 m.next += "put_z"
67 m.d.sync += z.nan(1)
68 #if a is inf return inf
69 with m.Elif(a.is_inf()):
70 m.next += "put_z"
71 m.d.sync += z.inf(0)
72 #if b is zero return NaN
73 with m.If(b.is_zero()):
74 m.d.sync += z.nan(1)
75 #if b is inf return inf
76 with m.Elif(b.is_inf()):
77 m.next += "put_z"
78 m.d.sync += z.inf(0)
79 #if a is zero return NaN
80 with m.If(a.is_zero()):
81 m.next += "put_z"
82 m.d.sync += z.nan(1)
83 #if a is zero return zero
84 with m.Elif(a.is_zero()):
85 m.next += "put_z"
86 m.d.sync += z.zero(0)
87 #if b is zero return zero
88 with m.Elif(b.is_zero()):
89 m.next += "put_z"
90 m.d.sync += z.zero(0)
91 # Denormalised Number checks
92 with m.Else():
93 m.next = "normalise_a"
94 self.denormalise(m, a)
95 self.denormalise(m, b)
96
97 # ******
98 # normalise_a
99
100 with m.State("normalise_a"):
101 self.op_normalise(m, a, "normalise_b")
102
103 # ******
104 # normalise_b
105
106 with m.State("normalise_b"):
107 self.op_normalise(m, b, "multiply_0")
108
109
110
111 """
112 special_cases:
113 begin
114 //if a is NaN or b is NaN return NaN
115 if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
116 z[31] <= 1;
117 z[30:23] <= 255;
118 z[22] <= 1;
119 z[21:0] <= 0;
120 state <= put_z;
121 //if a is inf return inf
122 end else if (a_e == 128) begin
123 z[31] <= a_s ^ b_s;
124 z[30:23] <= 255;
125 z[22:0] <= 0;
126 //if b is zero return NaN
127 if (($signed(b_e) == -127) && (b_m == 0)) begin
128 z[31] <= 1;
129 z[30:23] <= 255;
130 z[22] <= 1;
131 z[21:0] <= 0;
132 end
133 state <= put_z;
134 //if b is inf return inf
135 end else if (b_e == 128) begin
136 z[31] <= a_s ^ b_s;
137 z[30:23] <= 255;
138 z[22:0] <= 0;
139 //if a is zero return NaN
140 if (($signed(a_e) == -127) && (a_m == 0)) begin
141 z[31] <= 1;
142 z[30:23] <= 255;
143 z[22] <= 1;
144 z[21:0] <= 0;
145 end
146 state <= put_z;
147 //if a is zero return zero
148 end else if (($signed(a_e) == -127) && (a_m == 0)) begin
149 z[31] <= a_s ^ b_s;
150 z[30:23] <= 0;
151 z[22:0] <= 0;
152 state <= put_z;
153 //if b is zero return zero
154 end else if (($signed(b_e) == -127) && (b_m == 0)) begin
155 z[31] <= a_s ^ b_s;
156 z[30:23] <= 0;
157 z[22:0] <= 0;
158 state <= put_z;
159 //^ done up to here
160 end else begin
161 //Denormalised Number
162 if ($signed(a_e) == -127) begin
163 a_e <= -126;
164 end else begin
165 a_m[23] <= 1;
166 end
167 //Denormalised Number
168 if ($signed(b_e) == -127) begin
169 b_e <= -126;
170 end else begin
171 b_m[23] <= 1;
172 end
173 state <= normalise_a;
174 end
175 end
176
177 normalise_a:
178 begin
179 if (a_m[23]) begin
180 state <= normalise_b;
181 end else begin
182 a_m <= a_m << 1;
183 a_e <= a_e - 1;
184 end
185 end
186
187 normalise_b:
188 begin
189 if (b_m[23]) begin
190 state <= multiply_0;
191 end else begin
192 b_m <= b_m << 1;
193 b_e <= b_e - 1;
194 end
195 end
196
197 multiply_0:
198 begin
199 z_s <= a_s ^ b_s;
200 z_e <= a_e + b_e + 1;
201 product <= a_m * b_m * 4;
202 state <= multiply_1;
203 end
204
205 multiply_1:
206 begin
207 z_m <= product[49:26];
208 guard <= product[25];
209 round_bit <= product[24];
210 sticky <= (product[23:0] != 0);
211 state <= normalise_1;
212 end
213
214 normalise_1:
215 begin
216 if (z_m[23] == 0) begin
217 z_e <= z_e - 1;
218 z_m <= z_m << 1;
219 z_m[0] <= guard;
220 guard <= round_bit;
221 round_bit <= 0;
222 end else begin
223 state <= normalise_2;
224 end
225 end
226
227 normalise_2:
228 begin
229 if ($signed(z_e) < -126) begin
230 z_e <= z_e + 1;
231 z_m <= z_m >> 1;
232 guard <= z_m[0];
233 round_bit <= guard;
234 sticky <= sticky | round_bit;
235 end else begin
236 state <= round;
237 end
238 end
239
240 round:
241 begin
242 if (guard && (round_bit | sticky | z_m[0])) begin
243 z_m <= z_m + 1;
244 if (z_m == 24'hffffff) begin
245 z_e <=z_e + 1;
246 end
247 end
248 state <= pack;
249 end
250
251 pack:
252 begin
253 z[22 : 0] <= z_m[22:0];
254 z[30 : 23] <= z_e[7:0] + 127;
255 z[31] <= z_s;
256 if ($signed(z_e) == -126 && z_m[23] == 0) begin
257 z[30 : 23] <= 0;
258 end
259 //if overflow occurs, return inf
260 if ($signed(z_e) > 127) begin
261 z[22 : 0] <= 0;
262 z[30 : 23] <= 255;
263 z[31] <= z_s;
264 end
265 state <= put_z;
266 end
267
268 put_z:
269 begin
270 s_output_z_stb <= 1;
271 s_output_z <= z;
272 if (s_output_z_stb && output_z_ack) begin
273 s_output_z_stb <= 0;
274 state <= get_a;
275 end
276 end
277
278 """