src/add/fmul.py

   1 from nmigen import Module, Signal
   2 from nmigen.cli import main, verilog
   3
   4 from fpbase import FPNum, FPOp, Overflow, FPBase
   5
   6
   7 class FPMUL(FPBase):
   8
   9     def __init__(self, width):
  10         FPBase.__init__(self)
  11         self.width = width
  12
  13         self.in_a  = FPOp(width)
  14         self.in_b  = FPOp(width)
  15         self.out_z = FPOp(width)
  16
  17     def get_fragment(self, platform=None):
  18         """ creates the HDL code-fragment for FPMUL
  19         """
  20         m = Module()
  21
  22         # Latches
  23         a = FPNum(self.width)
  24         b = FPNum(self.width)
  25         z = FPNum(self.width, False)
  26
  27         tot = Signal(28)     # sticky/round/guard bits, 23 result, 1 overflow
  28
  29         of = Overflow()
  30
  31         with m.FSM() as fsm:
  32
  33                 with m.State("get_a"):
  34                         m.next += "get_b"
  35                         m.d.sync += s.in_a.ack.eq(1)
  36                         with m.If(s.in_a.ack & in_a.stb):
  37                                 m.d.sync += [
  38                                 a.eq(in_a),
  39                                 s.in_a.ack(0)
  40                         ]
  41
  42                 with m.State("get_b"):
  43                         m.next += "unpack"
  44                         m.d.sync += s.in_b.ack.eq(1)
  45                         with m.If(s.in_b.ack & in_b.stb):
  46                                 m.d.sync += [
  47                                 b.eq(in_b),
  48                                 s.in_b.ack(0)
  49                         ]
  50
  51                 with m.State("unpack"):
  52                         m.next += "special_cases"
  53                         m.d.sync += [
  54                         a.m.eq(a[0:22]),
  55                         b.m.eq(b[0:22]),
  56                         a.e.eq(a[23:31] - 127),
  57                         b.e.eq(b[23:31] - 127),
  58                         a.s.eq(a[31]),
  59                         b.s.eq(b[31])
  60                         ]
  61
  62                 with m.State("special_cases"):
  63                         m.next = "normalise_a"
  64                         #if a or b is NaN return NaN
  65                         with m.If(a.is_nan() | b.is_nan()):
  66                                 m.next += "put_z"
  67                                 m.d.sync += z.nan(1)
  68                         #if a is inf return inf
  69                         with m.Elif(a.is_inf()):
  70                                 m.next += "put_z"
  71                                 m.d.sync += z.inf(0)
  72                         #if b is zero return NaN
  73                         with m.If(b.is_zero()):
  74                                 m.d.sync += z.nan(1)
  75                         #if b is inf return inf
  76                         with m.Elif(b.is_inf()):
  77                                 m.next += "put_z"
  78                                 m.d.sync += z.inf(0)
  79                         #if a is zero return NaN
  80                         with m.If(a.is_zero()):
  81                                 m.next += "put_z"
  82                                 m.d.sync += z.nan(1)
  83                         with m.Elif(a.is_zero()):
  84                                 m.next += "put_z"
  85                                 m.d.sync += z.zero(0)
  86
  87
  88
  89 """
  90 special_cases:
  91       begin
  92         //if a is NaN or b is NaN return NaN
  93         if ((a_e == 128 && a_m != 0) || (b_e == 128 && b_m != 0)) begin
  94           z[31] <= 1;
  95           z[30:23] <= 255;
  96           z[22] <= 1;
  97           z[21:0] <= 0;
  98           state <= put_z;
  99         //if a is inf return inf
 100         end else if (a_e == 128) begin
 101           z[31] <= a_s ^ b_s;
 102           z[30:23] <= 255;
 103           z[22:0] <= 0;
 104           //if b is zero return NaN
 105           if (($signed(b_e) == -127) && (b_m == 0)) begin
 106             z[31] <= 1;
 107             z[30:23] <= 255;
 108             z[22] <= 1;
 109             z[21:0] <= 0;
 110           end
 111           state <= put_z;
 112         //if b is inf return inf
 113         end else if (b_e == 128) begin
 114           z[31] <= a_s ^ b_s;
 115           z[30:23] <= 255;
 116           z[22:0] <= 0;
 117           //if a is zero return NaN
 118           if (($signed(a_e) == -127) && (a_m == 0)) begin
 119             z[31] <= 1;
 120             z[30:23] <= 255;
 121             z[22] <= 1;
 122             z[21:0] <= 0;
 123           end
 124           state <= put_z;
 125         //if a is zero return zero
 126         end else if (($signed(a_e) == -127) && (a_m == 0)) begin
 127           z[31] <= a_s ^ b_s;
 128           z[30:23] <= 0;
 129           z[22:0] <= 0;
 130           state <= put_z;
 131         //if b is zero return zero
 132         end else if (($signed(b_e) == -127) && (b_m == 0)) begin
 133           z[31] <= a_s ^ b_s;
 134           z[30:23] <= 0;
 135           z[22:0] <= 0;
 136           state <= put_z;
 137         end else begin
 138           //Denormalised Number
 139           if ($signed(a_e) == -127) begin
 140             a_e <= -126;
 141           end else begin
 142             a_m[23] <= 1;
 143           end
 144           //Denormalised Number
 145           if ($signed(b_e) == -127) begin
 146             b_e <= -126;
 147           end else begin
 148             b_m[23] <= 1;
 149           end
 150           state <= normalise_a;
 151         end
 152       end
 153
 154       normalise_a:
 155       begin
 156         if (a_m[23]) begin
 157           state <= normalise_b;
 158         end else begin
 159           a_m <= a_m << 1;
 160           a_e <= a_e - 1;
 161         end
 162       end
 163
 164       normalise_b:
 165       begin
 166         if (b_m[23]) begin
 167           state <= multiply_0;
 168         end else begin
 169           b_m <= b_m << 1;
 170           b_e <= b_e - 1;
 171         end
 172       end
 173
 174       multiply_0:
 175       begin
 176         z_s <= a_s ^ b_s;
 177         z_e <= a_e + b_e + 1;
 178         product <= a_m * b_m * 4;
 179         state <= multiply_1;
 180       end
 181
 182       multiply_1:
 183       begin
 184         z_m <= product[49:26];
 185         guard <= product[25];
 186         round_bit <= product[24];
 187         sticky <= (product[23:0] != 0);
 188         state <= normalise_1;
 189       end
 190
 191       normalise_1:
 192       begin
 193         if (z_m[23] == 0) begin
 194           z_e <= z_e - 1;
 195           z_m <= z_m << 1;
 196           z_m[0] <= guard;
 197           guard <= round_bit;
 198           round_bit <= 0;
 199         end else begin
 200           state <= normalise_2;
 201         end
 202       end
 203
 204       normalise_2:
 205       begin
 206         if ($signed(z_e) < -126) begin
 207           z_e <= z_e + 1;
 208           z_m <= z_m >> 1;
 209           guard <= z_m[0];
 210           round_bit <= guard;
 211           sticky <= sticky | round_bit;
 212         end else begin
 213           state <= round;
 214         end
 215       end
 216
 217       round:
 218       begin
 219         if (guard && (round_bit | sticky | z_m[0])) begin
 220           z_m <= z_m + 1;
 221           if (z_m == 24'hffffff) begin
 222             z_e <=z_e + 1;
 223           end
 224         end
 225         state <= pack;
 226       end
 227
 228       pack:
 229       begin
 230         z[22 : 0] <= z_m[22:0];
 231         z[30 : 23] <= z_e[7:0] + 127;
 232         z[31] <= z_s;
 233         if ($signed(z_e) == -126 && z_m[23] == 0) begin
 234           z[30 : 23] <= 0;
 235         end
 236         //if overflow occurs, return inf
 237         if ($signed(z_e) > 127) begin
 238           z[22 : 0] <= 0;
 239           z[30 : 23] <= 255;
 240           z[31] <= z_s;
 241         end
 242         state <= put_z;
 243       end
 244
 245       put_z:
 246       begin
 247         s_output_z_stb <= 1;
 248         s_output_z <= z;
 249         if (s_output_z_stb && output_z_ack) begin
 250           s_output_z_stb <= 0;
 251           state <= get_a;
 252         end
 253 end
 254
 255 """