add missing data_i and data_o temporarily
[ieee754fpu.git] / src / add / fpcommon / getop.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const, Elaboratable
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOpIn, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 from singlepipe import (ControlBase, StageChain, SimpleHandshake,
13 PassThroughStage, PrevControl)
14 from multipipe import CombMuxOutPipe
15 from multipipe import PriorityCombMuxInPipe
16
17 from fpbase import FPState
18
19
20 class FPGetOpMod(Elaboratable):
21 def __init__(self, width):
22 self.in_op = FPOpIn(width)
23 self.in_op.data_i = Signal(width)
24 self.out_op = Signal(width)
25 self.out_decode = Signal(reset_less=True)
26
27 def elaborate(self, platform):
28 m = Module()
29 m.d.comb += self.out_decode.eq((self.in_op.ready_o) & \
30 (self.in_op.valid_i_test))
31 m.submodules.get_op_in = self.in_op
32 #m.submodules.get_op_out = self.out_op
33 with m.If(self.out_decode):
34 m.d.comb += [
35 self.out_op.eq(self.in_op.v),
36 ]
37 return m
38
39
40 class FPGetOp(FPState):
41 """ gets operand
42 """
43
44 def __init__(self, in_state, out_state, in_op, width):
45 FPState.__init__(self, in_state)
46 self.out_state = out_state
47 self.mod = FPGetOpMod(width)
48 self.in_op = in_op
49 self.out_op = Signal(width)
50 self.out_decode = Signal(reset_less=True)
51
52 def setup(self, m, in_op):
53 """ links module to inputs and outputs
54 """
55 setattr(m.submodules, self.state_from, self.mod)
56 m.d.comb += self.mod.in_op.eq(in_op)
57 m.d.comb += self.out_decode.eq(self.mod.out_decode)
58
59 def action(self, m):
60 with m.If(self.out_decode):
61 m.next = self.out_state
62 m.d.sync += [
63 self.in_op.ready_o.eq(0),
64 self.out_op.eq(self.mod.out_op)
65 ]
66 with m.Else():
67 m.d.sync += self.in_op.ready_o.eq(1)
68
69
70 class FPNumBase2Ops:
71
72 def __init__(self, width, id_wid, m_extra=True):
73 self.a = FPNumBase(width, m_extra)
74 self.b = FPNumBase(width, m_extra)
75 self.mid = Signal(id_wid, reset_less=True)
76
77 def eq(self, i):
78 return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
79
80 def ports(self):
81 return [self.a, self.b, self.mid]
82
83
84 class FPADDBaseData:
85
86 def __init__(self, width, id_wid):
87 self.width = width
88 self.id_wid = id_wid
89 self.a = Signal(width)
90 self.b = Signal(width)
91 self.mid = Signal(id_wid, reset_less=True)
92
93 def eq(self, i):
94 return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
95
96 def ports(self):
97 return [self.a, self.b, self.mid]
98
99
100 class FPGet2OpMod(PrevControl):
101 def __init__(self, width, id_wid):
102 PrevControl.__init__(self)
103 self.width = width
104 self.id_wid = id_wid
105 self.data_i = self.ispec()
106 self.i = self.data_i
107 self.o = self.ospec()
108
109 def ispec(self):
110 return FPADDBaseData(self.width, self.id_wid)
111
112 def ospec(self):
113 return FPADDBaseData(self.width, self.id_wid)
114
115 def process(self, i):
116 return self.o
117
118 def elaborate(self, platform):
119 m = PrevControl.elaborate(self, platform)
120 with m.If(self.trigger):
121 m.d.comb += [
122 self.o.eq(self.data_i),
123 ]
124 return m
125
126
127 class FPGet2Op(FPState):
128 """ gets operands
129 """
130
131 def __init__(self, in_state, out_state, width, id_wid):
132 FPState.__init__(self, in_state)
133 self.out_state = out_state
134 self.mod = FPGet2OpMod(width, id_wid)
135 self.o = self.ospec()
136 self.in_stb = Signal(reset_less=True)
137 self.out_ack = Signal(reset_less=True)
138 self.out_decode = Signal(reset_less=True)
139
140 def ispec(self):
141 return self.mod.ispec()
142
143 def ospec(self):
144 return self.mod.ospec()
145
146 def trigger_setup(self, m, in_stb, in_ack):
147 """ links stb/ack
148 """
149 m.d.comb += self.mod.valid_i.eq(in_stb)
150 m.d.comb += in_ack.eq(self.mod.ready_o)
151
152 def setup(self, m, i):
153 """ links module to inputs and outputs
154 """
155 m.submodules.get_ops = self.mod
156 m.d.comb += self.mod.i.eq(i)
157 m.d.comb += self.out_ack.eq(self.mod.ready_o)
158 m.d.comb += self.out_decode.eq(self.mod.trigger)
159
160 def process(self, i):
161 return self.o
162
163 def action(self, m):
164 with m.If(self.out_decode):
165 m.next = self.out_state
166 m.d.sync += [
167 self.mod.ready_o.eq(0),
168 self.o.eq(self.mod.o),
169 ]
170 with m.Else():
171 m.d.sync += self.mod.ready_o.eq(1)
172
173