split out normalisation to separate module
[ieee754fpu.git] / src / add / fpcommon / postcalc.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 from singlepipe import (ControlBase, StageChain, UnbufferedPipeline,
13 PassThroughStage)
14 from multipipe import CombMuxOutPipe
15 from multipipe import PriorityCombMuxInPipe
16
17 class FPAddStage1Data:
18
19 def __init__(self, width, id_wid):
20 self.z = FPNumBase(width, False)
21 self.out_do_z = Signal(reset_less=True)
22 self.oz = Signal(width, reset_less=True)
23 self.of = Overflow()
24 self.mid = Signal(id_wid, reset_less=True)
25
26 def eq(self, i):
27 return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z), self.oz.eq(i.oz),
28 self.of.eq(i.of), self.mid.eq(i.mid)]