1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
5 from nmigen
import Module
, Signal
, Cat
, Mux
, Array
, Const
6 from nmigen
.lib
.coding
import PriorityEncoder
7 from nmigen
.cli
import main
, verilog
10 from fpbase
import FPNumIn
, FPNumOut
, FPOp
, Overflow
, FPBase
, FPNumBase
11 from fpbase
import MultiShiftRMerge
, Trigger
12 from singlepipe
import (ControlBase
, StageChain
, UnbufferedPipeline
,
14 from multipipe
import CombMuxOutPipe
15 from multipipe
import PriorityCombMuxInPipe
17 from fpbase
import FPState
, FPID
18 from fpcommon
.getop
import (FPGetOpMod
, FPGetOp
, FPNumBase2Ops
, FPADDBaseData
, FPGet2OpMod
, FPGet2Op
)
19 from fpcommon
.denorm
import (FPSCData
, FPAddDeNormMod
, FPAddDeNorm
)
20 from fpcommon
.postcalc
import FPAddStage1Data
21 from fpcommon
.postnormalise
import (FPNorm1Data
, FPNorm1ModSingle
,
22 FPNorm1ModMulti
, FPNorm1Single
, FPNorm1Multi
)
23 from fpcommon
.roundz
import (FPRoundData
, FPRoundMod
, FPRound
)
24 from fpcommon
.corrections
import (FPCorrectionsMod
, FPCorrections
)
25 from fpcommon
.pack
import (FPPackData
, FPPackMod
, FPPack
)
26 from fpcommon
.normtopack
import FPNormToPack
29 class FPPutZ(FPState
):
31 def __init__(self
, state
, in_z
, out_z
, in_mid
, out_mid
, to_state
=None):
32 FPState
.__init
__(self
, state
)
35 self
.to_state
= to_state
39 self
.out_mid
= out_mid
42 if self
.in_mid
is not None:
43 m
.d
.sync
+= self
.out_mid
.eq(self
.in_mid
)
45 self
.out_z
.z
.v
.eq(self
.in_z
)
47 with m
.If(self
.out_z
.z
.stb
& self
.out_z
.z
.ack
):
48 m
.d
.sync
+= self
.out_z
.z
.stb
.eq(0)
49 m
.next
= self
.to_state
51 m
.d
.sync
+= self
.out_z
.z
.stb
.eq(1)
54 class FPPutZIdx(FPState
):
56 def __init__(self
, state
, in_z
, out_zs
, in_mid
, to_state
=None):
57 FPState
.__init
__(self
, state
)
60 self
.to_state
= to_state
66 outz_stb
= Signal(reset_less
=True)
67 outz_ack
= Signal(reset_less
=True)
68 m
.d
.comb
+= [outz_stb
.eq(self
.out_zs
[self
.in_mid
].stb
),
69 outz_ack
.eq(self
.out_zs
[self
.in_mid
].ack
),
72 self
.out_zs
[self
.in_mid
].v
.eq(self
.in_z
.v
)
74 with m
.If(outz_stb
& outz_ack
):
75 m
.d
.sync
+= self
.out_zs
[self
.in_mid
].stb
.eq(0)
76 m
.next
= self
.to_state
78 m
.d
.sync
+= self
.out_zs
[self
.in_mid
].stb
.eq(1)