1 from sfpy
import Float32
4 # XXX DO NOT USE, fails on num=65536. wark-wark...
13 if (num
>= res
+ bit
):
15 res
= (res
>> 1) + bit
24 D
= num
# D is input (from num)
28 for i
in range(15, -1, -1): # negative ranges are weird...
32 R
= (R
<<2)|
((D
>>(i
+i
))&3)
33 R
= R
-((Q
<<2)|
1) #/*-Q01*/
37 R
= (R
<<2)|
((D
>>(i
+i
))&3)
38 R
= R
+((Q
<<2)|
3) #/*+Q11*/
41 Q
= (Q
<<1)|
1 #/*new Q:*/
43 Q
= (Q
<<1)|
0 #/*new Q:*/
52 # grabbed these from unit_test_single (convenience, this is just experimenting)
58 return ((x
& 0x7f800000) >> 23) - 127
60 def set_exponent(x
, e
):
61 return (x
& ~
0x7f800000) |
((e
+127) << 23)
64 return ((x
& 0x80000000) >> 31)
66 # convert FP32 to s/e/m
67 def create_fp32(s
, e
, m
):
68 """ receive sign, exponent, mantissa, return FP32 """
69 return set_exponent((s
<< 31) |
get_mantissa(m
))
71 # convert s/e/m to FP32
73 """ receive FP32, return sign, exponent, mantissa """
74 return get_sign(x
), get_exponent(x
), get_mantissa(x
)
77 # main function, takes mantissa and exponent as separate arguments
78 # returns a tuple, sqrt'd mantissa, sqrt'd exponent
80 def main(mantissa
, exponent
):
82 # shift mantissa up, subtract 1 from exp to compensate
83 return sqrt(mantissa
<< 1), (exponent
- 1) >> 1
84 # mantissa as-is, no compensating needed on exp
85 return sqrt(mantissa
), (exponent
>> 1)
88 if __name__
== '__main__':
90 # quick test up to 1000 of two sqrt functions
91 for Q
in range(1, int(1e4
)):
92 print(Q
, sqrt(Q
), sqrtsimple(Q
), int(Q
**0.5))
93 assert int(Q
**0.5) == sqrtsimple(Q
), "Q sqrtsimpl fail %d" % Q
94 assert int(Q
**0.5) == sqrt(Q
), "Q sqrt fail %d" % Q
96 # quick mantissa/exponent demo
100 print("m:%d e:%d sqrt: m:%d e:%d" % (m
, e
, ms
, es
))
102 x
= Float32(1234.123456789)
106 print (xbits
, type(xbits
))
107 s
, e
, m
= decode_fp32(xbits
)
108 print(s
, e
, m
, hex(m
))
113 https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf
115 //This is the main code of integer sqrt function found here:http://verilogcodes.blogspot.com/2017/11/a-verilog-function-for-finding-square-root.html
122 //Verilog function to find square root of a 32 bit number.
123 //The output is 16 bit.
124 function [15:0] sqrt;
125 input [31:0] num; //declare input
126 //intermediate signals.
129 reg [17:0] left,right,r;
132 //initialize all the variables.
136 left = 0; //input to adder/sub
137 right = 0; //input to adder/sub
139 //run the calculations for 16 iterations.
140 for(i=0;i<16;i=i+1) begin
141 right = {q,r[17],1'b1};
142 left = {r[15:0],a[31:30]};
143 a = {a[29:0],2'b00}; //left shift by 2 bits.
144 if (r[17] == 1) //add if r is negative
146 else //subtract if r is positive
148 q = {q[14:0],!r[17]};
150 sqrt = q; //final assignment of output.
152 endfunction //end of Function
155 c version (from paper linked from URL)
157 unsigned squart(D, r) /*Non-Restoring sqrt*/
158 unsigned D; /*D:32-bit unsigned integer to be square rooted */
161 unsigned Q = 0; /*Q:16-bit unsigned integer (root)*/
162 int R = 0; /*R:17-bit integer (remainder)*/
164 for (i = 15;i>=0;i--) /*for each root bit*/
168 R = R<<2)|((D>>(i+i))&3);
169 R = R-((Q<<2)|1); /*-Q01*/
173 R = R<<2)|((D>>(i+i))&3);
174 R = R+((Q<<2)|3); /*+Q11*/
176 if (R>=0) Q = Q<<1)|1; /*new Q:*/
177 else Q = Q<<1)|0; /*new Q:*/
180 /*remainder adjusting*/
181 if (R<0) R = R+((Q<<1)|1);
182 *r = R; /*return remainder*/
183 return(Q); /*return root*/
188 short isqrt(short num) {
190 short bit = 1 << 14; // The second-to-top bit is set: 1 << 30 for 32 bits
192 // "bit" starts at the highest power of four <= the argument.
197 if (num >= res + bit) {
199 res = (res >> 1) + bit;