src/add/fsqrt.py

   1
   2
   3 """
   4 //This is the main code of integer sqrt function found here:http://verilogcodes.blogspot.com/2017/11/a-verilog-function-for-finding-square-root.html
   5 //
   6
   7 module testbench;
   8
   9 reg [15:0] sqr;
  10
  11 //Verilog function to find square root of a 32 bit number.
  12 //The output is 16 bit.
  13 function [15:0] sqrt;
  14     input [31:0] num;  //declare input
  15     //intermediate signals.
  16     reg [31:0] a;
  17     reg [15:0] q;
  18     reg [17:0] left,right,r;
  19     integer i;
  20 begin
  21     //initialize all the variables.
  22     a = num;
  23     q = 0;
  24     i = 0;
  25     left = 0;   //input to adder/sub
  26     right = 0;  //input to adder/sub
  27     r = 0;  //remainder
  28     //run the calculations for 16 iterations.
  29     for(i=0;i<16;i=i+1) begin
  30         right = {q,r[17],1'b1};
  31         left = {r[15:0],a[31:30]};
  32         a = {a[29:0],2'b00};    //left shift by 2 bits.
  33         if (r[17] == 1) //add if r is negative
  34             r = left + right;
  35         else    //subtract if r is positive
  36             r = left - right;
  37         q = {q[14:0],!r[17]};
  38     end
  39     sqrt = q;   //final assignment of output.
  40 end
  41 endfunction //end of Function
  42
  43 """