src/add/multipipe.py

   1 """ Combinatorial Multi-input multiplexer block conforming to Pipeline API
   2 """
   3
   4 from math import log
   5 from nmigen import Signal, Cat, Const, Mux, Module, Array
   6 from nmigen.cli import verilog, rtlil
   7 from nmigen.lib.coding import PriorityEncoder
   8 from nmigen.hdl.rec import Record, Layout
   9
  10 from collections.abc import Sequence
  11
  12 from example_buf_pipe import eq, NextControl, PrevControl, ExampleStage
  13
  14
  15 class MultiInControl:
  16     """ Common functions for Pipeline API
  17     """
  18     def __init__(self, in_multi=None, p_len=1):
  19         """ Multi-input Control class
  20
  21             User must also:
  22             * add i_data members to PrevControl and
  23             * add o_data member  to NextControl
  24         """
  25         # set up input and output IO ACK (prev/next ready/valid)
  26         p = []
  27         for i in range(p_len):
  28             p.append(PrevControl(in_multi))
  29         self.p = Array(p)
  30         self.n = NextControl()
  31
  32     def connect_to_next(self, nxt, p_idx=0):
  33         """ helper function to connect to the next stage data/valid/ready.
  34         """
  35         return self.n.connect_to_next(nxt.p[p_idx])
  36
  37     def _connect_in(self, prev, idx=0, prev_idx=None):
  38         """ helper function to connect stage to an input source.  do not
  39             use to connect stage-to-stage!
  40         """
  41         if prev_idx is None:
  42             return self.p[idx]._connect_in(prev.p)
  43         return self.p[idx]._connect_in(prev.p[prev_idx])
  44
  45     def _connect_out(self, nxt):
  46         """ helper function to connect stage to an output source.  do not
  47             use to connect stage-to-stage!
  48         """
  49         if nxt_idx is None:
  50             return self.n._connect_out(nxt.n)
  51         return self.n._connect_out(nxt.n)
  52
  53     def set_input(self, i, idx=0):
  54         """ helper function to set the input data
  55         """
  56         return eq(self.p[idx].i_data, i)
  57
  58     def ports(self):
  59         res = []
  60         for i in range(len(self.p)):
  61             res += [self.p[i].i_valid, self.p[i].o_ready,
  62                     self.p[i].i_data]# XXX need flattening!]
  63         res += [self.n.i_ready, self.n.o_valid,
  64                 self.n.o_data]   # XXX need flattening!]
  65         return res
  66
  67
  68
  69 class MultiOutControl:
  70     """ Common functions for Pipeline API
  71     """
  72     def __init__(self, n_len=1):
  73         """ Multi-output Control class
  74
  75             User must also:
  76             * add i_data member to PrevControl and
  77             * add o_data members to NextControl
  78         """
  79
  80         # set up input and output IO ACK (prev/next ready/valid)
  81         self.p = PrevControl(in_multi)
  82         for i in range(n_len):
  83             n.append(NextControl())
  84         self.n = Array(n)
  85
  86     def connect_to_next(self, nxt, n_idx=0):
  87         """ helper function to connect to the next stage data/valid/ready.
  88         """
  89         return self.n[n_idx].connect_to_next(nxt.p)
  90
  91     def _connect_in(self, prev, idx=0):
  92         """ helper function to connect stage to an input source.  do not
  93             use to connect stage-to-stage!
  94         """
  95         return self.n[idx]._connect_in(prev.p)
  96
  97     def _connect_out(self, nxt, idx=0, nxt_idx=None):
  98         """ helper function to connect stage to an output source.  do not
  99             use to connect stage-to-stage!
 100         """
 101         if nxt_idx is None:
 102             return self.n[idx]._connect_out(nxt.n)
 103         return self.n[idx]._connect_out(nxt.n[nxt_idx])
 104
 105     def set_input(self, i):
 106         """ helper function to set the input data
 107         """
 108         return eq(self.p.i_data, i)
 109
 110     def ports(self):
 111         res = []
 112         res += [self.p.i_valid, self.p.o_ready,
 113                 self.p.i_data]# XXX need flattening!]
 114         for i in range(len(self.n)):
 115             res += [self.n[i].i_ready, self.n[i].o_valid,
 116                     self.n[i].o_data]   # XXX need flattening!]
 117         return res
 118
 119
 120
 121 class CombMultiOutPipeline(MultiInControl):
 122     """ A multi-input Combinatorial block conforming to the Pipeline API
 123
 124         Attributes:
 125         -----------
 126         p.i_data : StageInput, shaped according to ispec
 127             The pipeline input
 128         p.o_data : StageOutput, shaped according to ospec
 129             The pipeline output
 130         r_data : input_shape according to ispec
 131             A temporary (buffered) copy of a prior (valid) input.
 132             This is HELD if the output is not ready.  It is updated
 133             SYNCHRONOUSLY.
 134     """
 135
 136     def __init__(self, stage, n_len, n_mux):
 137         MultiInControl.__init__(self, n_len=n_len)
 138         self.stage = stage
 139         self.p_mux = p_mux
 140
 141         # set up the input and output data
 142         for i in range(p_len):
 143             self.p[i].i_data = stage.ispec() # input type
 144         self.n.o_data = stage.ospec()
 145
 146     def elaborate(self, platform):
 147         m = Module()
 148
 149         m.submodules += self.p_mux
 150
 151         # need buffer register conforming to *input* spec
 152         r_data = self.stage.ispec() # input type
 153         if hasattr(self.stage, "setup"):
 154             self.stage.setup(m, r_data)
 155
 156         data_valid = []
 157         n_i_readyn = []
 158         n_len = len(self.n)
 159         for i in range(n_len):
 160             data_valid.append(Signal(name="data_valid", reset_less=True))
 161             n_i_readyn.append(Signal(name="n_i_readyn", reset_less=True))
 162         n_i_readyn = Array(n_i_readyn)
 163         data_valid = Array(data_valid)
 164
 165         p_i_valid = Signal(reset_less=True)
 166         m.d.comb += p_i_valid.eq(self.p.i_valid_logic())
 167
 168         mid = self.p_mux.m_id
 169
 170         for i in range(p_len):
 171             m.d.comb += data_valid[i].eq(0)
 172             m.d.comb += n_i_readyn[i].eq(1)
 173             m.d.comb += self.n[i].o_valid.eq(data_valid[i])
 174         m.d.comb += self.p[mid].o_ready.eq(~data_valid[mid] | self.n.i_ready)
 175         m.d.comb += n_i_readyn[mid].eq(~self.n[mid].i_ready & data_valid[mid])
 176         anyvalid = Signal(i, reset_less=True)
 177         av = []
 178         for i in range(p_len):
 179             av.append(~data_valid[i] | self.n[i].i_ready)
 180         anyvalid = Cat(*av)
 181         m.d.comb += self.p.o_ready.eq(anyvalid.bool())
 182         m.d.comb += data_valid[mid].eq(p_i_valid | \
 183                                     (n_i_readyn[mid] & data_valid[mid]))
 184
 185         with m.If(self.p.i_valid & self.p.o_ready):
 186             m.d.comb += eq(r_data, self.p.i_data)
 187         m.d.comb += eq(self.n[mid].o_data, self.stage.process(r_data))
 188
 189         return m
 190
 191
 192 class CombMultiInPipeline(MultiInControl):
 193     """ A multi-input Combinatorial block conforming to the Pipeline API
 194
 195         Attributes:
 196         -----------
 197         p.i_data : StageInput, shaped according to ispec
 198             The pipeline input
 199         p.o_data : StageOutput, shaped according to ospec
 200             The pipeline output
 201         r_data : input_shape according to ispec
 202             A temporary (buffered) copy of a prior (valid) input.
 203             This is HELD if the output is not ready.  It is updated
 204             SYNCHRONOUSLY.
 205     """
 206
 207     def __init__(self, stage, p_len, p_mux):
 208         MultiInControl.__init__(self, p_len=p_len)
 209         self.stage = stage
 210         self.p_mux = p_mux
 211
 212         # set up the input and output data
 213         for i in range(p_len):
 214             self.p[i].i_data = stage.ispec() # input type
 215         self.n.o_data = stage.ospec()
 216
 217     def elaborate(self, platform):
 218         m = Module()
 219
 220         m.submodules += self.p_mux
 221
 222         # need an array of buffer registers conforming to *input* spec
 223         r_data = []
 224         data_valid = []
 225         p_i_valid = []
 226         n_i_readyn = []
 227         p_len = len(self.p)
 228         for i in range(p_len):
 229             r = self.stage.ispec() # input type
 230             r_data.append(r)
 231             data_valid.append(Signal(name="data_valid", reset_less=True))
 232             p_i_valid.append(Signal(name="p_i_valid", reset_less=True))
 233             n_i_readyn.append(Signal(name="n_i_readyn", reset_less=True))
 234             if hasattr(self.stage, "setup"):
 235                 self.stage.setup(m, r)
 236         if len(r_data) > 1:
 237             r_data = Array(r_data)
 238             p_i_valid = Array(p_i_valid)
 239             n_i_readyn = Array(n_i_readyn)
 240             data_valid = Array(data_valid)
 241
 242         mid = self.p_mux.m_id
 243         for i in range(p_len):
 244             m.d.comb += data_valid[i].eq(0)
 245             m.d.comb += n_i_readyn[i].eq(1)
 246             m.d.comb += p_i_valid[i].eq(0)
 247             m.d.comb += self.p[i].o_ready.eq(0)
 248         m.d.comb += p_i_valid[mid].eq(self.p_mux.active)
 249         m.d.comb += self.p[mid].o_ready.eq(~data_valid[mid] | self.n.i_ready)
 250         m.d.comb += n_i_readyn[mid].eq(~self.n.i_ready & data_valid[mid])
 251         anyvalid = Signal(i, reset_less=True)
 252         av = []
 253         for i in range(p_len):
 254             av.append(data_valid[i])
 255         anyvalid = Cat(*av)
 256         m.d.comb += self.n.o_valid.eq(anyvalid.bool())
 257         m.d.comb += data_valid[mid].eq(p_i_valid[mid] | \
 258                                     (n_i_readyn[mid] & data_valid[mid]))
 259
 260         for i in range(p_len):
 261             vr = Signal(reset_less=True)
 262             m.d.comb += vr.eq(self.p[i].i_valid & self.p[i].o_ready)
 263             with m.If(vr):
 264                 m.d.comb += eq(r_data[i], self.p[i].i_data)
 265
 266         m.d.comb += eq(self.n.o_data, self.stage.process(r_data[mid]))
 267
 268         return m
 269
 270
 271 class InputPriorityArbiter:
 272     def __init__(self, pipe, num_rows):
 273         self.pipe = pipe
 274         self.num_rows = num_rows
 275         self.mmax = int(log(self.num_rows) / log(2))
 276         self.m_id = Signal(self.mmax, reset_less=True) # multiplex id
 277         self.active = Signal(reset_less=True)
 278
 279     def elaborate(self, platform):
 280         m = Module()
 281
 282         assert len(self.pipe.p) == self.num_rows, \
 283                 "must declare input to be same size"
 284         pe = PriorityEncoder(self.num_rows)
 285         m.submodules.selector = pe
 286
 287         # connect priority encoder
 288         in_ready = []
 289         for i in range(self.num_rows):
 290             p_i_valid = Signal(reset_less=True)
 291             m.d.comb += p_i_valid.eq(self.pipe.p[i].i_valid_logic())
 292             in_ready.append(p_i_valid)
 293         m.d.comb += pe.i.eq(Cat(*in_ready)) # array of input "valids"
 294         m.d.comb += self.active.eq(~pe.n)   # encoder active (one input valid)
 295         m.d.comb += self.m_id.eq(pe.o)       # output one active input
 296
 297         return m
 298
 299     def ports(self):
 300         return [self.m_id, self.active]
 301
 302
 303
 304 class ExamplePipeline(CombMultiInPipeline):
 305     """ an example of how to use the combinatorial pipeline.
 306     """
 307
 308     def __init__(self, p_len=2):
 309         p_mux = InputPriorityArbiter(self, p_len)
 310         CombMultiInPipeline.__init__(self, ExampleStage, p_len, p_mux)
 311
 312
 313 if __name__ == '__main__':
 314
 315     dut = ExamplePipeline()
 316     vl = rtlil.convert(dut, ports=dut.ports())
 317     with open("test_combpipe.il", "w") as f:
 318         f.write(vl)