src/add/multipipe.py

   1 """ Combinatorial Multi-input multiplexer block conforming to Pipeline API
   2 """
   3
   4 from math import log
   5 from nmigen import Signal, Cat, Const, Mux, Module, Array
   6 from nmigen.cli import verilog, rtlil
   7 from nmigen.lib.coding import PriorityEncoder
   8 from nmigen.hdl.rec import Record, Layout
   9
  10 from collections.abc import Sequence
  11
  12 from example_buf_pipe import eq, NextControl, PrevControl, ExampleStage
  13
  14
  15 class MultiInControl:
  16     """ Common functions for Pipeline API
  17     """
  18     def __init__(self, in_multi=None, p_len=1):
  19         """ Multi-input Control class
  20
  21             User must also:
  22             * add i_data members to PrevControl and
  23             * add o_data member  to NextControl
  24         """
  25
  26         # set up input and output IO ACK (prev/next ready/valid)
  27         p = []
  28         for i in range(p_len):
  29             p.append(PrevControl(in_multi))
  30         self.p = Array(p)
  31         self.n = NextControl()
  32
  33     def connect_to_next(self, nxt, p_idx=0):
  34         """ helper function to connect to the next stage data/valid/ready.
  35         """
  36         return self.n.connect_to_next(nxt.p[p_idx])
  37
  38     def connect_in(self, prev, idx=0, prev_idx=None):
  39         """ helper function to connect stage to an input source.  do not
  40             use to connect stage-to-stage!
  41         """
  42         if prev_idx is None:
  43             return self.p[idx].connect_in(prev.p)
  44         return self.p[idx].connect_in(prev.p[prev_idx])
  45
  46     def connect_out(self, nxt):
  47         """ helper function to connect stage to an output source.  do not
  48             use to connect stage-to-stage!
  49         """
  50         if nxt_idx is None:
  51             return self.n.connect_out(nxt.n)
  52         return self.n.connect_out(nxt.n)
  53
  54     def set_input(self, i, idx=0):
  55         """ helper function to set the input data
  56         """
  57         return eq(self.p[idx].i_data, i)
  58
  59     def ports(self):
  60         res = []
  61         for i in range(len(self.p)):
  62             res += [self.p[i].i_valid, self.p[i].o_ready,
  63                     self.p[i].i_data]# XXX need flattening!]
  64         res += [self.n.i_ready, self.n.o_valid,
  65                 self.n.o_data]   # XXX need flattening!]
  66         return res
  67
  68
  69
  70 class MultiOutControl:
  71     """ Common functions for Pipeline API
  72     """
  73     def __init__(self, n_len=1):
  74         """ Multi-output Control class
  75
  76             User must also:
  77             * add i_data member to PrevControl and
  78             * add o_data members to NextControl
  79         """
  80
  81         # set up input and output IO ACK (prev/next ready/valid)
  82         self.p = PrevControl(in_multi)
  83         for i in range(n_len):
  84             n.append(NextControl())
  85         self.n = Array(n)
  86
  87     def connect_to_next(self, nxt, n_idx=0):
  88         """ helper function to connect to the next stage data/valid/ready.
  89         """
  90         return self.n[n_idx].connect_to_next(nxt.p)
  91
  92     def connect_in(self, prev, idx=0):
  93         """ helper function to connect stage to an input source.  do not
  94             use to connect stage-to-stage!
  95         """
  96         return self.n[idx].connect_in(prev.p)
  97
  98     def connect_out(self, nxt, idx=0, nxt_idx=None):
  99         """ helper function to connect stage to an output source.  do not
 100             use to connect stage-to-stage!
 101         """
 102         if nxt_idx is None:
 103             return self.n[idx].connect_out(nxt.n)
 104         return self.n[idx].connect_out(nxt.n[nxt_idx])
 105
 106     def set_input(self, i):
 107         """ helper function to set the input data
 108         """
 109         return eq(self.p.i_data, i)
 110
 111     def ports(self):
 112         res = []
 113         res += [self.p.i_valid, self.p.o_ready,
 114                 self.p.i_data]# XXX need flattening!]
 115         for i in range(len(self.n)):
 116             res += [self.n[i].i_ready, self.n[i].o_valid,
 117                     self.n[i].o_data]   # XXX need flattening!]
 118         return res
 119
 120
 121
 122 class CombMultiOutPipeline(MultiInControl):
 123     """ A multi-input Combinatorial block conforming to the Pipeline API
 124
 125         Attributes:
 126         -----------
 127         p.i_data : StageInput, shaped according to ispec
 128             The pipeline input
 129         p.o_data : StageOutput, shaped according to ospec
 130             The pipeline output
 131         r_data : input_shape according to ispec
 132             A temporary (buffered) copy of a prior (valid) input.
 133             This is HELD if the output is not ready.  It is updated
 134             SYNCHRONOUSLY.
 135     """
 136
 137     def __init__(self, stage, n_len, n_mux):
 138         MultiInControl.__init__(self, n_len=n_len)
 139         self.stage = stage
 140         self.p_mux = p_mux
 141
 142         # set up the input and output data
 143         for i in range(p_len):
 144             self.p[i].i_data = stage.ispec() # input type
 145         self.n.o_data = stage.ospec()
 146
 147     def elaborate(self, platform):
 148         m = Module()
 149
 150         m.submodules += self.p_mux
 151
 152         # need buffer register conforming to *input* spec
 153         r_data = self.stage.ispec() # input type
 154         if hasattr(self.stage, "setup"):
 155             self.stage.setup(m, r_data)
 156
 157         data_valid = []
 158         n_i_readyn = []
 159         n_len = len(self.n)
 160         for i in range(n_len):
 161             data_valid.append(Signal(name="data_valid", reset_less=True))
 162             n_i_readyn.append(Signal(name="n_i_readyn", reset_less=True))
 163         n_i_readyn = Array(n_i_readyn)
 164         data_valid = Array(data_valid)
 165
 166         p_i_valid = Signal(reset_less=True)
 167         m.d.comb += p_i_valid.eq(self.p.i_valid_logic())
 168
 169         mid = self.p_mux.m_id
 170
 171         for i in range(p_len):
 172             m.d.comb += data_valid[i].eq(0)
 173             m.d.comb += n_i_readyn[i].eq(1)
 174             m.d.comb += self.n[i].o_valid.eq(data_valid[i])
 175         m.d.comb += self.p[mid].o_ready.eq(~data_valid[mid] | self.n.i_ready)
 176         m.d.comb += n_i_readyn[mid].eq(~self.n[mid].i_ready & data_valid[mid])
 177         anyvalid = Signal(i, reset_less=True)
 178         av = []
 179         for i in range(p_len):
 180             av.append(~data_valid[i] | self.n[i].i_ready)
 181         anyvalid = Cat(*av)
 182         m.d.comb += self.p.o_ready.eq(anyvalid.bool())
 183         m.d.comb += data_valid[mid].eq(p_i_valid | \
 184                                     (n_i_readyn[mid] & data_valid[mid]))
 185
 186         with m.If(self.p.i_valid & self.p.o_ready):
 187             m.d.comb += eq(r_data, self.p.i_data)
 188         m.d.comb += eq(self.n[mid].o_data, self.stage.process(r_data))
 189
 190         return m
 191
 192
 193 class CombMultiInPipeline(MultiInControl):
 194     """ A multi-input Combinatorial block conforming to the Pipeline API
 195
 196         Attributes:
 197         -----------
 198         p.i_data : StageInput, shaped according to ispec
 199             The pipeline input
 200         p.o_data : StageOutput, shaped according to ospec
 201             The pipeline output
 202         r_data : input_shape according to ispec
 203             A temporary (buffered) copy of a prior (valid) input.
 204             This is HELD if the output is not ready.  It is updated
 205             SYNCHRONOUSLY.
 206     """
 207
 208     def __init__(self, stage, p_len, p_mux):
 209         MultiInControl.__init__(self, p_len=p_len)
 210         self.stage = stage
 211         self.p_mux = p_mux
 212
 213         # set up the input and output data
 214         for i in range(p_len):
 215             self.p[i].i_data = stage.ispec() # input type
 216         self.n.o_data = stage.ospec()
 217
 218     def elaborate(self, platform):
 219         m = Module()
 220
 221         m.submodules += self.p_mux
 222
 223         # need an array of buffer registers conforming to *input* spec
 224         r_data = []
 225         data_valid = []
 226         p_i_valid = []
 227         n_i_readyn = []
 228         p_len = len(self.p)
 229         for i in range(p_len):
 230             r = self.stage.ispec() # input type
 231             r_data.append(r)
 232             data_valid.append(Signal(name="data_valid", reset_less=True))
 233             p_i_valid.append(Signal(name="p_i_valid", reset_less=True))
 234             n_i_readyn.append(Signal(name="n_i_readyn", reset_less=True))
 235             if hasattr(self.stage, "setup"):
 236                 self.stage.setup(m, r)
 237         if len(r_data) > 1:
 238             r_data = Array(r_data)
 239             p_i_valid = Array(p_i_valid)
 240             n_i_readyn = Array(n_i_readyn)
 241             data_valid = Array(data_valid)
 242
 243         mid = self.p_mux.m_id
 244         for i in range(p_len):
 245             m.d.comb += data_valid[i].eq(0)
 246             m.d.comb += n_i_readyn[i].eq(1)
 247             m.d.comb += p_i_valid[i].eq(0)
 248             m.d.comb += self.p[i].o_ready.eq(0)
 249         m.d.comb += p_i_valid[mid].eq(self.p_mux.active)
 250         m.d.comb += self.p[mid].o_ready.eq(~data_valid[mid] | self.n.i_ready)
 251         m.d.comb += n_i_readyn[mid].eq(~self.n.i_ready & data_valid[mid])
 252         anyvalid = Signal(i, reset_less=True)
 253         av = []
 254         for i in range(p_len):
 255             av.append(data_valid[i])
 256         anyvalid = Cat(*av)
 257         m.d.comb += self.n.o_valid.eq(anyvalid.bool())
 258         m.d.comb += data_valid[mid].eq(p_i_valid[mid] | \
 259                                     (n_i_readyn[mid] & data_valid[mid]))
 260
 261         for i in range(p_len):
 262             vr = Signal(reset_less=True)
 263             m.d.comb += vr.eq(self.p[i].i_valid & self.p[i].o_ready)
 264             with m.If(vr):
 265                 m.d.comb += eq(r_data[i], self.p[i].i_data)
 266
 267         m.d.comb += eq(self.n.o_data, self.stage.process(r_data[mid]))
 268
 269         return m
 270
 271
 272 class InputPriorityArbiter:
 273     def __init__(self, pipe, num_rows):
 274         self.pipe = pipe
 275         self.num_rows = num_rows
 276         self.mmax = int(log(self.num_rows) / log(2))
 277         self.m_id = Signal(self.mmax, reset_less=True) # multiplex id
 278         self.active = Signal(reset_less=True)
 279
 280     def elaborate(self, platform):
 281         m = Module()
 282
 283         assert len(self.pipe.p) == self.num_rows, \
 284                 "must declare input to be same size"
 285         pe = PriorityEncoder(self.num_rows)
 286         m.submodules.selector = pe
 287
 288         # connect priority encoder
 289         in_ready = []
 290         for i in range(self.num_rows):
 291             p_i_valid = Signal(reset_less=True)
 292             m.d.comb += p_i_valid.eq(self.pipe.p[i].i_valid_logic())
 293             in_ready.append(p_i_valid)
 294         m.d.comb += pe.i.eq(Cat(*in_ready)) # array of input "valids"
 295         m.d.comb += self.active.eq(~pe.n)   # encoder active (one input valid)
 296         m.d.comb += self.m_id.eq(pe.o)       # output one active input
 297
 298         return m
 299
 300     def ports(self):
 301         return [self.m_id, self.active]
 302
 303
 304
 305 class ExamplePipeline(CombMultiInPipeline):
 306     """ an example of how to use the combinatorial pipeline.
 307     """
 308
 309     def __init__(self, p_len=2):
 310         p_mux = InputPriorityArbiter(self, p_len)
 311         CombMultiInPipeline.__init__(self, ExampleStage, p_len, p_mux)
 312
 313
 314 if __name__ == '__main__':
 315
 316     dut = ExamplePipeline()
 317     vl = rtlil.convert(dut, ports=dut.ports())
 318     with open("test_combpipe.il", "w") as f:
 319         f.write(vl)