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090e117be707d2982b161d4ba7bf1bc31a36da63
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 #from fpbase import FPNumShiftMultiRight
13
14
15 class FPState(FPBase):
16 def __init__(self, state_from):
17 self.state_from = state_from
18
19 def set_inputs(self, inputs):
20 self.inputs = inputs
21 for k,v in inputs.items():
22 setattr(self, k, v)
23
24 def set_outputs(self, outputs):
25 self.outputs = outputs
26 for k,v in outputs.items():
27 setattr(self, k, v)
28
29
30 class FPGetSyncOpsMod:
31 def __init__(self, width, num_ops=2):
32 self.width = width
33 self.num_ops = num_ops
34 inops = []
35 outops = []
36 for i in range(num_ops):
37 inops.append(Signal(width, reset_less=True))
38 outops.append(Signal(width, reset_less=True))
39 self.in_op = inops
40 self.out_op = outops
41 self.stb = Signal(num_ops)
42 self.ack = Signal()
43 self.ready = Signal(reset_less=True)
44 self.out_decode = Signal(reset_less=True)
45
46 def elaborate(self, platform):
47 m = Module()
48 m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
49 m.d.comb += self.out_decode.eq(self.ack & self.ready)
50 with m.If(self.out_decode):
51 for i in range(self.num_ops):
52 m.d.comb += [
53 self.out_op[i].eq(self.in_op[i]),
54 ]
55 return m
56
57 def ports(self):
58 return self.in_op + self.out_op + [self.stb, self.ack]
59
60
61 class FPOps(Trigger):
62 def __init__(self, width, num_ops):
63 Trigger.__init__(self)
64 self.width = width
65 self.num_ops = num_ops
66
67 res = []
68 for i in range(num_ops):
69 res.append(Signal(width))
70 self.v = Array(res)
71
72 def ports(self):
73 res = []
74 for i in range(self.num_ops):
75 res.append(self.v[i])
76 res.append(self.ack)
77 res.append(self.stb)
78 return res
79
80
81 class InputGroup:
82 def __init__(self, width, num_ops=2, num_rows=4):
83 self.width = width
84 self.num_ops = num_ops
85 self.num_rows = num_rows
86 self.mmax = int(log(self.num_rows) / log(2))
87 self.rs = []
88 self.mid = Signal(self.mmax, reset_less=True) # multiplex id
89 for i in range(num_rows):
90 self.rs.append(FPGetSyncOpsMod(width, num_ops))
91 self.rs = Array(self.rs)
92
93 self.out_op = FPOps(width, num_ops)
94
95 def elaborate(self, platform):
96 m = Module()
97
98 pe = PriorityEncoder(self.num_rows)
99 m.submodules.selector = pe
100 m.submodules.out_op = self.out_op
101 m.submodules += self.rs
102
103 # connect priority encoder
104 in_ready = []
105 for i in range(self.num_rows):
106 in_ready.append(self.rs[i].ready)
107 m.d.comb += pe.i.eq(Cat(*in_ready))
108
109 active = Signal(reset_less=True)
110 out_en = Signal(reset_less=True)
111 m.d.comb += active.eq(~pe.n) # encoder active
112 m.d.comb += out_en.eq(active & self.out_op.trigger)
113
114 # encoder active: ack relevant input, record MID, pass output
115 with m.If(out_en):
116 rs = self.rs[pe.o]
117 m.d.sync += self.mid.eq(pe.o)
118 m.d.sync += rs.ack.eq(0)
119 m.d.sync += self.out_op.stb.eq(0)
120 for j in range(self.num_ops):
121 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
122 with m.Else():
123 m.d.sync += self.out_op.stb.eq(1)
124 # acks all default to zero
125 for i in range(self.num_rows):
126 m.d.sync += self.rs[i].ack.eq(1)
127
128 return m
129
130 def ports(self):
131 res = []
132 for i in range(self.num_rows):
133 inop = self.rs[i]
134 res += inop.in_op + [inop.stb]
135 return self.out_op.ports() + res + [self.mid]
136
137
138 class FPGetOpMod:
139 def __init__(self, width):
140 self.in_op = FPOp(width)
141 self.out_op = Signal(width)
142 self.out_decode = Signal(reset_less=True)
143
144 def elaborate(self, platform):
145 m = Module()
146 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
147 m.submodules.get_op_in = self.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m.If(self.out_decode):
150 m.d.comb += [
151 self.out_op.eq(self.in_op.v),
152 ]
153 return m
154
155
156 class FPGetOp(FPState):
157 """ gets operand
158 """
159
160 def __init__(self, in_state, out_state, in_op, width):
161 FPState.__init__(self, in_state)
162 self.out_state = out_state
163 self.mod = FPGetOpMod(width)
164 self.in_op = in_op
165 self.out_op = Signal(width)
166 self.out_decode = Signal(reset_less=True)
167
168 def setup(self, m, in_op):
169 """ links module to inputs and outputs
170 """
171 setattr(m.submodules, self.state_from, self.mod)
172 m.d.comb += self.mod.in_op.eq(in_op)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m.d.comb += self.out_decode.eq(self.mod.out_decode)
175
176 def action(self, m):
177 with m.If(self.out_decode):
178 m.next = self.out_state
179 m.d.sync += [
180 self.in_op.ack.eq(0),
181 self.out_op.eq(self.mod.out_op)
182 ]
183 with m.Else():
184 m.d.sync += self.in_op.ack.eq(1)
185
186
187 class FPGet2OpMod(Trigger):
188 def __init__(self, width):
189 Trigger.__init__(self)
190 self.in_op1 = Signal(width, reset_less=True)
191 self.in_op2 = Signal(width, reset_less=True)
192 self.out_op1 = FPNumIn(None, width)
193 self.out_op2 = FPNumIn(None, width)
194
195 def elaborate(self, platform):
196 m = Trigger.elaborate(self, platform)
197 #m.submodules.get_op_in = self.in_op
198 m.submodules.get_op1_out = self.out_op1
199 m.submodules.get_op2_out = self.out_op2
200 with m.If(self.trigger):
201 m.d.comb += [
202 self.out_op1.decode(self.in_op1),
203 self.out_op2.decode(self.in_op2),
204 ]
205 return m
206
207
208 class FPGet2Op(FPState):
209 """ gets operands
210 """
211
212 def __init__(self, in_state, out_state, in_op1, in_op2, width):
213 FPState.__init__(self, in_state)
214 self.out_state = out_state
215 self.mod = FPGet2OpMod(width)
216 self.in_op1 = in_op1
217 self.in_op2 = in_op2
218 self.out_op1 = FPNumIn(None, width)
219 self.out_op2 = FPNumIn(None, width)
220 self.in_stb = Signal(reset_less=True)
221 self.out_ack = Signal(reset_less=True)
222 self.out_decode = Signal(reset_less=True)
223
224 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
225 """ links module to inputs and outputs
226 """
227 m.submodules.get_ops = self.mod
228 m.d.comb += self.mod.in_op1.eq(in_op1)
229 m.d.comb += self.mod.in_op2.eq(in_op2)
230 m.d.comb += self.mod.stb.eq(in_stb)
231 m.d.comb += self.out_ack.eq(self.mod.ack)
232 m.d.comb += self.out_decode.eq(self.mod.trigger)
233 m.d.comb += in_ack.eq(self.mod.ack)
234
235 def action(self, m):
236 with m.If(self.out_decode):
237 m.next = self.out_state
238 m.d.sync += [
239 self.mod.ack.eq(0),
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self.out_op1.eq(self.mod.out_op1),
243 self.out_op2.eq(self.mod.out_op2)
244 ]
245 with m.Else():
246 m.d.sync += self.mod.ack.eq(1)
247
248 class FPNumBase2Ops:
249
250 def __init__(self, width, m_extra=True):
251 self.a = FPNumBase(width, m_extra)
252 self.b = FPNumBase(width, m_extra)
253
254 def eq(self, i):
255 return [self.a.eq(i.a), self.b.eq(i.b)]
256
257
258 class FPAddSpecialCasesMod:
259 """ special cases: NaNs, infs, zeros, denormalised
260 NOTE: some of these are unique to add. see "Special Operations"
261 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
262 """
263
264 def __init__(self, width):
265 self.width = width
266 self.i = self.ispec()
267 self.out_z = self.ospec()
268 self.out_do_z = Signal(reset_less=True)
269
270 def ispec(self):
271 return FPNumBase2Ops(self.width)
272
273 def ospec(self):
274 return FPNumOut(self.width, False)
275
276 def setup(self, m, in_a, in_b, out_do_z):
277 """ links module to inputs and outputs
278 """
279 m.submodules.specialcases = self
280 m.d.comb += self.i.a.eq(in_a)
281 m.d.comb += self.i.b.eq(in_b)
282 m.d.comb += out_do_z.eq(self.out_do_z)
283
284 def elaborate(self, platform):
285 m = Module()
286
287 m.submodules.sc_in_a = self.i.a
288 m.submodules.sc_in_b = self.i.b
289 m.submodules.sc_out_z = self.out_z
290
291 s_nomatch = Signal()
292 m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
293
294 m_match = Signal()
295 m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
296
297 # if a is NaN or b is NaN return NaN
298 with m.If(self.i.a.is_nan | self.i.b.is_nan):
299 m.d.comb += self.out_do_z.eq(1)
300 m.d.comb += self.out_z.nan(0)
301
302 # XXX WEIRDNESS for FP16 non-canonical NaN handling
303 # under review
304
305 ## if a is zero and b is NaN return -b
306 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
307 # m.d.comb += self.out_do_z.eq(1)
308 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
309
310 ## if b is zero and a is NaN return -a
311 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
312 # m.d.comb += self.out_do_z.eq(1)
313 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
314
315 ## if a is -zero and b is NaN return -b
316 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
317 # m.d.comb += self.out_do_z.eq(1)
318 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
319
320 ## if b is -zero and a is NaN return -a
321 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
322 # m.d.comb += self.out_do_z.eq(1)
323 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
324
325 # if a is inf return inf (or NaN)
326 with m.Elif(self.i.a.is_inf):
327 m.d.comb += self.out_do_z.eq(1)
328 m.d.comb += self.out_z.inf(self.i.a.s)
329 # if a is inf and signs don't match return NaN
330 with m.If(self.i.b.exp_128 & s_nomatch):
331 m.d.comb += self.out_z.nan(0)
332
333 # if b is inf return inf
334 with m.Elif(self.i.b.is_inf):
335 m.d.comb += self.out_do_z.eq(1)
336 m.d.comb += self.out_z.inf(self.i.b.s)
337
338 # if a is zero and b zero return signed-a/b
339 with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
340 m.d.comb += self.out_do_z.eq(1)
341 m.d.comb += self.out_z.create(self.i.a.s & self.i.b.s,
342 self.i.b.e,
343 self.i.b.m[3:-1])
344
345 # if a is zero return b
346 with m.Elif(self.i.a.is_zero):
347 m.d.comb += self.out_do_z.eq(1)
348 m.d.comb += self.out_z.create(self.i.b.s, self.i.b.e,
349 self.i.b.m[3:-1])
350
351 # if b is zero return a
352 with m.Elif(self.i.b.is_zero):
353 m.d.comb += self.out_do_z.eq(1)
354 m.d.comb += self.out_z.create(self.i.a.s, self.i.a.e,
355 self.i.a.m[3:-1])
356
357 # if a equal to -b return zero (+ve zero)
358 with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
359 m.d.comb += self.out_do_z.eq(1)
360 m.d.comb += self.out_z.zero(0)
361
362 # Denormalised Number checks
363 with m.Else():
364 m.d.comb += self.out_do_z.eq(0)
365
366 return m
367
368
369 class FPID:
370 def __init__(self, id_wid):
371 self.id_wid = id_wid
372 if self.id_wid:
373 self.in_mid = Signal(id_wid, reset_less=True)
374 self.out_mid = Signal(id_wid, reset_less=True)
375 else:
376 self.in_mid = None
377 self.out_mid = None
378
379 def idsync(self, m):
380 if self.id_wid is not None:
381 m.d.sync += self.out_mid.eq(self.in_mid)
382
383
384 class FPAddSpecialCases(FPState, FPID):
385 """ special cases: NaNs, infs, zeros, denormalised
386 NOTE: some of these are unique to add. see "Special Operations"
387 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
388 """
389
390 def __init__(self, width, id_wid):
391 FPState.__init__(self, "special_cases")
392 FPID.__init__(self, id_wid)
393 self.mod = FPAddSpecialCasesMod(width)
394 self.out_z = self.mod.ospec()
395 self.out_do_z = Signal(reset_less=True)
396
397 def setup(self, m, in_a, in_b, in_mid):
398 """ links module to inputs and outputs
399 """
400 self.mod.setup(m, in_a, in_b, self.out_do_z)
401 if self.in_mid is not None:
402 m.d.comb += self.in_mid.eq(in_mid)
403
404 def action(self, m):
405 self.idsync(m)
406 with m.If(self.out_do_z):
407 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
408 m.next = "put_z"
409 with m.Else():
410 m.next = "denormalise"
411
412
413 class FPAddSpecialCasesDeNorm(FPState, FPID):
414 """ special cases: NaNs, infs, zeros, denormalised
415 NOTE: some of these are unique to add. see "Special Operations"
416 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
417 """
418
419 def __init__(self, width, id_wid):
420 FPState.__init__(self, "special_cases")
421 FPID.__init__(self, id_wid)
422 self.smod = FPAddSpecialCasesMod(width)
423 self.out_z = self.smod.ospec()
424 self.out_do_z = Signal(reset_less=True)
425
426 self.dmod = FPAddDeNormMod(width)
427 self.o = self.dmod.ospec()
428
429 def setup(self, m, in_a, in_b, in_mid):
430 """ links module to inputs and outputs
431 """
432 self.smod.setup(m, in_a, in_b, self.out_do_z)
433 self.dmod.setup(m, in_a, in_b)
434 if self.in_mid is not None:
435 m.d.comb += self.in_mid.eq(in_mid)
436
437 def action(self, m):
438 self.idsync(m)
439 with m.If(self.out_do_z):
440 m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
441 m.next = "put_z"
442 with m.Else():
443 m.next = "align"
444 m.d.sync += self.o.a.eq(self.dmod.o.a)
445 m.d.sync += self.o.b.eq(self.dmod.o.b)
446
447
448 class FPAddDeNormMod(FPState):
449
450 def __init__(self, width):
451 self.width = width
452 self.i = self.ispec()
453 self.o = self.ospec()
454
455 def ispec(self):
456 return FPNumBase2Ops(self.width)
457
458 def ospec(self):
459 return FPNumBase2Ops(self.width)
460
461 def setup(self, m, in_a, in_b):
462 """ links module to inputs and outputs
463 """
464 m.submodules.denormalise = self
465 m.d.comb += self.i.a.eq(in_a)
466 m.d.comb += self.i.b.eq(in_b)
467
468 def elaborate(self, platform):
469 m = Module()
470 m.submodules.denorm_in_a = self.i.a
471 m.submodules.denorm_in_b = self.i.b
472 m.submodules.denorm_out_a = self.o.a
473 m.submodules.denorm_out_b = self.o.b
474 # hmmm, don't like repeating identical code
475 m.d.comb += self.o.a.eq(self.i.a)
476 with m.If(self.i.a.exp_n127):
477 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
478 with m.Else():
479 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
480
481 m.d.comb += self.o.b.eq(self.i.b)
482 with m.If(self.i.b.exp_n127):
483 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
484 with m.Else():
485 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
486
487 return m
488
489
490 class FPAddDeNorm(FPState, FPID):
491
492 def __init__(self, width, id_wid):
493 FPState.__init__(self, "denormalise")
494 FPID.__init__(self, id_wid)
495 self.mod = FPAddDeNormMod(width)
496 self.out_a = FPNumBase(width)
497 self.out_b = FPNumBase(width)
498
499 def setup(self, m, in_a, in_b, in_mid):
500 """ links module to inputs and outputs
501 """
502 self.mod.setup(m, in_a, in_b)
503 if self.in_mid is not None:
504 m.d.comb += self.in_mid.eq(in_mid)
505
506 def action(self, m):
507 self.idsync(m)
508 # Denormalised Number checks
509 m.next = "align"
510 m.d.sync += self.out_a.eq(self.mod.out_a)
511 m.d.sync += self.out_b.eq(self.mod.out_b)
512
513
514 class FPAddAlignMultiMod(FPState):
515
516 def __init__(self, width):
517 self.in_a = FPNumBase(width)
518 self.in_b = FPNumBase(width)
519 self.out_a = FPNumIn(None, width)
520 self.out_b = FPNumIn(None, width)
521 self.exp_eq = Signal(reset_less=True)
522
523 def elaborate(self, platform):
524 # This one however (single-cycle) will do the shift
525 # in one go.
526
527 m = Module()
528
529 m.submodules.align_in_a = self.in_a
530 m.submodules.align_in_b = self.in_b
531 m.submodules.align_out_a = self.out_a
532 m.submodules.align_out_b = self.out_b
533
534 # NOTE: this does *not* do single-cycle multi-shifting,
535 # it *STAYS* in the align state until exponents match
536
537 # exponent of a greater than b: shift b down
538 m.d.comb += self.exp_eq.eq(0)
539 m.d.comb += self.out_a.eq(self.in_a)
540 m.d.comb += self.out_b.eq(self.in_b)
541 agtb = Signal(reset_less=True)
542 altb = Signal(reset_less=True)
543 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
544 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
545 with m.If(agtb):
546 m.d.comb += self.out_b.shift_down(self.in_b)
547 # exponent of b greater than a: shift a down
548 with m.Elif(altb):
549 m.d.comb += self.out_a.shift_down(self.in_a)
550 # exponents equal: move to next stage.
551 with m.Else():
552 m.d.comb += self.exp_eq.eq(1)
553 return m
554
555
556 class FPAddAlignMulti(FPState, FPID):
557
558 def __init__(self, width, id_wid):
559 FPID.__init__(self, id_wid)
560 FPState.__init__(self, "align")
561 self.mod = FPAddAlignMultiMod(width)
562 self.out_a = FPNumIn(None, width)
563 self.out_b = FPNumIn(None, width)
564 self.exp_eq = Signal(reset_less=True)
565
566 def setup(self, m, in_a, in_b, in_mid):
567 """ links module to inputs and outputs
568 """
569 m.submodules.align = self.mod
570 m.d.comb += self.mod.in_a.eq(in_a)
571 m.d.comb += self.mod.in_b.eq(in_b)
572 #m.d.comb += self.out_a.eq(self.mod.out_a)
573 #m.d.comb += self.out_b.eq(self.mod.out_b)
574 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
575 if self.in_mid is not None:
576 m.d.comb += self.in_mid.eq(in_mid)
577
578 def action(self, m):
579 self.idsync(m)
580 m.d.sync += self.out_a.eq(self.mod.out_a)
581 m.d.sync += self.out_b.eq(self.mod.out_b)
582 with m.If(self.exp_eq):
583 m.next = "add_0"
584
585
586 class FPNumIn2Ops:
587
588 def __init__(self, width):
589 self.a = FPNumIn(None, width)
590 self.b = FPNumIn(None, width)
591
592 def eq(self, i):
593 return [self.a.eq(i.a), self.b.eq(i.b)]
594
595
596 class FPAddAlignSingleMod:
597
598 def __init__(self, width):
599 self.width = width
600 self.i = self.ispec()
601 self.o = self.ospec()
602
603 def ispec(self):
604 return FPNumBase2Ops(self.width)
605
606 def ospec(self):
607 return FPNumIn2Ops(self.width)
608
609 def setup(self, m, in_a, in_b):
610 """ links module to inputs and outputs
611 """
612 m.submodules.align = self
613 m.d.comb += self.i.a.eq(in_a)
614 m.d.comb += self.i.b.eq(in_b)
615
616 def elaborate(self, platform):
617 """ Aligns A against B or B against A, depending on which has the
618 greater exponent. This is done in a *single* cycle using
619 variable-width bit-shift
620
621 the shifter used here is quite expensive in terms of gates.
622 Mux A or B in (and out) into temporaries, as only one of them
623 needs to be aligned against the other
624 """
625 m = Module()
626
627 m.submodules.align_in_a = self.i.a
628 m.submodules.align_in_b = self.i.b
629 m.submodules.align_out_a = self.o.a
630 m.submodules.align_out_b = self.o.b
631
632 # temporary (muxed) input and output to be shifted
633 t_inp = FPNumBase(self.width)
634 t_out = FPNumIn(None, self.width)
635 espec = (len(self.i.a.e), True)
636 msr = MultiShiftRMerge(self.i.a.m_width, espec)
637 m.submodules.align_t_in = t_inp
638 m.submodules.align_t_out = t_out
639 m.submodules.multishift_r = msr
640
641 ediff = Signal(espec, reset_less=True)
642 ediffr = Signal(espec, reset_less=True)
643 tdiff = Signal(espec, reset_less=True)
644 elz = Signal(reset_less=True)
645 egz = Signal(reset_less=True)
646
647 # connect multi-shifter to t_inp/out mantissa (and tdiff)
648 m.d.comb += msr.inp.eq(t_inp.m)
649 m.d.comb += msr.diff.eq(tdiff)
650 m.d.comb += t_out.m.eq(msr.m)
651 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
652 m.d.comb += t_out.s.eq(t_inp.s)
653
654 m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
655 m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
656 m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
657 m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
658
659 # default: A-exp == B-exp, A and B untouched (fall through)
660 m.d.comb += self.o.a.eq(self.i.a)
661 m.d.comb += self.o.b.eq(self.i.b)
662 # only one shifter (muxed)
663 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
664 # exponent of a greater than b: shift b down
665 with m.If(egz):
666 m.d.comb += [t_inp.eq(self.i.b),
667 tdiff.eq(ediff),
668 self.o.b.eq(t_out),
669 self.o.b.s.eq(self.i.b.s), # whoops forgot sign
670 ]
671 # exponent of b greater than a: shift a down
672 with m.Elif(elz):
673 m.d.comb += [t_inp.eq(self.i.a),
674 tdiff.eq(ediffr),
675 self.o.a.eq(t_out),
676 self.o.a.s.eq(self.i.a.s), # whoops forgot sign
677 ]
678 return m
679
680
681 class FPAddAlignSingle(FPState, FPID):
682
683 def __init__(self, width, id_wid):
684 FPState.__init__(self, "align")
685 FPID.__init__(self, id_wid)
686 self.mod = FPAddAlignSingleMod(width)
687 self.out_a = FPNumIn(None, width)
688 self.out_b = FPNumIn(None, width)
689
690 def setup(self, m, in_a, in_b, in_mid):
691 """ links module to inputs and outputs
692 """
693 self.mod.setup(m, in_a, in_b)
694 if self.in_mid is not None:
695 m.d.comb += self.in_mid.eq(in_mid)
696
697 def action(self, m):
698 self.idsync(m)
699 # NOTE: could be done as comb
700 m.d.sync += self.out_a.eq(self.mod.out_a)
701 m.d.sync += self.out_b.eq(self.mod.out_b)
702 m.next = "add_0"
703
704
705 class FPAddAlignSingleAdd(FPState, FPID):
706
707 def __init__(self, width, id_wid):
708 FPState.__init__(self, "align")
709 FPID.__init__(self, id_wid)
710 self.mod = FPAddAlignSingleMod(width)
711 self.o = self.mod.ospec()
712
713 self.a0mod = FPAddStage0Mod(width)
714 self.a0_out_z = FPNumBase(width, False)
715 self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
716 self.a0_out_z = FPNumBase(width, False)
717
718 self.a1mod = FPAddStage1Mod(width)
719 self.out_z = FPNumBase(width, False)
720 self.out_of = Overflow()
721
722 def setup(self, m, in_a, in_b, in_mid):
723 """ links module to inputs and outputs
724 """
725 self.mod.setup(m, in_a, in_b)
726 m.d.comb += self.o.eq(self.mod.o)
727
728 self.a0mod.setup(m, self.o.a, self.o.b)
729 m.d.comb += self.a0_out_z.eq(self.a0mod.out_z)
730 m.d.comb += self.out_tot.eq(self.a0mod.out_tot)
731
732 self.a1mod.setup(m, self.out_tot, self.a0_out_z)
733
734 if self.in_mid is not None:
735 m.d.comb += self.in_mid.eq(in_mid)
736
737 def action(self, m):
738 self.idsync(m)
739 m.d.sync += self.out_of.eq(self.a1mod.out_of)
740 m.d.sync += self.out_z.eq(self.a1mod.out_z)
741 m.next = "normalise_1"
742
743
744 class FPAddStage0Mod:
745
746 def __init__(self, width):
747 self.in_a = FPNumBase(width)
748 self.in_b = FPNumBase(width)
749 self.in_z = FPNumBase(width, False)
750 self.out_z = FPNumBase(width, False)
751 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
752
753 def setup(self, m, in_a, in_b):
754 """ links module to inputs and outputs
755 """
756 m.submodules.add0 = self
757 m.d.comb += self.in_a.eq(in_a)
758 m.d.comb += self.in_b.eq(in_b)
759
760 def elaborate(self, platform):
761 m = Module()
762 m.submodules.add0_in_a = self.in_a
763 m.submodules.add0_in_b = self.in_b
764 m.submodules.add0_out_z = self.out_z
765
766 m.d.comb += self.out_z.e.eq(self.in_a.e)
767
768 # store intermediate tests (and zero-extended mantissas)
769 seq = Signal(reset_less=True)
770 mge = Signal(reset_less=True)
771 am0 = Signal(len(self.in_a.m)+1, reset_less=True)
772 bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
773 m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
774 mge.eq(self.in_a.m >= self.in_b.m),
775 am0.eq(Cat(self.in_a.m, 0)),
776 bm0.eq(Cat(self.in_b.m, 0))
777 ]
778 # same-sign (both negative or both positive) add mantissas
779 with m.If(seq):
780 m.d.comb += [
781 self.out_tot.eq(am0 + bm0),
782 self.out_z.s.eq(self.in_a.s)
783 ]
784 # a mantissa greater than b, use a
785 with m.Elif(mge):
786 m.d.comb += [
787 self.out_tot.eq(am0 - bm0),
788 self.out_z.s.eq(self.in_a.s)
789 ]
790 # b mantissa greater than a, use b
791 with m.Else():
792 m.d.comb += [
793 self.out_tot.eq(bm0 - am0),
794 self.out_z.s.eq(self.in_b.s)
795 ]
796 return m
797
798
799 class FPAddStage0(FPState, FPID):
800 """ First stage of add. covers same-sign (add) and subtract
801 special-casing when mantissas are greater or equal, to
802 give greatest accuracy.
803 """
804
805 def __init__(self, width, id_wid):
806 FPState.__init__(self, "add_0")
807 FPID.__init__(self, id_wid)
808 self.mod = FPAddStage0Mod(width)
809 self.out_z = FPNumBase(width, False)
810 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
811
812 def setup(self, m, in_a, in_b, in_mid):
813 """ links module to inputs and outputs
814 """
815 self.mod.setup(m, in_a, in_b)
816 if self.in_mid is not None:
817 m.d.comb += self.in_mid.eq(in_mid)
818
819 def action(self, m):
820 self.idsync(m)
821 # NOTE: these could be done as combinatorial (merge add0+add1)
822 m.d.sync += self.out_z.eq(self.mod.out_z)
823 m.d.sync += self.out_tot.eq(self.mod.out_tot)
824 m.next = "add_1"
825
826
827 class FPAddStage1Mod(FPState):
828 """ Second stage of add: preparation for normalisation.
829 detects when tot sum is too big (tot[27] is kinda a carry bit)
830 """
831
832 def __init__(self, width):
833 self.out_norm = Signal(reset_less=True)
834 self.in_z = FPNumBase(width, False)
835 self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
836 self.out_z = FPNumBase(width, False)
837 self.out_of = Overflow()
838
839 def setup(self, m, in_tot, in_z):
840 """ links module to inputs and outputs
841 """
842 m.submodules.add1 = self
843 m.submodules.add1_out_overflow = self.out_of
844
845 m.d.comb += self.in_z.eq(in_z)
846 m.d.comb += self.in_tot.eq(in_tot)
847
848 def elaborate(self, platform):
849 m = Module()
850 #m.submodules.norm1_in_overflow = self.in_of
851 #m.submodules.norm1_out_overflow = self.out_of
852 #m.submodules.norm1_in_z = self.in_z
853 #m.submodules.norm1_out_z = self.out_z
854 m.d.comb += self.out_z.eq(self.in_z)
855 # tot[-1] (MSB) gets set when the sum overflows. shift result down
856 with m.If(self.in_tot[-1]):
857 m.d.comb += [
858 self.out_z.m.eq(self.in_tot[4:]),
859 self.out_of.m0.eq(self.in_tot[4]),
860 self.out_of.guard.eq(self.in_tot[3]),
861 self.out_of.round_bit.eq(self.in_tot[2]),
862 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
863 self.out_z.e.eq(self.in_z.e + 1)
864 ]
865 # tot[-1] (MSB) zero case
866 with m.Else():
867 m.d.comb += [
868 self.out_z.m.eq(self.in_tot[3:]),
869 self.out_of.m0.eq(self.in_tot[3]),
870 self.out_of.guard.eq(self.in_tot[2]),
871 self.out_of.round_bit.eq(self.in_tot[1]),
872 self.out_of.sticky.eq(self.in_tot[0])
873 ]
874 return m
875
876
877 class FPAddStage1(FPState, FPID):
878
879 def __init__(self, width, id_wid):
880 FPState.__init__(self, "add_1")
881 FPID.__init__(self, id_wid)
882 self.mod = FPAddStage1Mod(width)
883 self.out_z = FPNumBase(width, False)
884 self.out_of = Overflow()
885 self.norm_stb = Signal()
886
887 def setup(self, m, in_tot, in_z, in_mid):
888 """ links module to inputs and outputs
889 """
890 self.mod.setup(m, in_tot, in_z)
891
892 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
893
894 if self.in_mid is not None:
895 m.d.comb += self.in_mid.eq(in_mid)
896
897 def action(self, m):
898 self.idsync(m)
899 m.d.sync += self.out_of.eq(self.mod.out_of)
900 m.d.sync += self.out_z.eq(self.mod.out_z)
901 m.d.sync += self.norm_stb.eq(1)
902 m.next = "normalise_1"
903
904
905 class FPNormaliseModSingle:
906
907 def __init__(self, width):
908 self.width = width
909 self.in_z = FPNumBase(width, False)
910 self.out_z = FPNumBase(width, False)
911
912 def setup(self, m, in_z, out_z, modname):
913 """ links module to inputs and outputs
914 """
915 m.submodules.normalise = self
916 m.d.comb += self.in_z.eq(in_z)
917 m.d.comb += out_z.eq(self.out_z)
918
919 def elaborate(self, platform):
920 m = Module()
921
922 mwid = self.out_z.m_width+2
923 pe = PriorityEncoder(mwid)
924 m.submodules.norm_pe = pe
925
926 m.submodules.norm1_out_z = self.out_z
927 m.submodules.norm1_in_z = self.in_z
928
929 in_z = FPNumBase(self.width, False)
930 in_of = Overflow()
931 m.submodules.norm1_insel_z = in_z
932 m.submodules.norm1_insel_overflow = in_of
933
934 espec = (len(in_z.e), True)
935 ediff_n126 = Signal(espec, reset_less=True)
936 msr = MultiShiftRMerge(mwid, espec)
937 m.submodules.multishift_r = msr
938
939 m.d.comb += in_z.eq(self.in_z)
940 m.d.comb += in_of.eq(self.in_of)
941 # initialise out from in (overridden below)
942 m.d.comb += self.out_z.eq(in_z)
943 m.d.comb += self.out_of.eq(in_of)
944 # normalisation increase/decrease conditions
945 decrease = Signal(reset_less=True)
946 m.d.comb += decrease.eq(in_z.m_msbzero)
947 # decrease exponent
948 with m.If(decrease):
949 # *sigh* not entirely obvious: count leading zeros (clz)
950 # with a PriorityEncoder: to find from the MSB
951 # we reverse the order of the bits.
952 temp_m = Signal(mwid, reset_less=True)
953 temp_s = Signal(mwid+1, reset_less=True)
954 clz = Signal((len(in_z.e), True), reset_less=True)
955 m.d.comb += [
956 # cat round and guard bits back into the mantissa
957 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
958 pe.i.eq(temp_m[::-1]), # inverted
959 clz.eq(pe.o), # count zeros from MSB down
960 temp_s.eq(temp_m << clz), # shift mantissa UP
961 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
962 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
963 ]
964
965 return m
966
967
968 class FPNorm1ModSingle:
969
970 def __init__(self, width):
971 self.width = width
972 self.out_norm = Signal(reset_less=True)
973 self.in_z = FPNumBase(width, False)
974 self.in_of = Overflow()
975 self.out_z = FPNumBase(width, False)
976 self.out_of = Overflow()
977
978 def setup(self, m, in_z, in_of, out_z):
979 """ links module to inputs and outputs
980 """
981 m.submodules.normalise_1 = self
982
983 m.d.comb += self.in_z.eq(in_z)
984 m.d.comb += self.in_of.eq(in_of)
985
986 m.d.comb += out_z.eq(self.out_z)
987
988 def elaborate(self, platform):
989 m = Module()
990
991 mwid = self.out_z.m_width+2
992 pe = PriorityEncoder(mwid)
993 m.submodules.norm_pe = pe
994
995 m.submodules.norm1_out_z = self.out_z
996 m.submodules.norm1_out_overflow = self.out_of
997 m.submodules.norm1_in_z = self.in_z
998 m.submodules.norm1_in_overflow = self.in_of
999
1000 in_z = FPNumBase(self.width, False)
1001 in_of = Overflow()
1002 m.submodules.norm1_insel_z = in_z
1003 m.submodules.norm1_insel_overflow = in_of
1004
1005 espec = (len(in_z.e), True)
1006 ediff_n126 = Signal(espec, reset_less=True)
1007 msr = MultiShiftRMerge(mwid, espec)
1008 m.submodules.multishift_r = msr
1009
1010 m.d.comb += in_z.eq(self.in_z)
1011 m.d.comb += in_of.eq(self.in_of)
1012 # initialise out from in (overridden below)
1013 m.d.comb += self.out_z.eq(in_z)
1014 m.d.comb += self.out_of.eq(in_of)
1015 # normalisation increase/decrease conditions
1016 decrease = Signal(reset_less=True)
1017 increase = Signal(reset_less=True)
1018 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1019 m.d.comb += increase.eq(in_z.exp_lt_n126)
1020 # decrease exponent
1021 with m.If(decrease):
1022 # *sigh* not entirely obvious: count leading zeros (clz)
1023 # with a PriorityEncoder: to find from the MSB
1024 # we reverse the order of the bits.
1025 temp_m = Signal(mwid, reset_less=True)
1026 temp_s = Signal(mwid+1, reset_less=True)
1027 clz = Signal((len(in_z.e), True), reset_less=True)
1028 # make sure that the amount to decrease by does NOT
1029 # go below the minimum non-INF/NaN exponent
1030 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
1031 in_z.exp_sub_n126)
1032 m.d.comb += [
1033 # cat round and guard bits back into the mantissa
1034 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1035 pe.i.eq(temp_m[::-1]), # inverted
1036 clz.eq(limclz), # count zeros from MSB down
1037 temp_s.eq(temp_m << clz), # shift mantissa UP
1038 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
1039 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
1040 self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
1041 # overflow in bits 0..1: got shifted too (leave sticky)
1042 self.out_of.guard.eq(temp_s[1]), # guard
1043 self.out_of.round_bit.eq(temp_s[0]), # round
1044 ]
1045 # increase exponent
1046 with m.Elif(increase):
1047 temp_m = Signal(mwid+1, reset_less=True)
1048 m.d.comb += [
1049 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
1050 in_z.m)),
1051 ediff_n126.eq(in_z.N126 - in_z.e),
1052 # connect multi-shifter to inp/out mantissa (and ediff)
1053 msr.inp.eq(temp_m),
1054 msr.diff.eq(ediff_n126),
1055 self.out_z.m.eq(msr.m[3:]),
1056 self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
1057 # overflow in bits 0..1: got shifted too (leave sticky)
1058 self.out_of.guard.eq(temp_s[2]), # guard
1059 self.out_of.round_bit.eq(temp_s[1]), # round
1060 self.out_of.sticky.eq(temp_s[0]), # sticky
1061 self.out_z.e.eq(in_z.e + ediff_n126),
1062 ]
1063
1064 return m
1065
1066
1067 class FPNorm1ModMulti:
1068
1069 def __init__(self, width, single_cycle=True):
1070 self.width = width
1071 self.in_select = Signal(reset_less=True)
1072 self.out_norm = Signal(reset_less=True)
1073 self.in_z = FPNumBase(width, False)
1074 self.in_of = Overflow()
1075 self.temp_z = FPNumBase(width, False)
1076 self.temp_of = Overflow()
1077 self.out_z = FPNumBase(width, False)
1078 self.out_of = Overflow()
1079
1080 def elaborate(self, platform):
1081 m = Module()
1082
1083 m.submodules.norm1_out_z = self.out_z
1084 m.submodules.norm1_out_overflow = self.out_of
1085 m.submodules.norm1_temp_z = self.temp_z
1086 m.submodules.norm1_temp_of = self.temp_of
1087 m.submodules.norm1_in_z = self.in_z
1088 m.submodules.norm1_in_overflow = self.in_of
1089
1090 in_z = FPNumBase(self.width, False)
1091 in_of = Overflow()
1092 m.submodules.norm1_insel_z = in_z
1093 m.submodules.norm1_insel_overflow = in_of
1094
1095 # select which of temp or in z/of to use
1096 with m.If(self.in_select):
1097 m.d.comb += in_z.eq(self.in_z)
1098 m.d.comb += in_of.eq(self.in_of)
1099 with m.Else():
1100 m.d.comb += in_z.eq(self.temp_z)
1101 m.d.comb += in_of.eq(self.temp_of)
1102 # initialise out from in (overridden below)
1103 m.d.comb += self.out_z.eq(in_z)
1104 m.d.comb += self.out_of.eq(in_of)
1105 # normalisation increase/decrease conditions
1106 decrease = Signal(reset_less=True)
1107 increase = Signal(reset_less=True)
1108 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1109 m.d.comb += increase.eq(in_z.exp_lt_n126)
1110 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1111 # decrease exponent
1112 with m.If(decrease):
1113 m.d.comb += [
1114 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
1115 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1116 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1117 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1118 self.out_of.round_bit.eq(0), # reset round bit
1119 self.out_of.m0.eq(in_of.guard),
1120 ]
1121 # increase exponent
1122 with m.Elif(increase):
1123 m.d.comb += [
1124 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
1125 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1126 self.out_of.guard.eq(in_z.m[0]),
1127 self.out_of.m0.eq(in_z.m[1]),
1128 self.out_of.round_bit.eq(in_of.guard),
1129 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1130 ]
1131
1132 return m
1133
1134
1135 class FPNorm1Single(FPState, FPID):
1136
1137 def __init__(self, width, id_wid, single_cycle=True):
1138 FPID.__init__(self, id_wid)
1139 FPState.__init__(self, "normalise_1")
1140 self.mod = FPNorm1ModSingle(width)
1141 self.out_norm = Signal(reset_less=True)
1142 self.out_z = FPNumBase(width)
1143 self.out_roundz = Signal(reset_less=True)
1144
1145 def setup(self, m, in_z, in_of, in_mid):
1146 """ links module to inputs and outputs
1147 """
1148 self.mod.setup(m, in_z, in_of, self.out_z)
1149
1150 if self.in_mid is not None:
1151 m.d.comb += self.in_mid.eq(in_mid)
1152
1153 def action(self, m):
1154 self.idsync(m)
1155 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1156 m.next = "round"
1157
1158
1159 class FPNorm1Multi(FPState, FPID):
1160
1161 def __init__(self, width, id_wid):
1162 FPID.__init__(self, id_wid)
1163 FPState.__init__(self, "normalise_1")
1164 self.mod = FPNorm1ModMulti(width)
1165 self.stb = Signal(reset_less=True)
1166 self.ack = Signal(reset=0, reset_less=True)
1167 self.out_norm = Signal(reset_less=True)
1168 self.in_accept = Signal(reset_less=True)
1169 self.temp_z = FPNumBase(width)
1170 self.temp_of = Overflow()
1171 self.out_z = FPNumBase(width)
1172 self.out_roundz = Signal(reset_less=True)
1173
1174 def setup(self, m, in_z, in_of, norm_stb, in_mid):
1175 """ links module to inputs and outputs
1176 """
1177 self.mod.setup(m, in_z, in_of, norm_stb,
1178 self.in_accept, self.temp_z, self.temp_of,
1179 self.out_z, self.out_norm)
1180
1181 m.d.comb += self.stb.eq(norm_stb)
1182 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1183
1184 if self.in_mid is not None:
1185 m.d.comb += self.in_mid.eq(in_mid)
1186
1187 def action(self, m):
1188 self.idsync(m)
1189 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1190 m.d.sync += self.temp_of.eq(self.mod.out_of)
1191 m.d.sync += self.temp_z.eq(self.out_z)
1192 with m.If(self.out_norm):
1193 with m.If(self.in_accept):
1194 m.d.sync += [
1195 self.ack.eq(1),
1196 ]
1197 with m.Else():
1198 m.d.sync += self.ack.eq(0)
1199 with m.Else():
1200 # normalisation not required (or done).
1201 m.next = "round"
1202 m.d.sync += self.ack.eq(1)
1203 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1204
1205
1206 class FPNormToPack(FPState, FPID):
1207
1208 def __init__(self, width, id_wid):
1209 FPID.__init__(self, id_wid)
1210 FPState.__init__(self, "normalise_1")
1211 self.width = width
1212
1213 def setup(self, m, in_z, in_of, in_mid):
1214 """ links module to inputs and outputs
1215 """
1216
1217 # Normalisation (chained to input in_z+in_of)
1218 nmod = FPNorm1ModSingle(self.width)
1219 n_out_z = FPNumBase(self.width)
1220 n_out_roundz = Signal(reset_less=True)
1221 nmod.setup(m, in_z, in_of, n_out_z)
1222
1223 # Rounding (chained to normalisation)
1224 rmod = FPRoundMod(self.width)
1225 r_out_z = FPNumBase(self.width)
1226 rmod.setup(m, n_out_z, n_out_roundz)
1227 m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
1228 m.d.comb += r_out_z.eq(rmod.out_z)
1229
1230 # Corrections (chained to rounding)
1231 cmod = FPCorrectionsMod(self.width)
1232 c_out_z = FPNumBase(self.width)
1233 cmod.setup(m, r_out_z)
1234 m.d.comb += c_out_z.eq(cmod.out_z)
1235
1236 # Pack (chained to corrections)
1237 self.pmod = FPPackMod(self.width)
1238 self.out_z = FPNumBase(self.width)
1239 self.pmod.setup(m, c_out_z)
1240
1241 # Multiplex ID
1242 if self.in_mid is not None:
1243 m.d.comb += self.in_mid.eq(in_mid)
1244
1245 def action(self, m):
1246 self.idsync(m) # copies incoming ID to outgoing
1247 m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
1248 m.next = "pack_put_z"
1249
1250
1251 class FPRoundMod:
1252
1253 def __init__(self, width):
1254 self.in_roundz = Signal(reset_less=True)
1255 self.in_z = FPNumBase(width, False)
1256 self.out_z = FPNumBase(width, False)
1257
1258 def setup(self, m, in_z, roundz):
1259 m.submodules.roundz = self
1260
1261 m.d.comb += self.in_z.eq(in_z)
1262 m.d.comb += self.in_roundz.eq(roundz)
1263
1264 def elaborate(self, platform):
1265 m = Module()
1266 m.d.comb += self.out_z.eq(self.in_z)
1267 with m.If(self.in_roundz):
1268 m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
1269 with m.If(self.in_z.m == self.in_z.m1s): # all 1s
1270 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
1271 return m
1272
1273
1274 class FPRound(FPState, FPID):
1275
1276 def __init__(self, width, id_wid):
1277 FPState.__init__(self, "round")
1278 FPID.__init__(self, id_wid)
1279 self.mod = FPRoundMod(width)
1280 self.out_z = FPNumBase(width)
1281
1282 def setup(self, m, in_z, roundz, in_mid):
1283 """ links module to inputs and outputs
1284 """
1285 self.mod.setup(m, in_z, roundz)
1286
1287 if self.in_mid is not None:
1288 m.d.comb += self.in_mid.eq(in_mid)
1289
1290 def action(self, m):
1291 self.idsync(m)
1292 m.d.sync += self.out_z.eq(self.mod.out_z)
1293 m.next = "corrections"
1294
1295
1296 class FPCorrectionsMod:
1297
1298 def __init__(self, width):
1299 self.in_z = FPNumOut(width, False)
1300 self.out_z = FPNumOut(width, False)
1301
1302 def setup(self, m, in_z):
1303 """ links module to inputs and outputs
1304 """
1305 m.submodules.corrections = self
1306 m.d.comb += self.in_z.eq(in_z)
1307
1308 def elaborate(self, platform):
1309 m = Module()
1310 m.submodules.corr_in_z = self.in_z
1311 m.submodules.corr_out_z = self.out_z
1312 m.d.comb += self.out_z.eq(self.in_z)
1313 with m.If(self.in_z.is_denormalised):
1314 m.d.comb += self.out_z.e.eq(self.in_z.N127)
1315 return m
1316
1317
1318 class FPCorrections(FPState, FPID):
1319
1320 def __init__(self, width, id_wid):
1321 FPState.__init__(self, "corrections")
1322 FPID.__init__(self, id_wid)
1323 self.mod = FPCorrectionsMod(width)
1324 self.out_z = FPNumBase(width)
1325
1326 def setup(self, m, in_z, in_mid):
1327 """ links module to inputs and outputs
1328 """
1329 self.mod.setup(m, in_z)
1330 if self.in_mid is not None:
1331 m.d.comb += self.in_mid.eq(in_mid)
1332
1333 def action(self, m):
1334 self.idsync(m)
1335 m.d.sync += self.out_z.eq(self.mod.out_z)
1336 m.next = "pack"
1337
1338
1339 class FPPackMod:
1340
1341 def __init__(self, width):
1342 self.in_z = FPNumOut(width, False)
1343 self.out_z = FPNumOut(width, False)
1344
1345 def setup(self, m, in_z):
1346 """ links module to inputs and outputs
1347 """
1348 m.submodules.pack = self
1349 m.d.comb += self.in_z.eq(in_z)
1350
1351 def elaborate(self, platform):
1352 m = Module()
1353 m.submodules.pack_in_z = self.in_z
1354 with m.If(self.in_z.is_overflowed):
1355 m.d.comb += self.out_z.inf(self.in_z.s)
1356 with m.Else():
1357 m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
1358 return m
1359
1360
1361 class FPPack(FPState, FPID):
1362
1363 def __init__(self, width, id_wid):
1364 FPState.__init__(self, "pack")
1365 FPID.__init__(self, id_wid)
1366 self.mod = FPPackMod(width)
1367 self.out_z = FPNumOut(width, False)
1368
1369 def setup(self, m, in_z, in_mid):
1370 """ links module to inputs and outputs
1371 """
1372 self.mod.setup(m, in_z)
1373 if self.in_mid is not None:
1374 m.d.comb += self.in_mid.eq(in_mid)
1375
1376 def action(self, m):
1377 self.idsync(m)
1378 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1379 m.next = "pack_put_z"
1380
1381
1382 class FPPutZ(FPState):
1383
1384 def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1385 FPState.__init__(self, state)
1386 if to_state is None:
1387 to_state = "get_ops"
1388 self.to_state = to_state
1389 self.in_z = in_z
1390 self.out_z = out_z
1391 self.in_mid = in_mid
1392 self.out_mid = out_mid
1393
1394 def action(self, m):
1395 if self.in_mid is not None:
1396 m.d.sync += self.out_mid.eq(self.in_mid)
1397 m.d.sync += [
1398 self.out_z.v.eq(self.in_z.v)
1399 ]
1400 with m.If(self.out_z.stb & self.out_z.ack):
1401 m.d.sync += self.out_z.stb.eq(0)
1402 m.next = self.to_state
1403 with m.Else():
1404 m.d.sync += self.out_z.stb.eq(1)
1405
1406
1407 class FPPutZIdx(FPState):
1408
1409 def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1410 FPState.__init__(self, state)
1411 if to_state is None:
1412 to_state = "get_ops"
1413 self.to_state = to_state
1414 self.in_z = in_z
1415 self.out_zs = out_zs
1416 self.in_mid = in_mid
1417
1418 def action(self, m):
1419 outz_stb = Signal(reset_less=True)
1420 outz_ack = Signal(reset_less=True)
1421 m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1422 outz_ack.eq(self.out_zs[self.in_mid].ack),
1423 ]
1424 m.d.sync += [
1425 self.out_zs[self.in_mid].v.eq(self.in_z.v)
1426 ]
1427 with m.If(outz_stb & outz_ack):
1428 m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1429 m.next = self.to_state
1430 with m.Else():
1431 m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1432
1433
1434 class FPADDBaseMod(FPID):
1435
1436 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1437 """ IEEE754 FP Add
1438
1439 * width: bit-width of IEEE754. supported: 16, 32, 64
1440 * id_wid: an identifier that is sync-connected to the input
1441 * single_cycle: True indicates each stage to complete in 1 clock
1442 * compact: True indicates a reduced number of stages
1443 """
1444 FPID.__init__(self, id_wid)
1445 self.width = width
1446 self.single_cycle = single_cycle
1447 self.compact = compact
1448
1449 self.in_t = Trigger()
1450 self.in_a = Signal(width)
1451 self.in_b = Signal(width)
1452 self.out_z = FPOp(width)
1453
1454 self.states = []
1455
1456 def add_state(self, state):
1457 self.states.append(state)
1458 return state
1459
1460 def get_fragment(self, platform=None):
1461 """ creates the HDL code-fragment for FPAdd
1462 """
1463 m = Module()
1464 m.submodules.out_z = self.out_z
1465 m.submodules.in_t = self.in_t
1466 if self.compact:
1467 self.get_compact_fragment(m, platform)
1468 else:
1469 self.get_longer_fragment(m, platform)
1470
1471 with m.FSM() as fsm:
1472
1473 for state in self.states:
1474 with m.State(state.state_from):
1475 state.action(m)
1476
1477 return m
1478
1479 def get_longer_fragment(self, m, platform=None):
1480
1481 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1482 self.in_a, self.in_b, self.width))
1483 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1484 a = get.out_op1
1485 b = get.out_op2
1486
1487 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1488 sc.setup(m, a, b, self.in_mid)
1489
1490 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1491 dn.setup(m, a, b, sc.in_mid)
1492
1493 if self.single_cycle:
1494 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1495 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1496 else:
1497 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1498 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1499
1500 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1501 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1502
1503 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1504 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1505
1506 if self.single_cycle:
1507 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1508 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1509 else:
1510 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1511 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1512
1513 rn = self.add_state(FPRound(self.width, self.id_wid))
1514 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1515
1516 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1517 cor.setup(m, rn.out_z, rn.in_mid)
1518
1519 pa = self.add_state(FPPack(self.width, self.id_wid))
1520 pa.setup(m, cor.out_z, rn.in_mid)
1521
1522 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1523 pa.in_mid, self.out_mid))
1524
1525 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1526 pa.in_mid, self.out_mid))
1527
1528 def get_compact_fragment(self, m, platform=None):
1529
1530 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1531 self.in_a, self.in_b, self.width))
1532 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1533 a = get.out_op1
1534 b = get.out_op2
1535
1536 sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1537 sc.setup(m, a, b, self.in_mid)
1538
1539 alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1540 alm.setup(m, sc.o.a, sc.o.b, sc.in_mid)
1541
1542 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1543 n1.setup(m, alm.out_z, alm.out_of, alm.in_mid)
1544
1545 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
1546 n1.in_mid, self.out_mid))
1547
1548 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1549 sc.in_mid, self.out_mid))
1550
1551
1552 class FPADDBase(FPState, FPID):
1553
1554 def __init__(self, width, id_wid=None, single_cycle=False):
1555 """ IEEE754 FP Add
1556
1557 * width: bit-width of IEEE754. supported: 16, 32, 64
1558 * id_wid: an identifier that is sync-connected to the input
1559 * single_cycle: True indicates each stage to complete in 1 clock
1560 """
1561 FPID.__init__(self, id_wid)
1562 FPState.__init__(self, "fpadd")
1563 self.width = width
1564 self.single_cycle = single_cycle
1565 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1566
1567 self.in_t = Trigger()
1568 self.in_a = Signal(width)
1569 self.in_b = Signal(width)
1570 #self.out_z = FPOp(width)
1571
1572 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1573 self.in_accept = Signal(reset_less=True)
1574 self.add_stb = Signal(reset_less=True)
1575 self.add_ack = Signal(reset=0, reset_less=True)
1576
1577 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1578 self.out_z = out_z
1579 self.out_mid = out_mid
1580 m.d.comb += [self.in_a.eq(a),
1581 self.in_b.eq(b),
1582 self.mod.in_a.eq(self.in_a),
1583 self.mod.in_b.eq(self.in_b),
1584 self.in_mid.eq(in_mid),
1585 self.mod.in_mid.eq(self.in_mid),
1586 self.z_done.eq(self.mod.out_z.trigger),
1587 #self.add_stb.eq(add_stb),
1588 self.mod.in_t.stb.eq(self.in_t.stb),
1589 self.in_t.ack.eq(self.mod.in_t.ack),
1590 self.out_mid.eq(self.mod.out_mid),
1591 self.out_z.v.eq(self.mod.out_z.v),
1592 self.out_z.stb.eq(self.mod.out_z.stb),
1593 self.mod.out_z.ack.eq(self.out_z.ack),
1594 ]
1595
1596 m.d.sync += self.add_stb.eq(add_stb)
1597 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1598 m.d.sync += self.out_z.ack.eq(0) # likewise
1599 #m.d.sync += self.in_t.stb.eq(0)
1600
1601 m.submodules.fpadd = self.mod
1602
1603 def action(self, m):
1604
1605 # in_accept is set on incoming strobe HIGH and ack LOW.
1606 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1607
1608 #with m.If(self.in_t.ack):
1609 # m.d.sync += self.in_t.stb.eq(0)
1610 with m.If(~self.z_done):
1611 # not done: test for accepting an incoming operand pair
1612 with m.If(self.in_accept):
1613 m.d.sync += [
1614 self.add_ack.eq(1), # acknowledge receipt...
1615 self.in_t.stb.eq(1), # initiate add
1616 ]
1617 with m.Else():
1618 m.d.sync += [self.add_ack.eq(0),
1619 self.in_t.stb.eq(0),
1620 self.out_z.ack.eq(1),
1621 ]
1622 with m.Else():
1623 # done: acknowledge, and write out id and value
1624 m.d.sync += [self.add_ack.eq(1),
1625 self.in_t.stb.eq(0)
1626 ]
1627 m.next = "put_z"
1628
1629 return
1630
1631 if self.in_mid is not None:
1632 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1633
1634 m.d.sync += [
1635 self.out_z.v.eq(self.mod.out_z.v)
1636 ]
1637 # move to output state on detecting z ack
1638 with m.If(self.out_z.trigger):
1639 m.d.sync += self.out_z.stb.eq(0)
1640 m.next = "put_z"
1641 with m.Else():
1642 m.d.sync += self.out_z.stb.eq(1)
1643
1644 class ResArray:
1645 def __init__(self, width, id_wid):
1646 self.width = width
1647 self.id_wid = id_wid
1648 res = []
1649 for i in range(rs_sz):
1650 out_z = FPOp(width)
1651 out_z.name = "out_z_%d" % i
1652 res.append(out_z)
1653 self.res = Array(res)
1654 self.in_z = FPOp(width)
1655 self.in_mid = Signal(self.id_wid, reset_less=True)
1656
1657 def setup(self, m, in_z, in_mid):
1658 m.d.comb += [self.in_z.eq(in_z),
1659 self.in_mid.eq(in_mid)]
1660
1661 def get_fragment(self, platform=None):
1662 """ creates the HDL code-fragment for FPAdd
1663 """
1664 m = Module()
1665 m.submodules.res_in_z = self.in_z
1666 m.submodules += self.res
1667
1668 return m
1669
1670 def ports(self):
1671 res = []
1672 for z in self.res:
1673 res += z.ports()
1674 return res
1675
1676
1677 class FPADD(FPID):
1678 """ FPADD: stages as follows:
1679
1680 FPGetOp (a)
1681 |
1682 FPGetOp (b)
1683 |
1684 FPAddBase---> FPAddBaseMod
1685 | |
1686 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1687
1688 FPAddBase is tricky: it is both a stage and *has* stages.
1689 Connection to FPAddBaseMod therefore requires an in stb/ack
1690 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1691 needs to be the thing that raises the incoming stb.
1692 """
1693
1694 def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1695 """ IEEE754 FP Add
1696
1697 * width: bit-width of IEEE754. supported: 16, 32, 64
1698 * id_wid: an identifier that is sync-connected to the input
1699 * single_cycle: True indicates each stage to complete in 1 clock
1700 """
1701 self.width = width
1702 self.id_wid = id_wid
1703 self.single_cycle = single_cycle
1704
1705 #self.out_z = FPOp(width)
1706 self.ids = FPID(id_wid)
1707
1708 rs = []
1709 for i in range(rs_sz):
1710 in_a = FPOp(width)
1711 in_b = FPOp(width)
1712 in_a.name = "in_a_%d" % i
1713 in_b.name = "in_b_%d" % i
1714 rs.append((in_a, in_b))
1715 self.rs = Array(rs)
1716
1717 res = []
1718 for i in range(rs_sz):
1719 out_z = FPOp(width)
1720 out_z.name = "out_z_%d" % i
1721 res.append(out_z)
1722 self.res = Array(res)
1723
1724 self.states = []
1725
1726 def add_state(self, state):
1727 self.states.append(state)
1728 return state
1729
1730 def get_fragment(self, platform=None):
1731 """ creates the HDL code-fragment for FPAdd
1732 """
1733 m = Module()
1734 m.submodules += self.rs
1735
1736 in_a = self.rs[0][0]
1737 in_b = self.rs[0][1]
1738
1739 out_z = FPOp(self.width)
1740 out_mid = Signal(self.id_wid, reset_less=True)
1741 m.submodules.out_z = out_z
1742
1743 geta = self.add_state(FPGetOp("get_a", "get_b",
1744 in_a, self.width))
1745 geta.setup(m, in_a)
1746 a = geta.out_op
1747
1748 getb = self.add_state(FPGetOp("get_b", "fpadd",
1749 in_b, self.width))
1750 getb.setup(m, in_b)
1751 b = getb.out_op
1752
1753 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1754 ab = self.add_state(ab)
1755 ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1756 out_z, out_mid)
1757
1758 pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1759 out_mid, "get_a"))
1760
1761 with m.FSM() as fsm:
1762
1763 for state in self.states:
1764 with m.State(state.state_from):
1765 state.action(m)
1766
1767 return m
1768
1769
1770 if __name__ == "__main__":
1771 if True:
1772 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1773 main(alu, ports=alu.rs[0][0].ports() + \
1774 alu.rs[0][1].ports() + \
1775 alu.res[0].ports() + \
1776 [alu.ids.in_mid, alu.ids.out_mid])
1777 else:
1778 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1779 main(alu, ports=[alu.in_a, alu.in_b] + \
1780 alu.in_t.ports() + \
1781 alu.out_z.ports() + \
1782 [alu.in_mid, alu.out_mid])
1783
1784
1785 # works... but don't use, just do "python fname.py convert -t v"
1786 #print (verilog.convert(alu, ports=[
1787 # ports=alu.in_a.ports() + \
1788 # alu.in_b.ports() + \
1789 # alu.out_z.ports())