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convert FPAddDeNormMod to ospec/ispec
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 #from fpbase import FPNumShiftMultiRight
13
14
15 class FPState(FPBase):
16 def __init__(self, state_from):
17 self.state_from = state_from
18
19 def set_inputs(self, inputs):
20 self.inputs = inputs
21 for k,v in inputs.items():
22 setattr(self, k, v)
23
24 def set_outputs(self, outputs):
25 self.outputs = outputs
26 for k,v in outputs.items():
27 setattr(self, k, v)
28
29
30 class FPGetSyncOpsMod:
31 def __init__(self, width, num_ops=2):
32 self.width = width
33 self.num_ops = num_ops
34 inops = []
35 outops = []
36 for i in range(num_ops):
37 inops.append(Signal(width, reset_less=True))
38 outops.append(Signal(width, reset_less=True))
39 self.in_op = inops
40 self.out_op = outops
41 self.stb = Signal(num_ops)
42 self.ack = Signal()
43 self.ready = Signal(reset_less=True)
44 self.out_decode = Signal(reset_less=True)
45
46 def elaborate(self, platform):
47 m = Module()
48 m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
49 m.d.comb += self.out_decode.eq(self.ack & self.ready)
50 with m.If(self.out_decode):
51 for i in range(self.num_ops):
52 m.d.comb += [
53 self.out_op[i].eq(self.in_op[i]),
54 ]
55 return m
56
57 def ports(self):
58 return self.in_op + self.out_op + [self.stb, self.ack]
59
60
61 class FPOps(Trigger):
62 def __init__(self, width, num_ops):
63 Trigger.__init__(self)
64 self.width = width
65 self.num_ops = num_ops
66
67 res = []
68 for i in range(num_ops):
69 res.append(Signal(width))
70 self.v = Array(res)
71
72 def ports(self):
73 res = []
74 for i in range(self.num_ops):
75 res.append(self.v[i])
76 res.append(self.ack)
77 res.append(self.stb)
78 return res
79
80
81 class InputGroup:
82 def __init__(self, width, num_ops=2, num_rows=4):
83 self.width = width
84 self.num_ops = num_ops
85 self.num_rows = num_rows
86 self.mmax = int(log(self.num_rows) / log(2))
87 self.rs = []
88 self.mid = Signal(self.mmax, reset_less=True) # multiplex id
89 for i in range(num_rows):
90 self.rs.append(FPGetSyncOpsMod(width, num_ops))
91 self.rs = Array(self.rs)
92
93 self.out_op = FPOps(width, num_ops)
94
95 def elaborate(self, platform):
96 m = Module()
97
98 pe = PriorityEncoder(self.num_rows)
99 m.submodules.selector = pe
100 m.submodules.out_op = self.out_op
101 m.submodules += self.rs
102
103 # connect priority encoder
104 in_ready = []
105 for i in range(self.num_rows):
106 in_ready.append(self.rs[i].ready)
107 m.d.comb += pe.i.eq(Cat(*in_ready))
108
109 active = Signal(reset_less=True)
110 out_en = Signal(reset_less=True)
111 m.d.comb += active.eq(~pe.n) # encoder active
112 m.d.comb += out_en.eq(active & self.out_op.trigger)
113
114 # encoder active: ack relevant input, record MID, pass output
115 with m.If(out_en):
116 rs = self.rs[pe.o]
117 m.d.sync += self.mid.eq(pe.o)
118 m.d.sync += rs.ack.eq(0)
119 m.d.sync += self.out_op.stb.eq(0)
120 for j in range(self.num_ops):
121 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
122 with m.Else():
123 m.d.sync += self.out_op.stb.eq(1)
124 # acks all default to zero
125 for i in range(self.num_rows):
126 m.d.sync += self.rs[i].ack.eq(1)
127
128 return m
129
130 def ports(self):
131 res = []
132 for i in range(self.num_rows):
133 inop = self.rs[i]
134 res += inop.in_op + [inop.stb]
135 return self.out_op.ports() + res + [self.mid]
136
137
138 class FPGetOpMod:
139 def __init__(self, width):
140 self.in_op = FPOp(width)
141 self.out_op = Signal(width)
142 self.out_decode = Signal(reset_less=True)
143
144 def elaborate(self, platform):
145 m = Module()
146 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
147 m.submodules.get_op_in = self.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m.If(self.out_decode):
150 m.d.comb += [
151 self.out_op.eq(self.in_op.v),
152 ]
153 return m
154
155
156 class FPGetOp(FPState):
157 """ gets operand
158 """
159
160 def __init__(self, in_state, out_state, in_op, width):
161 FPState.__init__(self, in_state)
162 self.out_state = out_state
163 self.mod = FPGetOpMod(width)
164 self.in_op = in_op
165 self.out_op = Signal(width)
166 self.out_decode = Signal(reset_less=True)
167
168 def setup(self, m, in_op):
169 """ links module to inputs and outputs
170 """
171 setattr(m.submodules, self.state_from, self.mod)
172 m.d.comb += self.mod.in_op.eq(in_op)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m.d.comb += self.out_decode.eq(self.mod.out_decode)
175
176 def action(self, m):
177 with m.If(self.out_decode):
178 m.next = self.out_state
179 m.d.sync += [
180 self.in_op.ack.eq(0),
181 self.out_op.eq(self.mod.out_op)
182 ]
183 with m.Else():
184 m.d.sync += self.in_op.ack.eq(1)
185
186
187 class FPGet2OpMod(Trigger):
188 def __init__(self, width):
189 Trigger.__init__(self)
190 self.in_op1 = Signal(width, reset_less=True)
191 self.in_op2 = Signal(width, reset_less=True)
192 self.out_op1 = FPNumIn(None, width)
193 self.out_op2 = FPNumIn(None, width)
194
195 def elaborate(self, platform):
196 m = Trigger.elaborate(self, platform)
197 #m.submodules.get_op_in = self.in_op
198 m.submodules.get_op1_out = self.out_op1
199 m.submodules.get_op2_out = self.out_op2
200 with m.If(self.trigger):
201 m.d.comb += [
202 self.out_op1.decode(self.in_op1),
203 self.out_op2.decode(self.in_op2),
204 ]
205 return m
206
207
208 class FPGet2Op(FPState):
209 """ gets operands
210 """
211
212 def __init__(self, in_state, out_state, in_op1, in_op2, width):
213 FPState.__init__(self, in_state)
214 self.out_state = out_state
215 self.mod = FPGet2OpMod(width)
216 self.in_op1 = in_op1
217 self.in_op2 = in_op2
218 self.out_op1 = FPNumIn(None, width)
219 self.out_op2 = FPNumIn(None, width)
220 self.in_stb = Signal(reset_less=True)
221 self.out_ack = Signal(reset_less=True)
222 self.out_decode = Signal(reset_less=True)
223
224 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
225 """ links module to inputs and outputs
226 """
227 m.submodules.get_ops = self.mod
228 m.d.comb += self.mod.in_op1.eq(in_op1)
229 m.d.comb += self.mod.in_op2.eq(in_op2)
230 m.d.comb += self.mod.stb.eq(in_stb)
231 m.d.comb += self.out_ack.eq(self.mod.ack)
232 m.d.comb += self.out_decode.eq(self.mod.trigger)
233 m.d.comb += in_ack.eq(self.mod.ack)
234
235 def action(self, m):
236 with m.If(self.out_decode):
237 m.next = self.out_state
238 m.d.sync += [
239 self.mod.ack.eq(0),
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self.out_op1.eq(self.mod.out_op1),
243 self.out_op2.eq(self.mod.out_op2)
244 ]
245 with m.Else():
246 m.d.sync += self.mod.ack.eq(1)
247
248 class FPNumBase2Ops:
249
250 def __init__(self, width, m_extra=True):
251 self.a = FPNumBase(width, m_extra)
252 self.b = FPNumBase(width, m_extra)
253
254 def eq(self, i):
255 return [self.a.eq(i.a), self.a.eq(i.b)]
256
257
258 class FPAddSpecialCasesMod:
259 """ special cases: NaNs, infs, zeros, denormalised
260 NOTE: some of these are unique to add. see "Special Operations"
261 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
262 """
263
264 def __init__(self, width):
265 self.width = width
266 self.i = self.ispec()
267 self.out_z = self.ospec()
268 self.out_do_z = Signal(reset_less=True)
269
270 def ispec(self):
271 return FPNumBase2Ops(self.width)
272
273 def ospec(self):
274 return FPNumOut(self.width, False)
275
276 def setup(self, m, in_a, in_b, out_do_z):
277 """ links module to inputs and outputs
278 """
279 m.submodules.specialcases = self
280 m.d.comb += self.i.a.eq(in_a)
281 m.d.comb += self.i.b.eq(in_b)
282 m.d.comb += out_do_z.eq(self.out_do_z)
283
284 def elaborate(self, platform):
285 m = Module()
286
287 m.submodules.sc_in_a = self.i.a
288 m.submodules.sc_in_b = self.i.b
289 m.submodules.sc_out_z = self.out_z
290
291 s_nomatch = Signal()
292 m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
293
294 m_match = Signal()
295 m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
296
297 # if a is NaN or b is NaN return NaN
298 with m.If(self.i.a.is_nan | self.i.b.is_nan):
299 m.d.comb += self.out_do_z.eq(1)
300 m.d.comb += self.out_z.nan(0)
301
302 # XXX WEIRDNESS for FP16 non-canonical NaN handling
303 # under review
304
305 ## if a is zero and b is NaN return -b
306 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
307 # m.d.comb += self.out_do_z.eq(1)
308 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
309
310 ## if b is zero and a is NaN return -a
311 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
312 # m.d.comb += self.out_do_z.eq(1)
313 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
314
315 ## if a is -zero and b is NaN return -b
316 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
317 # m.d.comb += self.out_do_z.eq(1)
318 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
319
320 ## if b is -zero and a is NaN return -a
321 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
322 # m.d.comb += self.out_do_z.eq(1)
323 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
324
325 # if a is inf return inf (or NaN)
326 with m.Elif(self.i.a.is_inf):
327 m.d.comb += self.out_do_z.eq(1)
328 m.d.comb += self.out_z.inf(self.i.a.s)
329 # if a is inf and signs don't match return NaN
330 with m.If(self.i.b.exp_128 & s_nomatch):
331 m.d.comb += self.out_z.nan(0)
332
333 # if b is inf return inf
334 with m.Elif(self.i.b.is_inf):
335 m.d.comb += self.out_do_z.eq(1)
336 m.d.comb += self.out_z.inf(self.i.b.s)
337
338 # if a is zero and b zero return signed-a/b
339 with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
340 m.d.comb += self.out_do_z.eq(1)
341 m.d.comb += self.out_z.create(self.i.a.s & self.i.b.s,
342 self.i.b.e,
343 self.i.b.m[3:-1])
344
345 # if a is zero return b
346 with m.Elif(self.i.a.is_zero):
347 m.d.comb += self.out_do_z.eq(1)
348 m.d.comb += self.out_z.create(self.i.b.s, self.i.b.e,
349 self.i.b.m[3:-1])
350
351 # if b is zero return a
352 with m.Elif(self.i.b.is_zero):
353 m.d.comb += self.out_do_z.eq(1)
354 m.d.comb += self.out_z.create(self.i.a.s, self.i.a.e,
355 self.i.a.m[3:-1])
356
357 # if a equal to -b return zero (+ve zero)
358 with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
359 m.d.comb += self.out_do_z.eq(1)
360 m.d.comb += self.out_z.zero(0)
361
362 # Denormalised Number checks
363 with m.Else():
364 m.d.comb += self.out_do_z.eq(0)
365
366 return m
367
368
369 class FPID:
370 def __init__(self, id_wid):
371 self.id_wid = id_wid
372 if self.id_wid:
373 self.in_mid = Signal(id_wid, reset_less=True)
374 self.out_mid = Signal(id_wid, reset_less=True)
375 else:
376 self.in_mid = None
377 self.out_mid = None
378
379 def idsync(self, m):
380 if self.id_wid is not None:
381 m.d.sync += self.out_mid.eq(self.in_mid)
382
383
384 class FPAddSpecialCases(FPState, FPID):
385 """ special cases: NaNs, infs, zeros, denormalised
386 NOTE: some of these are unique to add. see "Special Operations"
387 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
388 """
389
390 def __init__(self, width, id_wid):
391 FPState.__init__(self, "special_cases")
392 FPID.__init__(self, id_wid)
393 self.mod = FPAddSpecialCasesMod(width)
394 self.out_z = self.mod.ospec()
395 self.out_do_z = Signal(reset_less=True)
396
397 def setup(self, m, in_a, in_b, in_mid):
398 """ links module to inputs and outputs
399 """
400 self.mod.setup(m, in_a, in_b, self.out_do_z)
401 if self.in_mid is not None:
402 m.d.comb += self.in_mid.eq(in_mid)
403
404 def action(self, m):
405 self.idsync(m)
406 with m.If(self.out_do_z):
407 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
408 m.next = "put_z"
409 with m.Else():
410 m.next = "denormalise"
411
412
413 class FPAddSpecialCasesDeNorm(FPState, FPID):
414 """ special cases: NaNs, infs, zeros, denormalised
415 NOTE: some of these are unique to add. see "Special Operations"
416 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
417 """
418
419 def __init__(self, width, id_wid):
420 FPState.__init__(self, "special_cases")
421 FPID.__init__(self, id_wid)
422 self.smod = FPAddSpecialCasesMod(width)
423 self.out_z = self.smod.ospec()
424 self.out_do_z = Signal(reset_less=True)
425
426 self.dmod = FPAddDeNormMod(width)
427 self.out_a = FPNumBase(width)
428 self.out_b = FPNumBase(width)
429
430 def setup(self, m, in_a, in_b, in_mid):
431 """ links module to inputs and outputs
432 """
433 self.smod.setup(m, in_a, in_b, self.out_do_z)
434 self.dmod.setup(m, in_a, in_b)
435 if self.in_mid is not None:
436 m.d.comb += self.in_mid.eq(in_mid)
437
438 def action(self, m):
439 self.idsync(m)
440 with m.If(self.out_do_z):
441 m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
442 m.next = "put_z"
443 with m.Else():
444 m.next = "align"
445 m.d.sync += self.out_a.eq(self.dmod.o.a)
446 m.d.sync += self.out_b.eq(self.dmod.o.b)
447
448
449 class FPAddDeNormMod(FPState):
450
451 def __init__(self, width):
452 self.width = width
453 self.i = self.ispec()
454 self.o = self.ospec()
455
456 def ispec(self):
457 return FPNumBase2Ops(self.width)
458
459 def ospec(self):
460 return FPNumBase2Ops(self.width)
461
462 def setup(self, m, in_a, in_b):
463 """ links module to inputs and outputs
464 """
465 m.submodules.denormalise = self
466 m.d.comb += self.i.a.eq(in_a)
467 m.d.comb += self.i.b.eq(in_b)
468
469 def elaborate(self, platform):
470 m = Module()
471 m.submodules.denorm_in_a = self.i.a
472 m.submodules.denorm_in_b = self.i.b
473 m.submodules.denorm_out_a = self.o.a
474 m.submodules.denorm_out_b = self.o.b
475 # hmmm, don't like repeating identical code
476 m.d.comb += self.o.a.eq(self.i.a)
477 with m.If(self.i.a.exp_n127):
478 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
479 with m.Else():
480 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
481
482 m.d.comb += self.o.b.eq(self.i.b)
483 with m.If(self.i.b.exp_n127):
484 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
485 with m.Else():
486 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
487
488 return m
489
490
491 class FPAddDeNorm(FPState, FPID):
492
493 def __init__(self, width, id_wid):
494 FPState.__init__(self, "denormalise")
495 FPID.__init__(self, id_wid)
496 self.mod = FPAddDeNormMod(width)
497 self.out_a = FPNumBase(width)
498 self.out_b = FPNumBase(width)
499
500 def setup(self, m, in_a, in_b, in_mid):
501 """ links module to inputs and outputs
502 """
503 self.mod.setup(m, in_a, in_b)
504 if self.in_mid is not None:
505 m.d.comb += self.in_mid.eq(in_mid)
506
507 def action(self, m):
508 self.idsync(m)
509 # Denormalised Number checks
510 m.next = "align"
511 m.d.sync += self.out_a.eq(self.mod.out_a)
512 m.d.sync += self.out_b.eq(self.mod.out_b)
513
514
515 class FPAddAlignMultiMod(FPState):
516
517 def __init__(self, width):
518 self.in_a = FPNumBase(width)
519 self.in_b = FPNumBase(width)
520 self.out_a = FPNumIn(None, width)
521 self.out_b = FPNumIn(None, width)
522 self.exp_eq = Signal(reset_less=True)
523
524 def elaborate(self, platform):
525 # This one however (single-cycle) will do the shift
526 # in one go.
527
528 m = Module()
529
530 m.submodules.align_in_a = self.in_a
531 m.submodules.align_in_b = self.in_b
532 m.submodules.align_out_a = self.out_a
533 m.submodules.align_out_b = self.out_b
534
535 # NOTE: this does *not* do single-cycle multi-shifting,
536 # it *STAYS* in the align state until exponents match
537
538 # exponent of a greater than b: shift b down
539 m.d.comb += self.exp_eq.eq(0)
540 m.d.comb += self.out_a.eq(self.in_a)
541 m.d.comb += self.out_b.eq(self.in_b)
542 agtb = Signal(reset_less=True)
543 altb = Signal(reset_less=True)
544 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
545 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
546 with m.If(agtb):
547 m.d.comb += self.out_b.shift_down(self.in_b)
548 # exponent of b greater than a: shift a down
549 with m.Elif(altb):
550 m.d.comb += self.out_a.shift_down(self.in_a)
551 # exponents equal: move to next stage.
552 with m.Else():
553 m.d.comb += self.exp_eq.eq(1)
554 return m
555
556
557 class FPAddAlignMulti(FPState, FPID):
558
559 def __init__(self, width, id_wid):
560 FPID.__init__(self, id_wid)
561 FPState.__init__(self, "align")
562 self.mod = FPAddAlignMultiMod(width)
563 self.out_a = FPNumIn(None, width)
564 self.out_b = FPNumIn(None, width)
565 self.exp_eq = Signal(reset_less=True)
566
567 def setup(self, m, in_a, in_b, in_mid):
568 """ links module to inputs and outputs
569 """
570 m.submodules.align = self.mod
571 m.d.comb += self.mod.in_a.eq(in_a)
572 m.d.comb += self.mod.in_b.eq(in_b)
573 #m.d.comb += self.out_a.eq(self.mod.out_a)
574 #m.d.comb += self.out_b.eq(self.mod.out_b)
575 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
576 if self.in_mid is not None:
577 m.d.comb += self.in_mid.eq(in_mid)
578
579 def action(self, m):
580 self.idsync(m)
581 m.d.sync += self.out_a.eq(self.mod.out_a)
582 m.d.sync += self.out_b.eq(self.mod.out_b)
583 with m.If(self.exp_eq):
584 m.next = "add_0"
585
586
587 class FPAddAlignSingleMod:
588
589 def __init__(self, width):
590 self.width = width
591 self.in_a = FPNumBase(width)
592 self.in_b = FPNumBase(width)
593 self.out_a = FPNumIn(None, width)
594 self.out_b = FPNumIn(None, width)
595
596 def setup(self, m, in_a, in_b):
597 """ links module to inputs and outputs
598 """
599 m.submodules.align = self
600 m.d.comb += self.in_a.eq(in_a)
601 m.d.comb += self.in_b.eq(in_b)
602
603 def elaborate(self, platform):
604 """ Aligns A against B or B against A, depending on which has the
605 greater exponent. This is done in a *single* cycle using
606 variable-width bit-shift
607
608 the shifter used here is quite expensive in terms of gates.
609 Mux A or B in (and out) into temporaries, as only one of them
610 needs to be aligned against the other
611 """
612 m = Module()
613
614 m.submodules.align_in_a = self.in_a
615 m.submodules.align_in_b = self.in_b
616 m.submodules.align_out_a = self.out_a
617 m.submodules.align_out_b = self.out_b
618
619 # temporary (muxed) input and output to be shifted
620 t_inp = FPNumBase(self.width)
621 t_out = FPNumIn(None, self.width)
622 espec = (len(self.in_a.e), True)
623 msr = MultiShiftRMerge(self.in_a.m_width, espec)
624 m.submodules.align_t_in = t_inp
625 m.submodules.align_t_out = t_out
626 m.submodules.multishift_r = msr
627
628 ediff = Signal(espec, reset_less=True)
629 ediffr = Signal(espec, reset_less=True)
630 tdiff = Signal(espec, reset_less=True)
631 elz = Signal(reset_less=True)
632 egz = Signal(reset_less=True)
633
634 # connect multi-shifter to t_inp/out mantissa (and tdiff)
635 m.d.comb += msr.inp.eq(t_inp.m)
636 m.d.comb += msr.diff.eq(tdiff)
637 m.d.comb += t_out.m.eq(msr.m)
638 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
639 m.d.comb += t_out.s.eq(t_inp.s)
640
641 m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
642 m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
643 m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
644 m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
645
646 # default: A-exp == B-exp, A and B untouched (fall through)
647 m.d.comb += self.out_a.eq(self.in_a)
648 m.d.comb += self.out_b.eq(self.in_b)
649 # only one shifter (muxed)
650 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
651 # exponent of a greater than b: shift b down
652 with m.If(egz):
653 m.d.comb += [t_inp.eq(self.in_b),
654 tdiff.eq(ediff),
655 self.out_b.eq(t_out),
656 self.out_b.s.eq(self.in_b.s), # whoops forgot sign
657 ]
658 # exponent of b greater than a: shift a down
659 with m.Elif(elz):
660 m.d.comb += [t_inp.eq(self.in_a),
661 tdiff.eq(ediffr),
662 self.out_a.eq(t_out),
663 self.out_a.s.eq(self.in_a.s), # whoops forgot sign
664 ]
665 return m
666
667
668 class FPAddAlignSingle(FPState, FPID):
669
670 def __init__(self, width, id_wid):
671 FPState.__init__(self, "align")
672 FPID.__init__(self, id_wid)
673 self.mod = FPAddAlignSingleMod(width)
674 self.out_a = FPNumIn(None, width)
675 self.out_b = FPNumIn(None, width)
676
677 def setup(self, m, in_a, in_b, in_mid):
678 """ links module to inputs and outputs
679 """
680 self.mod.setup(m, in_a, in_b)
681 if self.in_mid is not None:
682 m.d.comb += self.in_mid.eq(in_mid)
683
684 def action(self, m):
685 self.idsync(m)
686 # NOTE: could be done as comb
687 m.d.sync += self.out_a.eq(self.mod.out_a)
688 m.d.sync += self.out_b.eq(self.mod.out_b)
689 m.next = "add_0"
690
691
692 class FPAddAlignSingleAdd(FPState, FPID):
693
694 def __init__(self, width, id_wid):
695 FPState.__init__(self, "align")
696 FPID.__init__(self, id_wid)
697 self.mod = FPAddAlignSingleMod(width)
698 self.out_a = FPNumIn(None, width)
699 self.out_b = FPNumIn(None, width)
700
701 self.a0mod = FPAddStage0Mod(width)
702 self.a0_out_z = FPNumBase(width, False)
703 self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
704 self.a0_out_z = FPNumBase(width, False)
705
706 self.a1mod = FPAddStage1Mod(width)
707 self.out_z = FPNumBase(width, False)
708 self.out_of = Overflow()
709
710 def setup(self, m, in_a, in_b, in_mid):
711 """ links module to inputs and outputs
712 """
713 self.mod.setup(m, in_a, in_b)
714 m.d.comb += self.out_a.eq(self.mod.out_a)
715 m.d.comb += self.out_b.eq(self.mod.out_b)
716
717 self.a0mod.setup(m, self.out_a, self.out_b)
718 m.d.comb += self.a0_out_z.eq(self.a0mod.out_z)
719 m.d.comb += self.out_tot.eq(self.a0mod.out_tot)
720
721 self.a1mod.setup(m, self.out_tot, self.a0_out_z)
722
723 if self.in_mid is not None:
724 m.d.comb += self.in_mid.eq(in_mid)
725
726 def action(self, m):
727 self.idsync(m)
728 m.d.sync += self.out_of.eq(self.a1mod.out_of)
729 m.d.sync += self.out_z.eq(self.a1mod.out_z)
730 m.next = "normalise_1"
731
732
733 class FPAddStage0Mod:
734
735 def __init__(self, width):
736 self.in_a = FPNumBase(width)
737 self.in_b = FPNumBase(width)
738 self.in_z = FPNumBase(width, False)
739 self.out_z = FPNumBase(width, False)
740 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
741
742 def setup(self, m, in_a, in_b):
743 """ links module to inputs and outputs
744 """
745 m.submodules.add0 = self
746 m.d.comb += self.in_a.eq(in_a)
747 m.d.comb += self.in_b.eq(in_b)
748
749 def elaborate(self, platform):
750 m = Module()
751 m.submodules.add0_in_a = self.in_a
752 m.submodules.add0_in_b = self.in_b
753 m.submodules.add0_out_z = self.out_z
754
755 m.d.comb += self.out_z.e.eq(self.in_a.e)
756
757 # store intermediate tests (and zero-extended mantissas)
758 seq = Signal(reset_less=True)
759 mge = Signal(reset_less=True)
760 am0 = Signal(len(self.in_a.m)+1, reset_less=True)
761 bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
762 m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
763 mge.eq(self.in_a.m >= self.in_b.m),
764 am0.eq(Cat(self.in_a.m, 0)),
765 bm0.eq(Cat(self.in_b.m, 0))
766 ]
767 # same-sign (both negative or both positive) add mantissas
768 with m.If(seq):
769 m.d.comb += [
770 self.out_tot.eq(am0 + bm0),
771 self.out_z.s.eq(self.in_a.s)
772 ]
773 # a mantissa greater than b, use a
774 with m.Elif(mge):
775 m.d.comb += [
776 self.out_tot.eq(am0 - bm0),
777 self.out_z.s.eq(self.in_a.s)
778 ]
779 # b mantissa greater than a, use b
780 with m.Else():
781 m.d.comb += [
782 self.out_tot.eq(bm0 - am0),
783 self.out_z.s.eq(self.in_b.s)
784 ]
785 return m
786
787
788 class FPAddStage0(FPState, FPID):
789 """ First stage of add. covers same-sign (add) and subtract
790 special-casing when mantissas are greater or equal, to
791 give greatest accuracy.
792 """
793
794 def __init__(self, width, id_wid):
795 FPState.__init__(self, "add_0")
796 FPID.__init__(self, id_wid)
797 self.mod = FPAddStage0Mod(width)
798 self.out_z = FPNumBase(width, False)
799 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
800
801 def setup(self, m, in_a, in_b, in_mid):
802 """ links module to inputs and outputs
803 """
804 self.mod.setup(m, in_a, in_b)
805 if self.in_mid is not None:
806 m.d.comb += self.in_mid.eq(in_mid)
807
808 def action(self, m):
809 self.idsync(m)
810 # NOTE: these could be done as combinatorial (merge add0+add1)
811 m.d.sync += self.out_z.eq(self.mod.out_z)
812 m.d.sync += self.out_tot.eq(self.mod.out_tot)
813 m.next = "add_1"
814
815
816 class FPAddStage1Mod(FPState):
817 """ Second stage of add: preparation for normalisation.
818 detects when tot sum is too big (tot[27] is kinda a carry bit)
819 """
820
821 def __init__(self, width):
822 self.out_norm = Signal(reset_less=True)
823 self.in_z = FPNumBase(width, False)
824 self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
825 self.out_z = FPNumBase(width, False)
826 self.out_of = Overflow()
827
828 def setup(self, m, in_tot, in_z):
829 """ links module to inputs and outputs
830 """
831 m.submodules.add1 = self
832 m.submodules.add1_out_overflow = self.out_of
833
834 m.d.comb += self.in_z.eq(in_z)
835 m.d.comb += self.in_tot.eq(in_tot)
836
837 def elaborate(self, platform):
838 m = Module()
839 #m.submodules.norm1_in_overflow = self.in_of
840 #m.submodules.norm1_out_overflow = self.out_of
841 #m.submodules.norm1_in_z = self.in_z
842 #m.submodules.norm1_out_z = self.out_z
843 m.d.comb += self.out_z.eq(self.in_z)
844 # tot[-1] (MSB) gets set when the sum overflows. shift result down
845 with m.If(self.in_tot[-1]):
846 m.d.comb += [
847 self.out_z.m.eq(self.in_tot[4:]),
848 self.out_of.m0.eq(self.in_tot[4]),
849 self.out_of.guard.eq(self.in_tot[3]),
850 self.out_of.round_bit.eq(self.in_tot[2]),
851 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
852 self.out_z.e.eq(self.in_z.e + 1)
853 ]
854 # tot[-1] (MSB) zero case
855 with m.Else():
856 m.d.comb += [
857 self.out_z.m.eq(self.in_tot[3:]),
858 self.out_of.m0.eq(self.in_tot[3]),
859 self.out_of.guard.eq(self.in_tot[2]),
860 self.out_of.round_bit.eq(self.in_tot[1]),
861 self.out_of.sticky.eq(self.in_tot[0])
862 ]
863 return m
864
865
866 class FPAddStage1(FPState, FPID):
867
868 def __init__(self, width, id_wid):
869 FPState.__init__(self, "add_1")
870 FPID.__init__(self, id_wid)
871 self.mod = FPAddStage1Mod(width)
872 self.out_z = FPNumBase(width, False)
873 self.out_of = Overflow()
874 self.norm_stb = Signal()
875
876 def setup(self, m, in_tot, in_z, in_mid):
877 """ links module to inputs and outputs
878 """
879 self.mod.setup(m, in_tot, in_z)
880
881 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
882
883 if self.in_mid is not None:
884 m.d.comb += self.in_mid.eq(in_mid)
885
886 def action(self, m):
887 self.idsync(m)
888 m.d.sync += self.out_of.eq(self.mod.out_of)
889 m.d.sync += self.out_z.eq(self.mod.out_z)
890 m.d.sync += self.norm_stb.eq(1)
891 m.next = "normalise_1"
892
893
894 class FPNormaliseModSingle:
895
896 def __init__(self, width):
897 self.width = width
898 self.in_z = FPNumBase(width, False)
899 self.out_z = FPNumBase(width, False)
900
901 def setup(self, m, in_z, out_z, modname):
902 """ links module to inputs and outputs
903 """
904 m.submodules.normalise = self
905 m.d.comb += self.in_z.eq(in_z)
906 m.d.comb += out_z.eq(self.out_z)
907
908 def elaborate(self, platform):
909 m = Module()
910
911 mwid = self.out_z.m_width+2
912 pe = PriorityEncoder(mwid)
913 m.submodules.norm_pe = pe
914
915 m.submodules.norm1_out_z = self.out_z
916 m.submodules.norm1_in_z = self.in_z
917
918 in_z = FPNumBase(self.width, False)
919 in_of = Overflow()
920 m.submodules.norm1_insel_z = in_z
921 m.submodules.norm1_insel_overflow = in_of
922
923 espec = (len(in_z.e), True)
924 ediff_n126 = Signal(espec, reset_less=True)
925 msr = MultiShiftRMerge(mwid, espec)
926 m.submodules.multishift_r = msr
927
928 m.d.comb += in_z.eq(self.in_z)
929 m.d.comb += in_of.eq(self.in_of)
930 # initialise out from in (overridden below)
931 m.d.comb += self.out_z.eq(in_z)
932 m.d.comb += self.out_of.eq(in_of)
933 # normalisation increase/decrease conditions
934 decrease = Signal(reset_less=True)
935 m.d.comb += decrease.eq(in_z.m_msbzero)
936 # decrease exponent
937 with m.If(decrease):
938 # *sigh* not entirely obvious: count leading zeros (clz)
939 # with a PriorityEncoder: to find from the MSB
940 # we reverse the order of the bits.
941 temp_m = Signal(mwid, reset_less=True)
942 temp_s = Signal(mwid+1, reset_less=True)
943 clz = Signal((len(in_z.e), True), reset_less=True)
944 m.d.comb += [
945 # cat round and guard bits back into the mantissa
946 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
947 pe.i.eq(temp_m[::-1]), # inverted
948 clz.eq(pe.o), # count zeros from MSB down
949 temp_s.eq(temp_m << clz), # shift mantissa UP
950 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
951 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
952 ]
953
954 return m
955
956
957 class FPNorm1ModSingle:
958
959 def __init__(self, width):
960 self.width = width
961 self.out_norm = Signal(reset_less=True)
962 self.in_z = FPNumBase(width, False)
963 self.in_of = Overflow()
964 self.out_z = FPNumBase(width, False)
965 self.out_of = Overflow()
966
967 def setup(self, m, in_z, in_of, out_z):
968 """ links module to inputs and outputs
969 """
970 m.submodules.normalise_1 = self
971
972 m.d.comb += self.in_z.eq(in_z)
973 m.d.comb += self.in_of.eq(in_of)
974
975 m.d.comb += out_z.eq(self.out_z)
976
977 def elaborate(self, platform):
978 m = Module()
979
980 mwid = self.out_z.m_width+2
981 pe = PriorityEncoder(mwid)
982 m.submodules.norm_pe = pe
983
984 m.submodules.norm1_out_z = self.out_z
985 m.submodules.norm1_out_overflow = self.out_of
986 m.submodules.norm1_in_z = self.in_z
987 m.submodules.norm1_in_overflow = self.in_of
988
989 in_z = FPNumBase(self.width, False)
990 in_of = Overflow()
991 m.submodules.norm1_insel_z = in_z
992 m.submodules.norm1_insel_overflow = in_of
993
994 espec = (len(in_z.e), True)
995 ediff_n126 = Signal(espec, reset_less=True)
996 msr = MultiShiftRMerge(mwid, espec)
997 m.submodules.multishift_r = msr
998
999 m.d.comb += in_z.eq(self.in_z)
1000 m.d.comb += in_of.eq(self.in_of)
1001 # initialise out from in (overridden below)
1002 m.d.comb += self.out_z.eq(in_z)
1003 m.d.comb += self.out_of.eq(in_of)
1004 # normalisation increase/decrease conditions
1005 decrease = Signal(reset_less=True)
1006 increase = Signal(reset_less=True)
1007 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1008 m.d.comb += increase.eq(in_z.exp_lt_n126)
1009 # decrease exponent
1010 with m.If(decrease):
1011 # *sigh* not entirely obvious: count leading zeros (clz)
1012 # with a PriorityEncoder: to find from the MSB
1013 # we reverse the order of the bits.
1014 temp_m = Signal(mwid, reset_less=True)
1015 temp_s = Signal(mwid+1, reset_less=True)
1016 clz = Signal((len(in_z.e), True), reset_less=True)
1017 # make sure that the amount to decrease by does NOT
1018 # go below the minimum non-INF/NaN exponent
1019 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
1020 in_z.exp_sub_n126)
1021 m.d.comb += [
1022 # cat round and guard bits back into the mantissa
1023 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1024 pe.i.eq(temp_m[::-1]), # inverted
1025 clz.eq(limclz), # count zeros from MSB down
1026 temp_s.eq(temp_m << clz), # shift mantissa UP
1027 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
1028 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
1029 self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
1030 # overflow in bits 0..1: got shifted too (leave sticky)
1031 self.out_of.guard.eq(temp_s[1]), # guard
1032 self.out_of.round_bit.eq(temp_s[0]), # round
1033 ]
1034 # increase exponent
1035 with m.Elif(increase):
1036 temp_m = Signal(mwid+1, reset_less=True)
1037 m.d.comb += [
1038 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
1039 in_z.m)),
1040 ediff_n126.eq(in_z.N126 - in_z.e),
1041 # connect multi-shifter to inp/out mantissa (and ediff)
1042 msr.inp.eq(temp_m),
1043 msr.diff.eq(ediff_n126),
1044 self.out_z.m.eq(msr.m[3:]),
1045 self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
1046 # overflow in bits 0..1: got shifted too (leave sticky)
1047 self.out_of.guard.eq(temp_s[2]), # guard
1048 self.out_of.round_bit.eq(temp_s[1]), # round
1049 self.out_of.sticky.eq(temp_s[0]), # sticky
1050 self.out_z.e.eq(in_z.e + ediff_n126),
1051 ]
1052
1053 return m
1054
1055
1056 class FPNorm1ModMulti:
1057
1058 def __init__(self, width, single_cycle=True):
1059 self.width = width
1060 self.in_select = Signal(reset_less=True)
1061 self.out_norm = Signal(reset_less=True)
1062 self.in_z = FPNumBase(width, False)
1063 self.in_of = Overflow()
1064 self.temp_z = FPNumBase(width, False)
1065 self.temp_of = Overflow()
1066 self.out_z = FPNumBase(width, False)
1067 self.out_of = Overflow()
1068
1069 def elaborate(self, platform):
1070 m = Module()
1071
1072 m.submodules.norm1_out_z = self.out_z
1073 m.submodules.norm1_out_overflow = self.out_of
1074 m.submodules.norm1_temp_z = self.temp_z
1075 m.submodules.norm1_temp_of = self.temp_of
1076 m.submodules.norm1_in_z = self.in_z
1077 m.submodules.norm1_in_overflow = self.in_of
1078
1079 in_z = FPNumBase(self.width, False)
1080 in_of = Overflow()
1081 m.submodules.norm1_insel_z = in_z
1082 m.submodules.norm1_insel_overflow = in_of
1083
1084 # select which of temp or in z/of to use
1085 with m.If(self.in_select):
1086 m.d.comb += in_z.eq(self.in_z)
1087 m.d.comb += in_of.eq(self.in_of)
1088 with m.Else():
1089 m.d.comb += in_z.eq(self.temp_z)
1090 m.d.comb += in_of.eq(self.temp_of)
1091 # initialise out from in (overridden below)
1092 m.d.comb += self.out_z.eq(in_z)
1093 m.d.comb += self.out_of.eq(in_of)
1094 # normalisation increase/decrease conditions
1095 decrease = Signal(reset_less=True)
1096 increase = Signal(reset_less=True)
1097 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1098 m.d.comb += increase.eq(in_z.exp_lt_n126)
1099 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1100 # decrease exponent
1101 with m.If(decrease):
1102 m.d.comb += [
1103 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
1104 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1105 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1106 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1107 self.out_of.round_bit.eq(0), # reset round bit
1108 self.out_of.m0.eq(in_of.guard),
1109 ]
1110 # increase exponent
1111 with m.Elif(increase):
1112 m.d.comb += [
1113 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
1114 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1115 self.out_of.guard.eq(in_z.m[0]),
1116 self.out_of.m0.eq(in_z.m[1]),
1117 self.out_of.round_bit.eq(in_of.guard),
1118 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1119 ]
1120
1121 return m
1122
1123
1124 class FPNorm1Single(FPState, FPID):
1125
1126 def __init__(self, width, id_wid, single_cycle=True):
1127 FPID.__init__(self, id_wid)
1128 FPState.__init__(self, "normalise_1")
1129 self.mod = FPNorm1ModSingle(width)
1130 self.out_norm = Signal(reset_less=True)
1131 self.out_z = FPNumBase(width)
1132 self.out_roundz = Signal(reset_less=True)
1133
1134 def setup(self, m, in_z, in_of, in_mid):
1135 """ links module to inputs and outputs
1136 """
1137 self.mod.setup(m, in_z, in_of, self.out_z)
1138
1139 if self.in_mid is not None:
1140 m.d.comb += self.in_mid.eq(in_mid)
1141
1142 def action(self, m):
1143 self.idsync(m)
1144 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1145 m.next = "round"
1146
1147
1148 class FPNorm1Multi(FPState, FPID):
1149
1150 def __init__(self, width, id_wid):
1151 FPID.__init__(self, id_wid)
1152 FPState.__init__(self, "normalise_1")
1153 self.mod = FPNorm1ModMulti(width)
1154 self.stb = Signal(reset_less=True)
1155 self.ack = Signal(reset=0, reset_less=True)
1156 self.out_norm = Signal(reset_less=True)
1157 self.in_accept = Signal(reset_less=True)
1158 self.temp_z = FPNumBase(width)
1159 self.temp_of = Overflow()
1160 self.out_z = FPNumBase(width)
1161 self.out_roundz = Signal(reset_less=True)
1162
1163 def setup(self, m, in_z, in_of, norm_stb, in_mid):
1164 """ links module to inputs and outputs
1165 """
1166 self.mod.setup(m, in_z, in_of, norm_stb,
1167 self.in_accept, self.temp_z, self.temp_of,
1168 self.out_z, self.out_norm)
1169
1170 m.d.comb += self.stb.eq(norm_stb)
1171 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1172
1173 if self.in_mid is not None:
1174 m.d.comb += self.in_mid.eq(in_mid)
1175
1176 def action(self, m):
1177 self.idsync(m)
1178 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1179 m.d.sync += self.temp_of.eq(self.mod.out_of)
1180 m.d.sync += self.temp_z.eq(self.out_z)
1181 with m.If(self.out_norm):
1182 with m.If(self.in_accept):
1183 m.d.sync += [
1184 self.ack.eq(1),
1185 ]
1186 with m.Else():
1187 m.d.sync += self.ack.eq(0)
1188 with m.Else():
1189 # normalisation not required (or done).
1190 m.next = "round"
1191 m.d.sync += self.ack.eq(1)
1192 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1193
1194
1195 class FPNormToPack(FPState, FPID):
1196
1197 def __init__(self, width, id_wid):
1198 FPID.__init__(self, id_wid)
1199 FPState.__init__(self, "normalise_1")
1200 self.width = width
1201
1202 def setup(self, m, in_z, in_of, in_mid):
1203 """ links module to inputs and outputs
1204 """
1205
1206 # Normalisation (chained to input in_z+in_of)
1207 nmod = FPNorm1ModSingle(self.width)
1208 n_out_z = FPNumBase(self.width)
1209 n_out_roundz = Signal(reset_less=True)
1210 nmod.setup(m, in_z, in_of, n_out_z)
1211
1212 # Rounding (chained to normalisation)
1213 rmod = FPRoundMod(self.width)
1214 r_out_z = FPNumBase(self.width)
1215 rmod.setup(m, n_out_z, n_out_roundz)
1216 m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
1217 m.d.comb += r_out_z.eq(rmod.out_z)
1218
1219 # Corrections (chained to rounding)
1220 cmod = FPCorrectionsMod(self.width)
1221 c_out_z = FPNumBase(self.width)
1222 cmod.setup(m, r_out_z)
1223 m.d.comb += c_out_z.eq(cmod.out_z)
1224
1225 # Pack (chained to corrections)
1226 self.pmod = FPPackMod(self.width)
1227 self.out_z = FPNumBase(self.width)
1228 self.pmod.setup(m, c_out_z)
1229
1230 # Multiplex ID
1231 if self.in_mid is not None:
1232 m.d.comb += self.in_mid.eq(in_mid)
1233
1234 def action(self, m):
1235 self.idsync(m) # copies incoming ID to outgoing
1236 m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
1237 m.next = "pack_put_z"
1238
1239
1240 class FPRoundMod:
1241
1242 def __init__(self, width):
1243 self.in_roundz = Signal(reset_less=True)
1244 self.in_z = FPNumBase(width, False)
1245 self.out_z = FPNumBase(width, False)
1246
1247 def setup(self, m, in_z, roundz):
1248 m.submodules.roundz = self
1249
1250 m.d.comb += self.in_z.eq(in_z)
1251 m.d.comb += self.in_roundz.eq(roundz)
1252
1253 def elaborate(self, platform):
1254 m = Module()
1255 m.d.comb += self.out_z.eq(self.in_z)
1256 with m.If(self.in_roundz):
1257 m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
1258 with m.If(self.in_z.m == self.in_z.m1s): # all 1s
1259 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
1260 return m
1261
1262
1263 class FPRound(FPState, FPID):
1264
1265 def __init__(self, width, id_wid):
1266 FPState.__init__(self, "round")
1267 FPID.__init__(self, id_wid)
1268 self.mod = FPRoundMod(width)
1269 self.out_z = FPNumBase(width)
1270
1271 def setup(self, m, in_z, roundz, in_mid):
1272 """ links module to inputs and outputs
1273 """
1274 self.mod.setup(m, in_z, roundz)
1275
1276 if self.in_mid is not None:
1277 m.d.comb += self.in_mid.eq(in_mid)
1278
1279 def action(self, m):
1280 self.idsync(m)
1281 m.d.sync += self.out_z.eq(self.mod.out_z)
1282 m.next = "corrections"
1283
1284
1285 class FPCorrectionsMod:
1286
1287 def __init__(self, width):
1288 self.in_z = FPNumOut(width, False)
1289 self.out_z = FPNumOut(width, False)
1290
1291 def setup(self, m, in_z):
1292 """ links module to inputs and outputs
1293 """
1294 m.submodules.corrections = self
1295 m.d.comb += self.in_z.eq(in_z)
1296
1297 def elaborate(self, platform):
1298 m = Module()
1299 m.submodules.corr_in_z = self.in_z
1300 m.submodules.corr_out_z = self.out_z
1301 m.d.comb += self.out_z.eq(self.in_z)
1302 with m.If(self.in_z.is_denormalised):
1303 m.d.comb += self.out_z.e.eq(self.in_z.N127)
1304 return m
1305
1306
1307 class FPCorrections(FPState, FPID):
1308
1309 def __init__(self, width, id_wid):
1310 FPState.__init__(self, "corrections")
1311 FPID.__init__(self, id_wid)
1312 self.mod = FPCorrectionsMod(width)
1313 self.out_z = FPNumBase(width)
1314
1315 def setup(self, m, in_z, in_mid):
1316 """ links module to inputs and outputs
1317 """
1318 self.mod.setup(m, in_z)
1319 if self.in_mid is not None:
1320 m.d.comb += self.in_mid.eq(in_mid)
1321
1322 def action(self, m):
1323 self.idsync(m)
1324 m.d.sync += self.out_z.eq(self.mod.out_z)
1325 m.next = "pack"
1326
1327
1328 class FPPackMod:
1329
1330 def __init__(self, width):
1331 self.in_z = FPNumOut(width, False)
1332 self.out_z = FPNumOut(width, False)
1333
1334 def setup(self, m, in_z):
1335 """ links module to inputs and outputs
1336 """
1337 m.submodules.pack = self
1338 m.d.comb += self.in_z.eq(in_z)
1339
1340 def elaborate(self, platform):
1341 m = Module()
1342 m.submodules.pack_in_z = self.in_z
1343 with m.If(self.in_z.is_overflowed):
1344 m.d.comb += self.out_z.inf(self.in_z.s)
1345 with m.Else():
1346 m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
1347 return m
1348
1349
1350 class FPPack(FPState, FPID):
1351
1352 def __init__(self, width, id_wid):
1353 FPState.__init__(self, "pack")
1354 FPID.__init__(self, id_wid)
1355 self.mod = FPPackMod(width)
1356 self.out_z = FPNumOut(width, False)
1357
1358 def setup(self, m, in_z, in_mid):
1359 """ links module to inputs and outputs
1360 """
1361 self.mod.setup(m, in_z)
1362 if self.in_mid is not None:
1363 m.d.comb += self.in_mid.eq(in_mid)
1364
1365 def action(self, m):
1366 self.idsync(m)
1367 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1368 m.next = "pack_put_z"
1369
1370
1371 class FPPutZ(FPState):
1372
1373 def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1374 FPState.__init__(self, state)
1375 if to_state is None:
1376 to_state = "get_ops"
1377 self.to_state = to_state
1378 self.in_z = in_z
1379 self.out_z = out_z
1380 self.in_mid = in_mid
1381 self.out_mid = out_mid
1382
1383 def action(self, m):
1384 if self.in_mid is not None:
1385 m.d.sync += self.out_mid.eq(self.in_mid)
1386 m.d.sync += [
1387 self.out_z.v.eq(self.in_z.v)
1388 ]
1389 with m.If(self.out_z.stb & self.out_z.ack):
1390 m.d.sync += self.out_z.stb.eq(0)
1391 m.next = self.to_state
1392 with m.Else():
1393 m.d.sync += self.out_z.stb.eq(1)
1394
1395
1396 class FPPutZIdx(FPState):
1397
1398 def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1399 FPState.__init__(self, state)
1400 if to_state is None:
1401 to_state = "get_ops"
1402 self.to_state = to_state
1403 self.in_z = in_z
1404 self.out_zs = out_zs
1405 self.in_mid = in_mid
1406
1407 def action(self, m):
1408 outz_stb = Signal(reset_less=True)
1409 outz_ack = Signal(reset_less=True)
1410 m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1411 outz_ack.eq(self.out_zs[self.in_mid].ack),
1412 ]
1413 m.d.sync += [
1414 self.out_zs[self.in_mid].v.eq(self.in_z.v)
1415 ]
1416 with m.If(outz_stb & outz_ack):
1417 m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1418 m.next = self.to_state
1419 with m.Else():
1420 m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1421
1422
1423 class FPADDBaseMod(FPID):
1424
1425 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1426 """ IEEE754 FP Add
1427
1428 * width: bit-width of IEEE754. supported: 16, 32, 64
1429 * id_wid: an identifier that is sync-connected to the input
1430 * single_cycle: True indicates each stage to complete in 1 clock
1431 * compact: True indicates a reduced number of stages
1432 """
1433 FPID.__init__(self, id_wid)
1434 self.width = width
1435 self.single_cycle = single_cycle
1436 self.compact = compact
1437
1438 self.in_t = Trigger()
1439 self.in_a = Signal(width)
1440 self.in_b = Signal(width)
1441 self.out_z = FPOp(width)
1442
1443 self.states = []
1444
1445 def add_state(self, state):
1446 self.states.append(state)
1447 return state
1448
1449 def get_fragment(self, platform=None):
1450 """ creates the HDL code-fragment for FPAdd
1451 """
1452 m = Module()
1453 m.submodules.out_z = self.out_z
1454 m.submodules.in_t = self.in_t
1455 if self.compact:
1456 self.get_compact_fragment(m, platform)
1457 else:
1458 self.get_longer_fragment(m, platform)
1459
1460 with m.FSM() as fsm:
1461
1462 for state in self.states:
1463 with m.State(state.state_from):
1464 state.action(m)
1465
1466 return m
1467
1468 def get_longer_fragment(self, m, platform=None):
1469
1470 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1471 self.in_a, self.in_b, self.width))
1472 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1473 a = get.out_op1
1474 b = get.out_op2
1475
1476 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1477 sc.setup(m, a, b, self.in_mid)
1478
1479 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1480 dn.setup(m, a, b, sc.in_mid)
1481
1482 if self.single_cycle:
1483 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1484 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1485 else:
1486 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1487 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1488
1489 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1490 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1491
1492 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1493 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1494
1495 if self.single_cycle:
1496 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1497 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1498 else:
1499 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1500 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1501
1502 rn = self.add_state(FPRound(self.width, self.id_wid))
1503 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1504
1505 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1506 cor.setup(m, rn.out_z, rn.in_mid)
1507
1508 pa = self.add_state(FPPack(self.width, self.id_wid))
1509 pa.setup(m, cor.out_z, rn.in_mid)
1510
1511 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1512 pa.in_mid, self.out_mid))
1513
1514 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1515 pa.in_mid, self.out_mid))
1516
1517 def get_compact_fragment(self, m, platform=None):
1518
1519 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1520 self.in_a, self.in_b, self.width))
1521 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1522 a = get.out_op1
1523 b = get.out_op2
1524
1525 sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1526 sc.setup(m, a, b, self.in_mid)
1527
1528 alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1529 alm.setup(m, sc.out_a, sc.out_b, sc.in_mid)
1530
1531 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1532 n1.setup(m, alm.out_z, alm.out_of, alm.in_mid)
1533
1534 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
1535 n1.in_mid, self.out_mid))
1536
1537 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1538 sc.in_mid, self.out_mid))
1539
1540
1541 class FPADDBase(FPState, FPID):
1542
1543 def __init__(self, width, id_wid=None, single_cycle=False):
1544 """ IEEE754 FP Add
1545
1546 * width: bit-width of IEEE754. supported: 16, 32, 64
1547 * id_wid: an identifier that is sync-connected to the input
1548 * single_cycle: True indicates each stage to complete in 1 clock
1549 """
1550 FPID.__init__(self, id_wid)
1551 FPState.__init__(self, "fpadd")
1552 self.width = width
1553 self.single_cycle = single_cycle
1554 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1555
1556 self.in_t = Trigger()
1557 self.in_a = Signal(width)
1558 self.in_b = Signal(width)
1559 #self.out_z = FPOp(width)
1560
1561 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1562 self.in_accept = Signal(reset_less=True)
1563 self.add_stb = Signal(reset_less=True)
1564 self.add_ack = Signal(reset=0, reset_less=True)
1565
1566 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1567 self.out_z = out_z
1568 self.out_mid = out_mid
1569 m.d.comb += [self.in_a.eq(a),
1570 self.in_b.eq(b),
1571 self.mod.in_a.eq(self.in_a),
1572 self.mod.in_b.eq(self.in_b),
1573 self.in_mid.eq(in_mid),
1574 self.mod.in_mid.eq(self.in_mid),
1575 self.z_done.eq(self.mod.out_z.trigger),
1576 #self.add_stb.eq(add_stb),
1577 self.mod.in_t.stb.eq(self.in_t.stb),
1578 self.in_t.ack.eq(self.mod.in_t.ack),
1579 self.out_mid.eq(self.mod.out_mid),
1580 self.out_z.v.eq(self.mod.out_z.v),
1581 self.out_z.stb.eq(self.mod.out_z.stb),
1582 self.mod.out_z.ack.eq(self.out_z.ack),
1583 ]
1584
1585 m.d.sync += self.add_stb.eq(add_stb)
1586 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1587 m.d.sync += self.out_z.ack.eq(0) # likewise
1588 #m.d.sync += self.in_t.stb.eq(0)
1589
1590 m.submodules.fpadd = self.mod
1591
1592 def action(self, m):
1593
1594 # in_accept is set on incoming strobe HIGH and ack LOW.
1595 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1596
1597 #with m.If(self.in_t.ack):
1598 # m.d.sync += self.in_t.stb.eq(0)
1599 with m.If(~self.z_done):
1600 # not done: test for accepting an incoming operand pair
1601 with m.If(self.in_accept):
1602 m.d.sync += [
1603 self.add_ack.eq(1), # acknowledge receipt...
1604 self.in_t.stb.eq(1), # initiate add
1605 ]
1606 with m.Else():
1607 m.d.sync += [self.add_ack.eq(0),
1608 self.in_t.stb.eq(0),
1609 self.out_z.ack.eq(1),
1610 ]
1611 with m.Else():
1612 # done: acknowledge, and write out id and value
1613 m.d.sync += [self.add_ack.eq(1),
1614 self.in_t.stb.eq(0)
1615 ]
1616 m.next = "put_z"
1617
1618 return
1619
1620 if self.in_mid is not None:
1621 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1622
1623 m.d.sync += [
1624 self.out_z.v.eq(self.mod.out_z.v)
1625 ]
1626 # move to output state on detecting z ack
1627 with m.If(self.out_z.trigger):
1628 m.d.sync += self.out_z.stb.eq(0)
1629 m.next = "put_z"
1630 with m.Else():
1631 m.d.sync += self.out_z.stb.eq(1)
1632
1633 class ResArray:
1634 def __init__(self, width, id_wid):
1635 self.width = width
1636 self.id_wid = id_wid
1637 res = []
1638 for i in range(rs_sz):
1639 out_z = FPOp(width)
1640 out_z.name = "out_z_%d" % i
1641 res.append(out_z)
1642 self.res = Array(res)
1643 self.in_z = FPOp(width)
1644 self.in_mid = Signal(self.id_wid, reset_less=True)
1645
1646 def setup(self, m, in_z, in_mid):
1647 m.d.comb += [self.in_z.eq(in_z),
1648 self.in_mid.eq(in_mid)]
1649
1650 def get_fragment(self, platform=None):
1651 """ creates the HDL code-fragment for FPAdd
1652 """
1653 m = Module()
1654 m.submodules.res_in_z = self.in_z
1655 m.submodules += self.res
1656
1657 return m
1658
1659 def ports(self):
1660 res = []
1661 for z in self.res:
1662 res += z.ports()
1663 return res
1664
1665
1666 class FPADD(FPID):
1667 """ FPADD: stages as follows:
1668
1669 FPGetOp (a)
1670 |
1671 FPGetOp (b)
1672 |
1673 FPAddBase---> FPAddBaseMod
1674 | |
1675 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1676
1677 FPAddBase is tricky: it is both a stage and *has* stages.
1678 Connection to FPAddBaseMod therefore requires an in stb/ack
1679 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1680 needs to be the thing that raises the incoming stb.
1681 """
1682
1683 def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1684 """ IEEE754 FP Add
1685
1686 * width: bit-width of IEEE754. supported: 16, 32, 64
1687 * id_wid: an identifier that is sync-connected to the input
1688 * single_cycle: True indicates each stage to complete in 1 clock
1689 """
1690 self.width = width
1691 self.id_wid = id_wid
1692 self.single_cycle = single_cycle
1693
1694 #self.out_z = FPOp(width)
1695 self.ids = FPID(id_wid)
1696
1697 rs = []
1698 for i in range(rs_sz):
1699 in_a = FPOp(width)
1700 in_b = FPOp(width)
1701 in_a.name = "in_a_%d" % i
1702 in_b.name = "in_b_%d" % i
1703 rs.append((in_a, in_b))
1704 self.rs = Array(rs)
1705
1706 res = []
1707 for i in range(rs_sz):
1708 out_z = FPOp(width)
1709 out_z.name = "out_z_%d" % i
1710 res.append(out_z)
1711 self.res = Array(res)
1712
1713 self.states = []
1714
1715 def add_state(self, state):
1716 self.states.append(state)
1717 return state
1718
1719 def get_fragment(self, platform=None):
1720 """ creates the HDL code-fragment for FPAdd
1721 """
1722 m = Module()
1723 m.submodules += self.rs
1724
1725 in_a = self.rs[0][0]
1726 in_b = self.rs[0][1]
1727
1728 out_z = FPOp(self.width)
1729 out_mid = Signal(self.id_wid, reset_less=True)
1730 m.submodules.out_z = out_z
1731
1732 geta = self.add_state(FPGetOp("get_a", "get_b",
1733 in_a, self.width))
1734 geta.setup(m, in_a)
1735 a = geta.out_op
1736
1737 getb = self.add_state(FPGetOp("get_b", "fpadd",
1738 in_b, self.width))
1739 getb.setup(m, in_b)
1740 b = getb.out_op
1741
1742 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1743 ab = self.add_state(ab)
1744 ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1745 out_z, out_mid)
1746
1747 pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1748 out_mid, "get_a"))
1749
1750 with m.FSM() as fsm:
1751
1752 for state in self.states:
1753 with m.State(state.state_from):
1754 state.action(m)
1755
1756 return m
1757
1758
1759 if __name__ == "__main__":
1760 if True:
1761 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1762 main(alu, ports=alu.rs[0][0].ports() + \
1763 alu.rs[0][1].ports() + \
1764 alu.res[0].ports() + \
1765 [alu.ids.in_mid, alu.ids.out_mid])
1766 else:
1767 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1768 main(alu, ports=[alu.in_a, alu.in_b] + \
1769 alu.in_t.ports() + \
1770 alu.out_z.ports() + \
1771 [alu.in_mid, alu.out_mid])
1772
1773
1774 # works... but don't use, just do "python fname.py convert -t v"
1775 #print (verilog.convert(alu, ports=[
1776 # ports=alu.in_a.ports() + \
1777 # alu.in_b.ports() + \
1778 # alu.out_z.ports())