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[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 #from fpbase import FPNumShiftMultiRight
13
14
15 class FPState(FPBase):
16 def __init__(self, state_from):
17 self.state_from = state_from
18
19 def set_inputs(self, inputs):
20 self.inputs = inputs
21 for k,v in inputs.items():
22 setattr(self, k, v)
23
24 def set_outputs(self, outputs):
25 self.outputs = outputs
26 for k,v in outputs.items():
27 setattr(self, k, v)
28
29
30 class FPGetSyncOpsMod:
31 def __init__(self, width, num_ops=2):
32 self.width = width
33 self.num_ops = num_ops
34 inops = []
35 outops = []
36 for i in range(num_ops):
37 inops.append(Signal(width, reset_less=True))
38 outops.append(Signal(width, reset_less=True))
39 self.in_op = inops
40 self.out_op = outops
41 self.stb = Signal(num_ops)
42 self.ack = Signal()
43 self.ready = Signal(reset_less=True)
44 self.out_decode = Signal(reset_less=True)
45
46 def elaborate(self, platform):
47 m = Module()
48 m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
49 m.d.comb += self.out_decode.eq(self.ack & self.ready)
50 with m.If(self.out_decode):
51 for i in range(self.num_ops):
52 m.d.comb += [
53 self.out_op[i].eq(self.in_op[i]),
54 ]
55 return m
56
57 def ports(self):
58 return self.in_op + self.out_op + [self.stb, self.ack]
59
60
61 class FPOps(Trigger):
62 def __init__(self, width, num_ops):
63 Trigger.__init__(self)
64 self.width = width
65 self.num_ops = num_ops
66
67 res = []
68 for i in range(num_ops):
69 res.append(Signal(width))
70 self.v = Array(res)
71
72 def ports(self):
73 res = []
74 for i in range(self.num_ops):
75 res.append(self.v[i])
76 res.append(self.ack)
77 res.append(self.stb)
78 return res
79
80
81 class InputGroup:
82 def __init__(self, width, num_ops=2, num_rows=4):
83 self.width = width
84 self.num_ops = num_ops
85 self.num_rows = num_rows
86 self.mmax = int(log(self.num_rows) / log(2))
87 self.rs = []
88 self.mid = Signal(self.mmax, reset_less=True) # multiplex id
89 for i in range(num_rows):
90 self.rs.append(FPGetSyncOpsMod(width, num_ops))
91 self.rs = Array(self.rs)
92
93 self.out_op = FPOps(width, num_ops)
94
95 def elaborate(self, platform):
96 m = Module()
97
98 pe = PriorityEncoder(self.num_rows)
99 m.submodules.selector = pe
100 m.submodules.out_op = self.out_op
101 m.submodules += self.rs
102
103 # connect priority encoder
104 in_ready = []
105 for i in range(self.num_rows):
106 in_ready.append(self.rs[i].ready)
107 m.d.comb += pe.i.eq(Cat(*in_ready))
108
109 active = Signal(reset_less=True)
110 out_en = Signal(reset_less=True)
111 m.d.comb += active.eq(~pe.n) # encoder active
112 m.d.comb += out_en.eq(active & self.out_op.trigger)
113
114 # encoder active: ack relevant input, record MID, pass output
115 with m.If(out_en):
116 rs = self.rs[pe.o]
117 m.d.sync += self.mid.eq(pe.o)
118 m.d.sync += rs.ack.eq(0)
119 m.d.sync += self.out_op.stb.eq(0)
120 for j in range(self.num_ops):
121 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
122 with m.Else():
123 m.d.sync += self.out_op.stb.eq(1)
124 # acks all default to zero
125 for i in range(self.num_rows):
126 m.d.sync += self.rs[i].ack.eq(1)
127
128 return m
129
130 def ports(self):
131 res = []
132 for i in range(self.num_rows):
133 inop = self.rs[i]
134 res += inop.in_op + [inop.stb]
135 return self.out_op.ports() + res + [self.mid]
136
137
138 class FPGetOpMod:
139 def __init__(self, width):
140 self.in_op = FPOp(width)
141 self.out_op = Signal(width)
142 self.out_decode = Signal(reset_less=True)
143
144 def elaborate(self, platform):
145 m = Module()
146 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
147 m.submodules.get_op_in = self.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m.If(self.out_decode):
150 m.d.comb += [
151 self.out_op.eq(self.in_op.v),
152 ]
153 return m
154
155
156 class FPGetOp(FPState):
157 """ gets operand
158 """
159
160 def __init__(self, in_state, out_state, in_op, width):
161 FPState.__init__(self, in_state)
162 self.out_state = out_state
163 self.mod = FPGetOpMod(width)
164 self.in_op = in_op
165 self.out_op = Signal(width)
166 self.out_decode = Signal(reset_less=True)
167
168 def setup(self, m, in_op):
169 """ links module to inputs and outputs
170 """
171 setattr(m.submodules, self.state_from, self.mod)
172 m.d.comb += self.mod.in_op.eq(in_op)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m.d.comb += self.out_decode.eq(self.mod.out_decode)
175
176 def action(self, m):
177 with m.If(self.out_decode):
178 m.next = self.out_state
179 m.d.sync += [
180 self.in_op.ack.eq(0),
181 self.out_op.eq(self.mod.out_op)
182 ]
183 with m.Else():
184 m.d.sync += self.in_op.ack.eq(1)
185
186
187 class FPGet2OpMod(Trigger):
188 def __init__(self, width):
189 Trigger.__init__(self)
190 self.in_op1 = Signal(width, reset_less=True)
191 self.in_op2 = Signal(width, reset_less=True)
192 self.out_op1 = FPNumIn(None, width)
193 self.out_op2 = FPNumIn(None, width)
194
195 def elaborate(self, platform):
196 m = Trigger.elaborate(self, platform)
197 #m.submodules.get_op_in = self.in_op
198 m.submodules.get_op1_out = self.out_op1
199 m.submodules.get_op2_out = self.out_op2
200 with m.If(self.trigger):
201 m.d.comb += [
202 self.out_op1.decode(self.in_op1),
203 self.out_op2.decode(self.in_op2),
204 ]
205 return m
206
207
208 class FPGet2Op(FPState):
209 """ gets operands
210 """
211
212 def __init__(self, in_state, out_state, in_op1, in_op2, width):
213 FPState.__init__(self, in_state)
214 self.out_state = out_state
215 self.mod = FPGet2OpMod(width)
216 self.in_op1 = in_op1
217 self.in_op2 = in_op2
218 self.out_op1 = FPNumIn(None, width)
219 self.out_op2 = FPNumIn(None, width)
220 self.in_stb = Signal(reset_less=True)
221 self.out_ack = Signal(reset_less=True)
222 self.out_decode = Signal(reset_less=True)
223
224 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
225 """ links module to inputs and outputs
226 """
227 m.submodules.get_ops = self.mod
228 m.d.comb += self.mod.in_op1.eq(in_op1)
229 m.d.comb += self.mod.in_op2.eq(in_op2)
230 m.d.comb += self.mod.stb.eq(in_stb)
231 m.d.comb += self.out_ack.eq(self.mod.ack)
232 m.d.comb += self.out_decode.eq(self.mod.trigger)
233 m.d.comb += in_ack.eq(self.mod.ack)
234
235 def action(self, m):
236 with m.If(self.out_decode):
237 m.next = self.out_state
238 m.d.sync += [
239 self.mod.ack.eq(0),
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self.out_op1.eq(self.mod.out_op1),
243 self.out_op2.eq(self.mod.out_op2)
244 ]
245 with m.Else():
246 m.d.sync += self.mod.ack.eq(1)
247
248 class FPNumBase2Ops:
249
250 def __init__(self, width, m_extra=True):
251 self.a = FPNumBase(width, m_extra)
252 self.b = FPNumBase(width, m_extra)
253
254 def eq(self, i):
255 return [self.a.eq(i.a), self.b.eq(i.b)]
256
257
258 class FPAddSpecialCasesMod:
259 """ special cases: NaNs, infs, zeros, denormalised
260 NOTE: some of these are unique to add. see "Special Operations"
261 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
262 """
263
264 def __init__(self, width):
265 self.width = width
266 self.i = self.ispec()
267 self.out_z = self.ospec()
268 self.out_do_z = Signal(reset_less=True)
269
270 def ispec(self):
271 return FPNumBase2Ops(self.width)
272
273 def ospec(self):
274 return FPNumOut(self.width, False)
275
276 def setup(self, m, in_a, in_b, out_do_z):
277 """ links module to inputs and outputs
278 """
279 m.submodules.specialcases = self
280 m.d.comb += self.i.a.eq(in_a)
281 m.d.comb += self.i.b.eq(in_b)
282 m.d.comb += out_do_z.eq(self.out_do_z)
283
284 def elaborate(self, platform):
285 m = Module()
286
287 m.submodules.sc_in_a = self.i.a
288 m.submodules.sc_in_b = self.i.b
289 m.submodules.sc_out_z = self.out_z
290
291 s_nomatch = Signal()
292 m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
293
294 m_match = Signal()
295 m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
296
297 # if a is NaN or b is NaN return NaN
298 with m.If(self.i.a.is_nan | self.i.b.is_nan):
299 m.d.comb += self.out_do_z.eq(1)
300 m.d.comb += self.out_z.nan(0)
301
302 # XXX WEIRDNESS for FP16 non-canonical NaN handling
303 # under review
304
305 ## if a is zero and b is NaN return -b
306 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
307 # m.d.comb += self.out_do_z.eq(1)
308 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
309
310 ## if b is zero and a is NaN return -a
311 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
312 # m.d.comb += self.out_do_z.eq(1)
313 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
314
315 ## if a is -zero and b is NaN return -b
316 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
317 # m.d.comb += self.out_do_z.eq(1)
318 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
319
320 ## if b is -zero and a is NaN return -a
321 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
322 # m.d.comb += self.out_do_z.eq(1)
323 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
324
325 # if a is inf return inf (or NaN)
326 with m.Elif(self.i.a.is_inf):
327 m.d.comb += self.out_do_z.eq(1)
328 m.d.comb += self.out_z.inf(self.i.a.s)
329 # if a is inf and signs don't match return NaN
330 with m.If(self.i.b.exp_128 & s_nomatch):
331 m.d.comb += self.out_z.nan(0)
332
333 # if b is inf return inf
334 with m.Elif(self.i.b.is_inf):
335 m.d.comb += self.out_do_z.eq(1)
336 m.d.comb += self.out_z.inf(self.i.b.s)
337
338 # if a is zero and b zero return signed-a/b
339 with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
340 m.d.comb += self.out_do_z.eq(1)
341 m.d.comb += self.out_z.create(self.i.a.s & self.i.b.s,
342 self.i.b.e,
343 self.i.b.m[3:-1])
344
345 # if a is zero return b
346 with m.Elif(self.i.a.is_zero):
347 m.d.comb += self.out_do_z.eq(1)
348 m.d.comb += self.out_z.create(self.i.b.s, self.i.b.e,
349 self.i.b.m[3:-1])
350
351 # if b is zero return a
352 with m.Elif(self.i.b.is_zero):
353 m.d.comb += self.out_do_z.eq(1)
354 m.d.comb += self.out_z.create(self.i.a.s, self.i.a.e,
355 self.i.a.m[3:-1])
356
357 # if a equal to -b return zero (+ve zero)
358 with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
359 m.d.comb += self.out_do_z.eq(1)
360 m.d.comb += self.out_z.zero(0)
361
362 # Denormalised Number checks
363 with m.Else():
364 m.d.comb += self.out_do_z.eq(0)
365
366 return m
367
368
369 class FPID:
370 def __init__(self, id_wid):
371 self.id_wid = id_wid
372 if self.id_wid:
373 self.in_mid = Signal(id_wid, reset_less=True)
374 self.out_mid = Signal(id_wid, reset_less=True)
375 else:
376 self.in_mid = None
377 self.out_mid = None
378
379 def idsync(self, m):
380 if self.id_wid is not None:
381 m.d.sync += self.out_mid.eq(self.in_mid)
382
383
384 class FPAddSpecialCases(FPState, FPID):
385 """ special cases: NaNs, infs, zeros, denormalised
386 NOTE: some of these are unique to add. see "Special Operations"
387 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
388 """
389
390 def __init__(self, width, id_wid):
391 FPState.__init__(self, "special_cases")
392 FPID.__init__(self, id_wid)
393 self.mod = FPAddSpecialCasesMod(width)
394 self.out_z = self.mod.ospec()
395 self.out_do_z = Signal(reset_less=True)
396
397 def setup(self, m, in_a, in_b, in_mid):
398 """ links module to inputs and outputs
399 """
400 self.mod.setup(m, in_a, in_b, self.out_do_z)
401 if self.in_mid is not None:
402 m.d.comb += self.in_mid.eq(in_mid)
403
404 def action(self, m):
405 self.idsync(m)
406 with m.If(self.out_do_z):
407 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
408 m.next = "put_z"
409 with m.Else():
410 m.next = "denormalise"
411
412
413 class FPAddSpecialCasesDeNorm(FPState, FPID):
414 """ special cases: NaNs, infs, zeros, denormalised
415 NOTE: some of these are unique to add. see "Special Operations"
416 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
417 """
418
419 def __init__(self, width, id_wid):
420 FPState.__init__(self, "special_cases")
421 FPID.__init__(self, id_wid)
422 self.smod = FPAddSpecialCasesMod(width)
423 self.out_z = self.smod.ospec()
424 self.out_do_z = Signal(reset_less=True)
425
426 self.dmod = FPAddDeNormMod(width)
427 self.o = self.dmod.ospec()
428
429 def setup(self, m, in_a, in_b, in_mid):
430 """ links module to inputs and outputs
431 """
432 self.smod.setup(m, in_a, in_b, self.out_do_z)
433 self.dmod.setup(m, in_a, in_b)
434 if self.in_mid is not None:
435 m.d.comb += self.in_mid.eq(in_mid)
436
437 def action(self, m):
438 self.idsync(m)
439 with m.If(self.out_do_z):
440 m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
441 m.next = "put_z"
442 with m.Else():
443 m.next = "align"
444 m.d.sync += self.o.a.eq(self.dmod.o.a)
445 m.d.sync += self.o.b.eq(self.dmod.o.b)
446
447
448 class FPAddDeNormMod(FPState):
449
450 def __init__(self, width):
451 self.width = width
452 self.i = self.ispec()
453 self.o = self.ospec()
454
455 def ispec(self):
456 return FPNumBase2Ops(self.width)
457
458 def ospec(self):
459 return FPNumBase2Ops(self.width)
460
461 def setup(self, m, in_a, in_b):
462 """ links module to inputs and outputs
463 """
464 m.submodules.denormalise = self
465 m.d.comb += self.i.a.eq(in_a)
466 m.d.comb += self.i.b.eq(in_b)
467
468 def elaborate(self, platform):
469 m = Module()
470 m.submodules.denorm_in_a = self.i.a
471 m.submodules.denorm_in_b = self.i.b
472 m.submodules.denorm_out_a = self.o.a
473 m.submodules.denorm_out_b = self.o.b
474 # hmmm, don't like repeating identical code
475 m.d.comb += self.o.a.eq(self.i.a)
476 with m.If(self.i.a.exp_n127):
477 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
478 with m.Else():
479 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
480
481 m.d.comb += self.o.b.eq(self.i.b)
482 with m.If(self.i.b.exp_n127):
483 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
484 with m.Else():
485 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
486
487 return m
488
489
490 class FPAddDeNorm(FPState, FPID):
491
492 def __init__(self, width, id_wid):
493 FPState.__init__(self, "denormalise")
494 FPID.__init__(self, id_wid)
495 self.mod = FPAddDeNormMod(width)
496 self.out_a = FPNumBase(width)
497 self.out_b = FPNumBase(width)
498
499 def setup(self, m, in_a, in_b, in_mid):
500 """ links module to inputs and outputs
501 """
502 self.mod.setup(m, in_a, in_b)
503 if self.in_mid is not None:
504 m.d.comb += self.in_mid.eq(in_mid)
505
506 def action(self, m):
507 self.idsync(m)
508 # Denormalised Number checks
509 m.next = "align"
510 m.d.sync += self.out_a.eq(self.mod.out_a)
511 m.d.sync += self.out_b.eq(self.mod.out_b)
512
513
514 class FPAddAlignMultiMod(FPState):
515
516 def __init__(self, width):
517 self.in_a = FPNumBase(width)
518 self.in_b = FPNumBase(width)
519 self.out_a = FPNumIn(None, width)
520 self.out_b = FPNumIn(None, width)
521 self.exp_eq = Signal(reset_less=True)
522
523 def elaborate(self, platform):
524 # This one however (single-cycle) will do the shift
525 # in one go.
526
527 m = Module()
528
529 m.submodules.align_in_a = self.in_a
530 m.submodules.align_in_b = self.in_b
531 m.submodules.align_out_a = self.out_a
532 m.submodules.align_out_b = self.out_b
533
534 # NOTE: this does *not* do single-cycle multi-shifting,
535 # it *STAYS* in the align state until exponents match
536
537 # exponent of a greater than b: shift b down
538 m.d.comb += self.exp_eq.eq(0)
539 m.d.comb += self.out_a.eq(self.in_a)
540 m.d.comb += self.out_b.eq(self.in_b)
541 agtb = Signal(reset_less=True)
542 altb = Signal(reset_less=True)
543 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
544 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
545 with m.If(agtb):
546 m.d.comb += self.out_b.shift_down(self.in_b)
547 # exponent of b greater than a: shift a down
548 with m.Elif(altb):
549 m.d.comb += self.out_a.shift_down(self.in_a)
550 # exponents equal: move to next stage.
551 with m.Else():
552 m.d.comb += self.exp_eq.eq(1)
553 return m
554
555
556 class FPAddAlignMulti(FPState, FPID):
557
558 def __init__(self, width, id_wid):
559 FPID.__init__(self, id_wid)
560 FPState.__init__(self, "align")
561 self.mod = FPAddAlignMultiMod(width)
562 self.out_a = FPNumIn(None, width)
563 self.out_b = FPNumIn(None, width)
564 self.exp_eq = Signal(reset_less=True)
565
566 def setup(self, m, in_a, in_b, in_mid):
567 """ links module to inputs and outputs
568 """
569 m.submodules.align = self.mod
570 m.d.comb += self.mod.in_a.eq(in_a)
571 m.d.comb += self.mod.in_b.eq(in_b)
572 #m.d.comb += self.out_a.eq(self.mod.out_a)
573 #m.d.comb += self.out_b.eq(self.mod.out_b)
574 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
575 if self.in_mid is not None:
576 m.d.comb += self.in_mid.eq(in_mid)
577
578 def action(self, m):
579 self.idsync(m)
580 m.d.sync += self.out_a.eq(self.mod.out_a)
581 m.d.sync += self.out_b.eq(self.mod.out_b)
582 with m.If(self.exp_eq):
583 m.next = "add_0"
584
585
586 class FPNumIn2Ops:
587
588 def __init__(self, width):
589 self.a = FPNumIn(None, width)
590 self.b = FPNumIn(None, width)
591
592 def eq(self, i):
593 return [self.a.eq(i.a), self.b.eq(i.b)]
594
595
596 class FPAddAlignSingleMod:
597
598 def __init__(self, width):
599 self.width = width
600 self.i = self.ispec()
601 self.o = self.ospec()
602
603 def ispec(self):
604 return FPNumBase2Ops(self.width)
605
606 def ospec(self):
607 return FPNumIn2Ops(self.width)
608
609 def setup(self, m, in_a, in_b):
610 """ links module to inputs and outputs
611 """
612 m.submodules.align = self
613 m.d.comb += self.i.a.eq(in_a)
614 m.d.comb += self.i.b.eq(in_b)
615
616 def elaborate(self, platform):
617 """ Aligns A against B or B against A, depending on which has the
618 greater exponent. This is done in a *single* cycle using
619 variable-width bit-shift
620
621 the shifter used here is quite expensive in terms of gates.
622 Mux A or B in (and out) into temporaries, as only one of them
623 needs to be aligned against the other
624 """
625 m = Module()
626
627 m.submodules.align_in_a = self.i.a
628 m.submodules.align_in_b = self.i.b
629 m.submodules.align_out_a = self.o.a
630 m.submodules.align_out_b = self.o.b
631
632 # temporary (muxed) input and output to be shifted
633 t_inp = FPNumBase(self.width)
634 t_out = FPNumIn(None, self.width)
635 espec = (len(self.i.a.e), True)
636 msr = MultiShiftRMerge(self.i.a.m_width, espec)
637 m.submodules.align_t_in = t_inp
638 m.submodules.align_t_out = t_out
639 m.submodules.multishift_r = msr
640
641 ediff = Signal(espec, reset_less=True)
642 ediffr = Signal(espec, reset_less=True)
643 tdiff = Signal(espec, reset_less=True)
644 elz = Signal(reset_less=True)
645 egz = Signal(reset_less=True)
646
647 # connect multi-shifter to t_inp/out mantissa (and tdiff)
648 m.d.comb += msr.inp.eq(t_inp.m)
649 m.d.comb += msr.diff.eq(tdiff)
650 m.d.comb += t_out.m.eq(msr.m)
651 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
652 m.d.comb += t_out.s.eq(t_inp.s)
653
654 m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
655 m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
656 m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
657 m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
658
659 # default: A-exp == B-exp, A and B untouched (fall through)
660 m.d.comb += self.o.a.eq(self.i.a)
661 m.d.comb += self.o.b.eq(self.i.b)
662 # only one shifter (muxed)
663 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
664 # exponent of a greater than b: shift b down
665 with m.If(egz):
666 m.d.comb += [t_inp.eq(self.i.b),
667 tdiff.eq(ediff),
668 self.o.b.eq(t_out),
669 self.o.b.s.eq(self.i.b.s), # whoops forgot sign
670 ]
671 # exponent of b greater than a: shift a down
672 with m.Elif(elz):
673 m.d.comb += [t_inp.eq(self.i.a),
674 tdiff.eq(ediffr),
675 self.o.a.eq(t_out),
676 self.o.a.s.eq(self.i.a.s), # whoops forgot sign
677 ]
678 return m
679
680
681 class FPAddAlignSingle(FPState, FPID):
682
683 def __init__(self, width, id_wid):
684 FPState.__init__(self, "align")
685 FPID.__init__(self, id_wid)
686 self.mod = FPAddAlignSingleMod(width)
687 self.out_a = FPNumIn(None, width)
688 self.out_b = FPNumIn(None, width)
689
690 def setup(self, m, in_a, in_b, in_mid):
691 """ links module to inputs and outputs
692 """
693 self.mod.setup(m, in_a, in_b)
694 if self.in_mid is not None:
695 m.d.comb += self.in_mid.eq(in_mid)
696
697 def action(self, m):
698 self.idsync(m)
699 # NOTE: could be done as comb
700 m.d.sync += self.out_a.eq(self.mod.out_a)
701 m.d.sync += self.out_b.eq(self.mod.out_b)
702 m.next = "add_0"
703
704
705 class FPAddAlignSingleAdd(FPState, FPID):
706
707 def __init__(self, width, id_wid):
708 FPState.__init__(self, "align")
709 FPID.__init__(self, id_wid)
710 self.mod = FPAddAlignSingleMod(width)
711 self.o = self.mod.ospec()
712
713 self.a0mod = FPAddStage0Mod(width)
714 self.a0_out_z = FPNumBase(width, False)
715 self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
716 self.a0_out_z = FPNumBase(width, False)
717
718 self.a1mod = FPAddStage1Mod(width)
719 self.out_z = FPNumBase(width, False)
720 self.out_of = Overflow()
721
722 def setup(self, m, in_a, in_b, in_mid):
723 """ links module to inputs and outputs
724 """
725 self.mod.setup(m, in_a, in_b)
726 m.d.comb += self.o.eq(self.mod.o)
727
728 self.a0mod.setup(m, self.o.a, self.o.b)
729 m.d.comb += self.a0_out_z.eq(self.a0mod.o.z)
730 m.d.comb += self.out_tot.eq(self.a0mod.o.tot)
731
732 self.a1mod.setup(m, self.out_tot, self.a0_out_z)
733
734 if self.in_mid is not None:
735 m.d.comb += self.in_mid.eq(in_mid)
736
737 def action(self, m):
738 self.idsync(m)
739 m.d.sync += self.out_of.eq(self.a1mod.out_of)
740 m.d.sync += self.out_z.eq(self.a1mod.out_z)
741 m.next = "normalise_1"
742
743
744 class FPAddStage0Data:
745
746 def __init__(self, width):
747 self.z = FPNumBase(width, False)
748 self.tot = Signal(self.z.m_width + 4, reset_less=True)
749
750 def eq(self, i):
751 return [self.z.eq(i.z), self.tot.eq(i.tot)]
752
753
754 class FPAddStage0Mod:
755
756 def __init__(self, width):
757 self.width = width
758 self.i = self.ispec()
759 self.o = self.ospec()
760
761 def ispec(self):
762 return FPNumBase2Ops(self.width)
763
764 def ospec(self):
765 return FPAddStage0Data(self.width)
766
767 def setup(self, m, in_a, in_b):
768 """ links module to inputs and outputs
769 """
770 m.submodules.add0 = self
771 m.d.comb += self.i.a.eq(in_a)
772 m.d.comb += self.i.b.eq(in_b)
773
774 def elaborate(self, platform):
775 m = Module()
776 m.submodules.add0_in_a = self.i.a
777 m.submodules.add0_in_b = self.i.b
778 m.submodules.add0_out_z = self.o.z
779
780 m.d.comb += self.o.z.e.eq(self.i.a.e)
781
782 # store intermediate tests (and zero-extended mantissas)
783 seq = Signal(reset_less=True)
784 mge = Signal(reset_less=True)
785 am0 = Signal(len(self.i.a.m)+1, reset_less=True)
786 bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
787 m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
788 mge.eq(self.i.a.m >= self.i.b.m),
789 am0.eq(Cat(self.i.a.m, 0)),
790 bm0.eq(Cat(self.i.b.m, 0))
791 ]
792 # same-sign (both negative or both positive) add mantissas
793 with m.If(seq):
794 m.d.comb += [
795 self.o.tot.eq(am0 + bm0),
796 self.o.z.s.eq(self.i.a.s)
797 ]
798 # a mantissa greater than b, use a
799 with m.Elif(mge):
800 m.d.comb += [
801 self.o.tot.eq(am0 - bm0),
802 self.o.z.s.eq(self.i.a.s)
803 ]
804 # b mantissa greater than a, use b
805 with m.Else():
806 m.d.comb += [
807 self.o.tot.eq(bm0 - am0),
808 self.o.z.s.eq(self.i.b.s)
809 ]
810 return m
811
812
813 class FPAddStage0(FPState, FPID):
814 """ First stage of add. covers same-sign (add) and subtract
815 special-casing when mantissas are greater or equal, to
816 give greatest accuracy.
817 """
818
819 def __init__(self, width, id_wid):
820 FPState.__init__(self, "add_0")
821 FPID.__init__(self, id_wid)
822 self.mod = FPAddStage0Mod(width)
823 self.o = self.mod.ospec()
824
825 def setup(self, m, in_a, in_b, in_mid):
826 """ links module to inputs and outputs
827 """
828 self.mod.setup(m, in_a, in_b)
829 if self.in_mid is not None:
830 m.d.comb += self.in_mid.eq(in_mid)
831
832 def action(self, m):
833 self.idsync(m)
834 # NOTE: these could be done as combinatorial (merge add0+add1)
835 m.d.sync += self.o.eq(self.mod.o)
836 m.next = "add_1"
837
838
839 class FPAddStage1Mod(FPState):
840 """ Second stage of add: preparation for normalisation.
841 detects when tot sum is too big (tot[27] is kinda a carry bit)
842 """
843
844 def __init__(self, width):
845 self.out_norm = Signal(reset_less=True)
846 self.in_z = FPNumBase(width, False)
847 self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
848 self.out_z = FPNumBase(width, False)
849 self.out_of = Overflow()
850
851 def setup(self, m, in_tot, in_z):
852 """ links module to inputs and outputs
853 """
854 m.submodules.add1 = self
855 m.submodules.add1_out_overflow = self.out_of
856
857 m.d.comb += self.in_z.eq(in_z)
858 m.d.comb += self.in_tot.eq(in_tot)
859
860 def elaborate(self, platform):
861 m = Module()
862 #m.submodules.norm1_in_overflow = self.in_of
863 #m.submodules.norm1_out_overflow = self.out_of
864 #m.submodules.norm1_in_z = self.in_z
865 #m.submodules.norm1_out_z = self.out_z
866 m.d.comb += self.out_z.eq(self.in_z)
867 # tot[-1] (MSB) gets set when the sum overflows. shift result down
868 with m.If(self.in_tot[-1]):
869 m.d.comb += [
870 self.out_z.m.eq(self.in_tot[4:]),
871 self.out_of.m0.eq(self.in_tot[4]),
872 self.out_of.guard.eq(self.in_tot[3]),
873 self.out_of.round_bit.eq(self.in_tot[2]),
874 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
875 self.out_z.e.eq(self.in_z.e + 1)
876 ]
877 # tot[-1] (MSB) zero case
878 with m.Else():
879 m.d.comb += [
880 self.out_z.m.eq(self.in_tot[3:]),
881 self.out_of.m0.eq(self.in_tot[3]),
882 self.out_of.guard.eq(self.in_tot[2]),
883 self.out_of.round_bit.eq(self.in_tot[1]),
884 self.out_of.sticky.eq(self.in_tot[0])
885 ]
886 return m
887
888
889 class FPAddStage1(FPState, FPID):
890
891 def __init__(self, width, id_wid):
892 FPState.__init__(self, "add_1")
893 FPID.__init__(self, id_wid)
894 self.mod = FPAddStage1Mod(width)
895 self.out_z = FPNumBase(width, False)
896 self.out_of = Overflow()
897 self.norm_stb = Signal()
898
899 def setup(self, m, in_tot, in_z, in_mid):
900 """ links module to inputs and outputs
901 """
902 self.mod.setup(m, in_tot, in_z)
903
904 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
905
906 if self.in_mid is not None:
907 m.d.comb += self.in_mid.eq(in_mid)
908
909 def action(self, m):
910 self.idsync(m)
911 m.d.sync += self.out_of.eq(self.mod.out_of)
912 m.d.sync += self.out_z.eq(self.mod.out_z)
913 m.d.sync += self.norm_stb.eq(1)
914 m.next = "normalise_1"
915
916
917 class FPNormaliseModSingle:
918
919 def __init__(self, width):
920 self.width = width
921 self.in_z = FPNumBase(width, False)
922 self.out_z = FPNumBase(width, False)
923
924 def setup(self, m, in_z, out_z, modname):
925 """ links module to inputs and outputs
926 """
927 m.submodules.normalise = self
928 m.d.comb += self.in_z.eq(in_z)
929 m.d.comb += out_z.eq(self.out_z)
930
931 def elaborate(self, platform):
932 m = Module()
933
934 mwid = self.out_z.m_width+2
935 pe = PriorityEncoder(mwid)
936 m.submodules.norm_pe = pe
937
938 m.submodules.norm1_out_z = self.out_z
939 m.submodules.norm1_in_z = self.in_z
940
941 in_z = FPNumBase(self.width, False)
942 in_of = Overflow()
943 m.submodules.norm1_insel_z = in_z
944 m.submodules.norm1_insel_overflow = in_of
945
946 espec = (len(in_z.e), True)
947 ediff_n126 = Signal(espec, reset_less=True)
948 msr = MultiShiftRMerge(mwid, espec)
949 m.submodules.multishift_r = msr
950
951 m.d.comb += in_z.eq(self.in_z)
952 m.d.comb += in_of.eq(self.in_of)
953 # initialise out from in (overridden below)
954 m.d.comb += self.out_z.eq(in_z)
955 m.d.comb += self.out_of.eq(in_of)
956 # normalisation increase/decrease conditions
957 decrease = Signal(reset_less=True)
958 m.d.comb += decrease.eq(in_z.m_msbzero)
959 # decrease exponent
960 with m.If(decrease):
961 # *sigh* not entirely obvious: count leading zeros (clz)
962 # with a PriorityEncoder: to find from the MSB
963 # we reverse the order of the bits.
964 temp_m = Signal(mwid, reset_less=True)
965 temp_s = Signal(mwid+1, reset_less=True)
966 clz = Signal((len(in_z.e), True), reset_less=True)
967 m.d.comb += [
968 # cat round and guard bits back into the mantissa
969 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
970 pe.i.eq(temp_m[::-1]), # inverted
971 clz.eq(pe.o), # count zeros from MSB down
972 temp_s.eq(temp_m << clz), # shift mantissa UP
973 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
974 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
975 ]
976
977 return m
978
979
980 class FPNorm1ModSingle:
981
982 def __init__(self, width):
983 self.width = width
984 self.out_norm = Signal(reset_less=True)
985 self.in_z = FPNumBase(width, False)
986 self.in_of = Overflow()
987 self.out_z = FPNumBase(width, False)
988 self.out_of = Overflow()
989
990 def setup(self, m, in_z, in_of, out_z):
991 """ links module to inputs and outputs
992 """
993 m.submodules.normalise_1 = self
994
995 m.d.comb += self.in_z.eq(in_z)
996 m.d.comb += self.in_of.eq(in_of)
997
998 m.d.comb += out_z.eq(self.out_z)
999
1000 def elaborate(self, platform):
1001 m = Module()
1002
1003 mwid = self.out_z.m_width+2
1004 pe = PriorityEncoder(mwid)
1005 m.submodules.norm_pe = pe
1006
1007 m.submodules.norm1_out_z = self.out_z
1008 m.submodules.norm1_out_overflow = self.out_of
1009 m.submodules.norm1_in_z = self.in_z
1010 m.submodules.norm1_in_overflow = self.in_of
1011
1012 in_z = FPNumBase(self.width, False)
1013 in_of = Overflow()
1014 m.submodules.norm1_insel_z = in_z
1015 m.submodules.norm1_insel_overflow = in_of
1016
1017 espec = (len(in_z.e), True)
1018 ediff_n126 = Signal(espec, reset_less=True)
1019 msr = MultiShiftRMerge(mwid, espec)
1020 m.submodules.multishift_r = msr
1021
1022 m.d.comb += in_z.eq(self.in_z)
1023 m.d.comb += in_of.eq(self.in_of)
1024 # initialise out from in (overridden below)
1025 m.d.comb += self.out_z.eq(in_z)
1026 m.d.comb += self.out_of.eq(in_of)
1027 # normalisation increase/decrease conditions
1028 decrease = Signal(reset_less=True)
1029 increase = Signal(reset_less=True)
1030 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1031 m.d.comb += increase.eq(in_z.exp_lt_n126)
1032 # decrease exponent
1033 with m.If(decrease):
1034 # *sigh* not entirely obvious: count leading zeros (clz)
1035 # with a PriorityEncoder: to find from the MSB
1036 # we reverse the order of the bits.
1037 temp_m = Signal(mwid, reset_less=True)
1038 temp_s = Signal(mwid+1, reset_less=True)
1039 clz = Signal((len(in_z.e), True), reset_less=True)
1040 # make sure that the amount to decrease by does NOT
1041 # go below the minimum non-INF/NaN exponent
1042 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
1043 in_z.exp_sub_n126)
1044 m.d.comb += [
1045 # cat round and guard bits back into the mantissa
1046 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1047 pe.i.eq(temp_m[::-1]), # inverted
1048 clz.eq(limclz), # count zeros from MSB down
1049 temp_s.eq(temp_m << clz), # shift mantissa UP
1050 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
1051 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
1052 self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
1053 # overflow in bits 0..1: got shifted too (leave sticky)
1054 self.out_of.guard.eq(temp_s[1]), # guard
1055 self.out_of.round_bit.eq(temp_s[0]), # round
1056 ]
1057 # increase exponent
1058 with m.Elif(increase):
1059 temp_m = Signal(mwid+1, reset_less=True)
1060 m.d.comb += [
1061 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
1062 in_z.m)),
1063 ediff_n126.eq(in_z.N126 - in_z.e),
1064 # connect multi-shifter to inp/out mantissa (and ediff)
1065 msr.inp.eq(temp_m),
1066 msr.diff.eq(ediff_n126),
1067 self.out_z.m.eq(msr.m[3:]),
1068 self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
1069 # overflow in bits 0..1: got shifted too (leave sticky)
1070 self.out_of.guard.eq(temp_s[2]), # guard
1071 self.out_of.round_bit.eq(temp_s[1]), # round
1072 self.out_of.sticky.eq(temp_s[0]), # sticky
1073 self.out_z.e.eq(in_z.e + ediff_n126),
1074 ]
1075
1076 return m
1077
1078
1079 class FPNorm1ModMulti:
1080
1081 def __init__(self, width, single_cycle=True):
1082 self.width = width
1083 self.in_select = Signal(reset_less=True)
1084 self.out_norm = Signal(reset_less=True)
1085 self.in_z = FPNumBase(width, False)
1086 self.in_of = Overflow()
1087 self.temp_z = FPNumBase(width, False)
1088 self.temp_of = Overflow()
1089 self.out_z = FPNumBase(width, False)
1090 self.out_of = Overflow()
1091
1092 def elaborate(self, platform):
1093 m = Module()
1094
1095 m.submodules.norm1_out_z = self.out_z
1096 m.submodules.norm1_out_overflow = self.out_of
1097 m.submodules.norm1_temp_z = self.temp_z
1098 m.submodules.norm1_temp_of = self.temp_of
1099 m.submodules.norm1_in_z = self.in_z
1100 m.submodules.norm1_in_overflow = self.in_of
1101
1102 in_z = FPNumBase(self.width, False)
1103 in_of = Overflow()
1104 m.submodules.norm1_insel_z = in_z
1105 m.submodules.norm1_insel_overflow = in_of
1106
1107 # select which of temp or in z/of to use
1108 with m.If(self.in_select):
1109 m.d.comb += in_z.eq(self.in_z)
1110 m.d.comb += in_of.eq(self.in_of)
1111 with m.Else():
1112 m.d.comb += in_z.eq(self.temp_z)
1113 m.d.comb += in_of.eq(self.temp_of)
1114 # initialise out from in (overridden below)
1115 m.d.comb += self.out_z.eq(in_z)
1116 m.d.comb += self.out_of.eq(in_of)
1117 # normalisation increase/decrease conditions
1118 decrease = Signal(reset_less=True)
1119 increase = Signal(reset_less=True)
1120 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1121 m.d.comb += increase.eq(in_z.exp_lt_n126)
1122 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1123 # decrease exponent
1124 with m.If(decrease):
1125 m.d.comb += [
1126 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
1127 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1128 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1129 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1130 self.out_of.round_bit.eq(0), # reset round bit
1131 self.out_of.m0.eq(in_of.guard),
1132 ]
1133 # increase exponent
1134 with m.Elif(increase):
1135 m.d.comb += [
1136 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
1137 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1138 self.out_of.guard.eq(in_z.m[0]),
1139 self.out_of.m0.eq(in_z.m[1]),
1140 self.out_of.round_bit.eq(in_of.guard),
1141 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1142 ]
1143
1144 return m
1145
1146
1147 class FPNorm1Single(FPState, FPID):
1148
1149 def __init__(self, width, id_wid, single_cycle=True):
1150 FPID.__init__(self, id_wid)
1151 FPState.__init__(self, "normalise_1")
1152 self.mod = FPNorm1ModSingle(width)
1153 self.out_norm = Signal(reset_less=True)
1154 self.out_z = FPNumBase(width)
1155 self.out_roundz = Signal(reset_less=True)
1156
1157 def setup(self, m, in_z, in_of, in_mid):
1158 """ links module to inputs and outputs
1159 """
1160 self.mod.setup(m, in_z, in_of, self.out_z)
1161
1162 if self.in_mid is not None:
1163 m.d.comb += self.in_mid.eq(in_mid)
1164
1165 def action(self, m):
1166 self.idsync(m)
1167 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1168 m.next = "round"
1169
1170
1171 class FPNorm1Multi(FPState, FPID):
1172
1173 def __init__(self, width, id_wid):
1174 FPID.__init__(self, id_wid)
1175 FPState.__init__(self, "normalise_1")
1176 self.mod = FPNorm1ModMulti(width)
1177 self.stb = Signal(reset_less=True)
1178 self.ack = Signal(reset=0, reset_less=True)
1179 self.out_norm = Signal(reset_less=True)
1180 self.in_accept = Signal(reset_less=True)
1181 self.temp_z = FPNumBase(width)
1182 self.temp_of = Overflow()
1183 self.out_z = FPNumBase(width)
1184 self.out_roundz = Signal(reset_less=True)
1185
1186 def setup(self, m, in_z, in_of, norm_stb, in_mid):
1187 """ links module to inputs and outputs
1188 """
1189 self.mod.setup(m, in_z, in_of, norm_stb,
1190 self.in_accept, self.temp_z, self.temp_of,
1191 self.out_z, self.out_norm)
1192
1193 m.d.comb += self.stb.eq(norm_stb)
1194 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1195
1196 if self.in_mid is not None:
1197 m.d.comb += self.in_mid.eq(in_mid)
1198
1199 def action(self, m):
1200 self.idsync(m)
1201 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1202 m.d.sync += self.temp_of.eq(self.mod.out_of)
1203 m.d.sync += self.temp_z.eq(self.out_z)
1204 with m.If(self.out_norm):
1205 with m.If(self.in_accept):
1206 m.d.sync += [
1207 self.ack.eq(1),
1208 ]
1209 with m.Else():
1210 m.d.sync += self.ack.eq(0)
1211 with m.Else():
1212 # normalisation not required (or done).
1213 m.next = "round"
1214 m.d.sync += self.ack.eq(1)
1215 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1216
1217
1218 class FPNormToPack(FPState, FPID):
1219
1220 def __init__(self, width, id_wid):
1221 FPID.__init__(self, id_wid)
1222 FPState.__init__(self, "normalise_1")
1223 self.width = width
1224
1225 def setup(self, m, in_z, in_of, in_mid):
1226 """ links module to inputs and outputs
1227 """
1228
1229 # Normalisation (chained to input in_z+in_of)
1230 nmod = FPNorm1ModSingle(self.width)
1231 n_out_z = FPNumBase(self.width)
1232 n_out_roundz = Signal(reset_less=True)
1233 nmod.setup(m, in_z, in_of, n_out_z)
1234
1235 # Rounding (chained to normalisation)
1236 rmod = FPRoundMod(self.width)
1237 r_out_z = FPNumBase(self.width)
1238 rmod.setup(m, n_out_z, n_out_roundz)
1239 m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
1240 m.d.comb += r_out_z.eq(rmod.out_z)
1241
1242 # Corrections (chained to rounding)
1243 cmod = FPCorrectionsMod(self.width)
1244 c_out_z = FPNumBase(self.width)
1245 cmod.setup(m, r_out_z)
1246 m.d.comb += c_out_z.eq(cmod.out_z)
1247
1248 # Pack (chained to corrections)
1249 self.pmod = FPPackMod(self.width)
1250 self.out_z = FPNumBase(self.width)
1251 self.pmod.setup(m, c_out_z)
1252
1253 # Multiplex ID
1254 if self.in_mid is not None:
1255 m.d.comb += self.in_mid.eq(in_mid)
1256
1257 def action(self, m):
1258 self.idsync(m) # copies incoming ID to outgoing
1259 m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
1260 m.next = "pack_put_z"
1261
1262
1263 class FPRoundMod:
1264
1265 def __init__(self, width):
1266 self.in_roundz = Signal(reset_less=True)
1267 self.in_z = FPNumBase(width, False)
1268 self.out_z = FPNumBase(width, False)
1269
1270 def setup(self, m, in_z, roundz):
1271 m.submodules.roundz = self
1272
1273 m.d.comb += self.in_z.eq(in_z)
1274 m.d.comb += self.in_roundz.eq(roundz)
1275
1276 def elaborate(self, platform):
1277 m = Module()
1278 m.d.comb += self.out_z.eq(self.in_z)
1279 with m.If(self.in_roundz):
1280 m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
1281 with m.If(self.in_z.m == self.in_z.m1s): # all 1s
1282 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
1283 return m
1284
1285
1286 class FPRound(FPState, FPID):
1287
1288 def __init__(self, width, id_wid):
1289 FPState.__init__(self, "round")
1290 FPID.__init__(self, id_wid)
1291 self.mod = FPRoundMod(width)
1292 self.out_z = FPNumBase(width)
1293
1294 def setup(self, m, in_z, roundz, in_mid):
1295 """ links module to inputs and outputs
1296 """
1297 self.mod.setup(m, in_z, roundz)
1298
1299 if self.in_mid is not None:
1300 m.d.comb += self.in_mid.eq(in_mid)
1301
1302 def action(self, m):
1303 self.idsync(m)
1304 m.d.sync += self.out_z.eq(self.mod.out_z)
1305 m.next = "corrections"
1306
1307
1308 class FPCorrectionsMod:
1309
1310 def __init__(self, width):
1311 self.in_z = FPNumOut(width, False)
1312 self.out_z = FPNumOut(width, False)
1313
1314 def setup(self, m, in_z):
1315 """ links module to inputs and outputs
1316 """
1317 m.submodules.corrections = self
1318 m.d.comb += self.in_z.eq(in_z)
1319
1320 def elaborate(self, platform):
1321 m = Module()
1322 m.submodules.corr_in_z = self.in_z
1323 m.submodules.corr_out_z = self.out_z
1324 m.d.comb += self.out_z.eq(self.in_z)
1325 with m.If(self.in_z.is_denormalised):
1326 m.d.comb += self.out_z.e.eq(self.in_z.N127)
1327 return m
1328
1329
1330 class FPCorrections(FPState, FPID):
1331
1332 def __init__(self, width, id_wid):
1333 FPState.__init__(self, "corrections")
1334 FPID.__init__(self, id_wid)
1335 self.mod = FPCorrectionsMod(width)
1336 self.out_z = FPNumBase(width)
1337
1338 def setup(self, m, in_z, in_mid):
1339 """ links module to inputs and outputs
1340 """
1341 self.mod.setup(m, in_z)
1342 if self.in_mid is not None:
1343 m.d.comb += self.in_mid.eq(in_mid)
1344
1345 def action(self, m):
1346 self.idsync(m)
1347 m.d.sync += self.out_z.eq(self.mod.out_z)
1348 m.next = "pack"
1349
1350
1351 class FPPackMod:
1352
1353 def __init__(self, width):
1354 self.in_z = FPNumOut(width, False)
1355 self.out_z = FPNumOut(width, False)
1356
1357 def setup(self, m, in_z):
1358 """ links module to inputs and outputs
1359 """
1360 m.submodules.pack = self
1361 m.d.comb += self.in_z.eq(in_z)
1362
1363 def elaborate(self, platform):
1364 m = Module()
1365 m.submodules.pack_in_z = self.in_z
1366 with m.If(self.in_z.is_overflowed):
1367 m.d.comb += self.out_z.inf(self.in_z.s)
1368 with m.Else():
1369 m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
1370 return m
1371
1372
1373 class FPPack(FPState, FPID):
1374
1375 def __init__(self, width, id_wid):
1376 FPState.__init__(self, "pack")
1377 FPID.__init__(self, id_wid)
1378 self.mod = FPPackMod(width)
1379 self.out_z = FPNumOut(width, False)
1380
1381 def setup(self, m, in_z, in_mid):
1382 """ links module to inputs and outputs
1383 """
1384 self.mod.setup(m, in_z)
1385 if self.in_mid is not None:
1386 m.d.comb += self.in_mid.eq(in_mid)
1387
1388 def action(self, m):
1389 self.idsync(m)
1390 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1391 m.next = "pack_put_z"
1392
1393
1394 class FPPutZ(FPState):
1395
1396 def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1397 FPState.__init__(self, state)
1398 if to_state is None:
1399 to_state = "get_ops"
1400 self.to_state = to_state
1401 self.in_z = in_z
1402 self.out_z = out_z
1403 self.in_mid = in_mid
1404 self.out_mid = out_mid
1405
1406 def action(self, m):
1407 if self.in_mid is not None:
1408 m.d.sync += self.out_mid.eq(self.in_mid)
1409 m.d.sync += [
1410 self.out_z.v.eq(self.in_z.v)
1411 ]
1412 with m.If(self.out_z.stb & self.out_z.ack):
1413 m.d.sync += self.out_z.stb.eq(0)
1414 m.next = self.to_state
1415 with m.Else():
1416 m.d.sync += self.out_z.stb.eq(1)
1417
1418
1419 class FPPutZIdx(FPState):
1420
1421 def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1422 FPState.__init__(self, state)
1423 if to_state is None:
1424 to_state = "get_ops"
1425 self.to_state = to_state
1426 self.in_z = in_z
1427 self.out_zs = out_zs
1428 self.in_mid = in_mid
1429
1430 def action(self, m):
1431 outz_stb = Signal(reset_less=True)
1432 outz_ack = Signal(reset_less=True)
1433 m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1434 outz_ack.eq(self.out_zs[self.in_mid].ack),
1435 ]
1436 m.d.sync += [
1437 self.out_zs[self.in_mid].v.eq(self.in_z.v)
1438 ]
1439 with m.If(outz_stb & outz_ack):
1440 m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1441 m.next = self.to_state
1442 with m.Else():
1443 m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1444
1445
1446 class FPADDBaseMod(FPID):
1447
1448 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1449 """ IEEE754 FP Add
1450
1451 * width: bit-width of IEEE754. supported: 16, 32, 64
1452 * id_wid: an identifier that is sync-connected to the input
1453 * single_cycle: True indicates each stage to complete in 1 clock
1454 * compact: True indicates a reduced number of stages
1455 """
1456 FPID.__init__(self, id_wid)
1457 self.width = width
1458 self.single_cycle = single_cycle
1459 self.compact = compact
1460
1461 self.in_t = Trigger()
1462 self.in_a = Signal(width)
1463 self.in_b = Signal(width)
1464 self.out_z = FPOp(width)
1465
1466 self.states = []
1467
1468 def add_state(self, state):
1469 self.states.append(state)
1470 return state
1471
1472 def get_fragment(self, platform=None):
1473 """ creates the HDL code-fragment for FPAdd
1474 """
1475 m = Module()
1476 m.submodules.out_z = self.out_z
1477 m.submodules.in_t = self.in_t
1478 if self.compact:
1479 self.get_compact_fragment(m, platform)
1480 else:
1481 self.get_longer_fragment(m, platform)
1482
1483 with m.FSM() as fsm:
1484
1485 for state in self.states:
1486 with m.State(state.state_from):
1487 state.action(m)
1488
1489 return m
1490
1491 def get_longer_fragment(self, m, platform=None):
1492
1493 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1494 self.in_a, self.in_b, self.width))
1495 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1496 a = get.out_op1
1497 b = get.out_op2
1498
1499 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1500 sc.setup(m, a, b, self.in_mid)
1501
1502 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1503 dn.setup(m, a, b, sc.in_mid)
1504
1505 if self.single_cycle:
1506 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1507 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1508 else:
1509 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1510 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1511
1512 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1513 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1514
1515 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1516 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1517
1518 if self.single_cycle:
1519 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1520 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1521 else:
1522 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1523 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1524
1525 rn = self.add_state(FPRound(self.width, self.id_wid))
1526 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1527
1528 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1529 cor.setup(m, rn.out_z, rn.in_mid)
1530
1531 pa = self.add_state(FPPack(self.width, self.id_wid))
1532 pa.setup(m, cor.out_z, rn.in_mid)
1533
1534 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1535 pa.in_mid, self.out_mid))
1536
1537 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1538 pa.in_mid, self.out_mid))
1539
1540 def get_compact_fragment(self, m, platform=None):
1541
1542 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1543 self.in_a, self.in_b, self.width))
1544 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1545 a = get.out_op1
1546 b = get.out_op2
1547
1548 sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1549 sc.setup(m, a, b, self.in_mid)
1550
1551 alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1552 alm.setup(m, sc.o.a, sc.o.b, sc.in_mid)
1553
1554 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1555 n1.setup(m, alm.out_z, alm.out_of, alm.in_mid)
1556
1557 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
1558 n1.in_mid, self.out_mid))
1559
1560 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1561 sc.in_mid, self.out_mid))
1562
1563
1564 class FPADDBase(FPState, FPID):
1565
1566 def __init__(self, width, id_wid=None, single_cycle=False):
1567 """ IEEE754 FP Add
1568
1569 * width: bit-width of IEEE754. supported: 16, 32, 64
1570 * id_wid: an identifier that is sync-connected to the input
1571 * single_cycle: True indicates each stage to complete in 1 clock
1572 """
1573 FPID.__init__(self, id_wid)
1574 FPState.__init__(self, "fpadd")
1575 self.width = width
1576 self.single_cycle = single_cycle
1577 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1578
1579 self.in_t = Trigger()
1580 self.in_a = Signal(width)
1581 self.in_b = Signal(width)
1582 #self.out_z = FPOp(width)
1583
1584 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1585 self.in_accept = Signal(reset_less=True)
1586 self.add_stb = Signal(reset_less=True)
1587 self.add_ack = Signal(reset=0, reset_less=True)
1588
1589 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1590 self.out_z = out_z
1591 self.out_mid = out_mid
1592 m.d.comb += [self.in_a.eq(a),
1593 self.in_b.eq(b),
1594 self.mod.in_a.eq(self.in_a),
1595 self.mod.in_b.eq(self.in_b),
1596 self.in_mid.eq(in_mid),
1597 self.mod.in_mid.eq(self.in_mid),
1598 self.z_done.eq(self.mod.out_z.trigger),
1599 #self.add_stb.eq(add_stb),
1600 self.mod.in_t.stb.eq(self.in_t.stb),
1601 self.in_t.ack.eq(self.mod.in_t.ack),
1602 self.out_mid.eq(self.mod.out_mid),
1603 self.out_z.v.eq(self.mod.out_z.v),
1604 self.out_z.stb.eq(self.mod.out_z.stb),
1605 self.mod.out_z.ack.eq(self.out_z.ack),
1606 ]
1607
1608 m.d.sync += self.add_stb.eq(add_stb)
1609 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1610 m.d.sync += self.out_z.ack.eq(0) # likewise
1611 #m.d.sync += self.in_t.stb.eq(0)
1612
1613 m.submodules.fpadd = self.mod
1614
1615 def action(self, m):
1616
1617 # in_accept is set on incoming strobe HIGH and ack LOW.
1618 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1619
1620 #with m.If(self.in_t.ack):
1621 # m.d.sync += self.in_t.stb.eq(0)
1622 with m.If(~self.z_done):
1623 # not done: test for accepting an incoming operand pair
1624 with m.If(self.in_accept):
1625 m.d.sync += [
1626 self.add_ack.eq(1), # acknowledge receipt...
1627 self.in_t.stb.eq(1), # initiate add
1628 ]
1629 with m.Else():
1630 m.d.sync += [self.add_ack.eq(0),
1631 self.in_t.stb.eq(0),
1632 self.out_z.ack.eq(1),
1633 ]
1634 with m.Else():
1635 # done: acknowledge, and write out id and value
1636 m.d.sync += [self.add_ack.eq(1),
1637 self.in_t.stb.eq(0)
1638 ]
1639 m.next = "put_z"
1640
1641 return
1642
1643 if self.in_mid is not None:
1644 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1645
1646 m.d.sync += [
1647 self.out_z.v.eq(self.mod.out_z.v)
1648 ]
1649 # move to output state on detecting z ack
1650 with m.If(self.out_z.trigger):
1651 m.d.sync += self.out_z.stb.eq(0)
1652 m.next = "put_z"
1653 with m.Else():
1654 m.d.sync += self.out_z.stb.eq(1)
1655
1656 class ResArray:
1657 def __init__(self, width, id_wid):
1658 self.width = width
1659 self.id_wid = id_wid
1660 res = []
1661 for i in range(rs_sz):
1662 out_z = FPOp(width)
1663 out_z.name = "out_z_%d" % i
1664 res.append(out_z)
1665 self.res = Array(res)
1666 self.in_z = FPOp(width)
1667 self.in_mid = Signal(self.id_wid, reset_less=True)
1668
1669 def setup(self, m, in_z, in_mid):
1670 m.d.comb += [self.in_z.eq(in_z),
1671 self.in_mid.eq(in_mid)]
1672
1673 def get_fragment(self, platform=None):
1674 """ creates the HDL code-fragment for FPAdd
1675 """
1676 m = Module()
1677 m.submodules.res_in_z = self.in_z
1678 m.submodules += self.res
1679
1680 return m
1681
1682 def ports(self):
1683 res = []
1684 for z in self.res:
1685 res += z.ports()
1686 return res
1687
1688
1689 class FPADD(FPID):
1690 """ FPADD: stages as follows:
1691
1692 FPGetOp (a)
1693 |
1694 FPGetOp (b)
1695 |
1696 FPAddBase---> FPAddBaseMod
1697 | |
1698 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1699
1700 FPAddBase is tricky: it is both a stage and *has* stages.
1701 Connection to FPAddBaseMod therefore requires an in stb/ack
1702 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1703 needs to be the thing that raises the incoming stb.
1704 """
1705
1706 def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1707 """ IEEE754 FP Add
1708
1709 * width: bit-width of IEEE754. supported: 16, 32, 64
1710 * id_wid: an identifier that is sync-connected to the input
1711 * single_cycle: True indicates each stage to complete in 1 clock
1712 """
1713 self.width = width
1714 self.id_wid = id_wid
1715 self.single_cycle = single_cycle
1716
1717 #self.out_z = FPOp(width)
1718 self.ids = FPID(id_wid)
1719
1720 rs = []
1721 for i in range(rs_sz):
1722 in_a = FPOp(width)
1723 in_b = FPOp(width)
1724 in_a.name = "in_a_%d" % i
1725 in_b.name = "in_b_%d" % i
1726 rs.append((in_a, in_b))
1727 self.rs = Array(rs)
1728
1729 res = []
1730 for i in range(rs_sz):
1731 out_z = FPOp(width)
1732 out_z.name = "out_z_%d" % i
1733 res.append(out_z)
1734 self.res = Array(res)
1735
1736 self.states = []
1737
1738 def add_state(self, state):
1739 self.states.append(state)
1740 return state
1741
1742 def get_fragment(self, platform=None):
1743 """ creates the HDL code-fragment for FPAdd
1744 """
1745 m = Module()
1746 m.submodules += self.rs
1747
1748 in_a = self.rs[0][0]
1749 in_b = self.rs[0][1]
1750
1751 out_z = FPOp(self.width)
1752 out_mid = Signal(self.id_wid, reset_less=True)
1753 m.submodules.out_z = out_z
1754
1755 geta = self.add_state(FPGetOp("get_a", "get_b",
1756 in_a, self.width))
1757 geta.setup(m, in_a)
1758 a = geta.out_op
1759
1760 getb = self.add_state(FPGetOp("get_b", "fpadd",
1761 in_b, self.width))
1762 getb.setup(m, in_b)
1763 b = getb.out_op
1764
1765 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1766 ab = self.add_state(ab)
1767 ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1768 out_z, out_mid)
1769
1770 pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1771 out_mid, "get_a"))
1772
1773 with m.FSM() as fsm:
1774
1775 for state in self.states:
1776 with m.State(state.state_from):
1777 state.action(m)
1778
1779 return m
1780
1781
1782 if __name__ == "__main__":
1783 if True:
1784 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1785 main(alu, ports=alu.rs[0][0].ports() + \
1786 alu.rs[0][1].ports() + \
1787 alu.res[0].ports() + \
1788 [alu.ids.in_mid, alu.ids.out_mid])
1789 else:
1790 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1791 main(alu, ports=[alu.in_a, alu.in_b] + \
1792 alu.in_t.ports() + \
1793 alu.out_z.ports() + \
1794 [alu.in_mid, alu.out_mid])
1795
1796
1797 # works... but don't use, just do "python fname.py convert -t v"
1798 #print (verilog.convert(alu, ports=[
1799 # ports=alu.in_a.ports() + \
1800 # alu.in_b.ports() + \
1801 # alu.out_z.ports())