projects / ieee754fpu.git / blob
? search:


bc5f6415c966f5cbbe1d84ad5c93e32b15596bd8
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 #from fpbase import FPNumShiftMultiRight
13
14
15 class FPState(FPBase):
16 def __init__(self, state_from):
17 self.state_from = state_from
18
19 def set_inputs(self, inputs):
20 self.inputs = inputs
21 for k,v in inputs.items():
22 setattr(self, k, v)
23
24 def set_outputs(self, outputs):
25 self.outputs = outputs
26 for k,v in outputs.items():
27 setattr(self, k, v)
28
29
30 class FPGetSyncOpsMod:
31 def __init__(self, width, num_ops=2):
32 self.width = width
33 self.num_ops = num_ops
34 inops = []
35 outops = []
36 for i in range(num_ops):
37 inops.append(Signal(width, reset_less=True))
38 outops.append(Signal(width, reset_less=True))
39 self.in_op = inops
40 self.out_op = outops
41 self.stb = Signal(num_ops)
42 self.ack = Signal()
43 self.ready = Signal(reset_less=True)
44 self.out_decode = Signal(reset_less=True)
45
46 def elaborate(self, platform):
47 m = Module()
48 m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
49 m.d.comb += self.out_decode.eq(self.ack & self.ready)
50 with m.If(self.out_decode):
51 for i in range(self.num_ops):
52 m.d.comb += [
53 self.out_op[i].eq(self.in_op[i]),
54 ]
55 return m
56
57 def ports(self):
58 return self.in_op + self.out_op + [self.stb, self.ack]
59
60
61 class FPOps(Trigger):
62 def __init__(self, width, num_ops):
63 Trigger.__init__(self)
64 self.width = width
65 self.num_ops = num_ops
66
67 res = []
68 for i in range(num_ops):
69 res.append(Signal(width))
70 self.v = Array(res)
71
72 def ports(self):
73 res = []
74 for i in range(self.num_ops):
75 res.append(self.v[i])
76 res.append(self.ack)
77 res.append(self.stb)
78 return res
79
80
81 class InputGroup:
82 def __init__(self, width, num_ops=2, num_rows=4):
83 self.width = width
84 self.num_ops = num_ops
85 self.num_rows = num_rows
86 self.mmax = int(log(self.num_rows) / log(2))
87 self.rs = []
88 self.mid = Signal(self.mmax, reset_less=True) # multiplex id
89 for i in range(num_rows):
90 self.rs.append(FPGetSyncOpsMod(width, num_ops))
91 self.rs = Array(self.rs)
92
93 self.out_op = FPOps(width, num_ops)
94
95 def elaborate(self, platform):
96 m = Module()
97
98 pe = PriorityEncoder(self.num_rows)
99 m.submodules.selector = pe
100 m.submodules.out_op = self.out_op
101 m.submodules += self.rs
102
103 # connect priority encoder
104 in_ready = []
105 for i in range(self.num_rows):
106 in_ready.append(self.rs[i].ready)
107 m.d.comb += pe.i.eq(Cat(*in_ready))
108
109 active = Signal(reset_less=True)
110 out_en = Signal(reset_less=True)
111 m.d.comb += active.eq(~pe.n) # encoder active
112 m.d.comb += out_en.eq(active & self.out_op.trigger)
113
114 # encoder active: ack relevant input, record MID, pass output
115 with m.If(out_en):
116 rs = self.rs[pe.o]
117 m.d.sync += self.mid.eq(pe.o)
118 m.d.sync += rs.ack.eq(0)
119 m.d.sync += self.out_op.stb.eq(0)
120 for j in range(self.num_ops):
121 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
122 with m.Else():
123 m.d.sync += self.out_op.stb.eq(1)
124 # acks all default to zero
125 for i in range(self.num_rows):
126 m.d.sync += self.rs[i].ack.eq(1)
127
128 return m
129
130 def ports(self):
131 res = []
132 for i in range(self.num_rows):
133 inop = self.rs[i]
134 res += inop.in_op + [inop.stb]
135 return self.out_op.ports() + res + [self.mid]
136
137
138 class FPGetOpMod:
139 def __init__(self, width):
140 self.in_op = FPOp(width)
141 self.out_op = Signal(width)
142 self.out_decode = Signal(reset_less=True)
143
144 def elaborate(self, platform):
145 m = Module()
146 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
147 m.submodules.get_op_in = self.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m.If(self.out_decode):
150 m.d.comb += [
151 self.out_op.eq(self.in_op.v),
152 ]
153 return m
154
155
156 class FPGetOp(FPState):
157 """ gets operand
158 """
159
160 def __init__(self, in_state, out_state, in_op, width):
161 FPState.__init__(self, in_state)
162 self.out_state = out_state
163 self.mod = FPGetOpMod(width)
164 self.in_op = in_op
165 self.out_op = Signal(width)
166 self.out_decode = Signal(reset_less=True)
167
168 def setup(self, m, in_op):
169 """ links module to inputs and outputs
170 """
171 setattr(m.submodules, self.state_from, self.mod)
172 m.d.comb += self.mod.in_op.eq(in_op)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m.d.comb += self.out_decode.eq(self.mod.out_decode)
175
176 def action(self, m):
177 with m.If(self.out_decode):
178 m.next = self.out_state
179 m.d.sync += [
180 self.in_op.ack.eq(0),
181 self.out_op.eq(self.mod.out_op)
182 ]
183 with m.Else():
184 m.d.sync += self.in_op.ack.eq(1)
185
186
187 class FPGet2OpMod(Trigger):
188 def __init__(self, width):
189 Trigger.__init__(self)
190 self.in_op1 = Signal(width, reset_less=True)
191 self.in_op2 = Signal(width, reset_less=True)
192 self.out_op1 = FPNumIn(None, width)
193 self.out_op2 = FPNumIn(None, width)
194
195 def elaborate(self, platform):
196 m = Trigger.elaborate(self, platform)
197 #m.submodules.get_op_in = self.in_op
198 m.submodules.get_op1_out = self.out_op1
199 m.submodules.get_op2_out = self.out_op2
200 with m.If(self.trigger):
201 m.d.comb += [
202 self.out_op1.decode(self.in_op1),
203 self.out_op2.decode(self.in_op2),
204 ]
205 return m
206
207
208 class FPGet2Op(FPState):
209 """ gets operands
210 """
211
212 def __init__(self, in_state, out_state, in_op1, in_op2, width):
213 FPState.__init__(self, in_state)
214 self.out_state = out_state
215 self.mod = FPGet2OpMod(width)
216 self.in_op1 = in_op1
217 self.in_op2 = in_op2
218 self.out_op1 = FPNumIn(None, width)
219 self.out_op2 = FPNumIn(None, width)
220 self.in_stb = Signal(reset_less=True)
221 self.out_ack = Signal(reset_less=True)
222 self.out_decode = Signal(reset_less=True)
223
224 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
225 """ links module to inputs and outputs
226 """
227 m.submodules.get_ops = self.mod
228 m.d.comb += self.mod.in_op1.eq(in_op1)
229 m.d.comb += self.mod.in_op2.eq(in_op2)
230 m.d.comb += self.mod.stb.eq(in_stb)
231 m.d.comb += self.out_ack.eq(self.mod.ack)
232 m.d.comb += self.out_decode.eq(self.mod.trigger)
233 m.d.comb += in_ack.eq(self.mod.ack)
234
235 def action(self, m):
236 with m.If(self.out_decode):
237 m.next = self.out_state
238 m.d.sync += [
239 self.mod.ack.eq(0),
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self.out_op1.eq(self.mod.out_op1),
243 self.out_op2.eq(self.mod.out_op2)
244 ]
245 with m.Else():
246 m.d.sync += self.mod.ack.eq(1)
247
248 class FPNumBase2Ops:
249
250 def __init__(self, width, m_extra=True):
251 self.a = FPNumBase(width, m_extra)
252 self.b = FPNumBase(width, m_extra)
253
254 def eq(self, i):
255 return [self.a.eq(i.a), self.b.eq(i.b)]
256
257
258 class FPAddSpecialCasesMod:
259 """ special cases: NaNs, infs, zeros, denormalised
260 NOTE: some of these are unique to add. see "Special Operations"
261 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
262 """
263
264 def __init__(self, width):
265 self.width = width
266 self.i = self.ispec()
267 self.out_z = self.ospec()
268 self.out_do_z = Signal(reset_less=True)
269
270 def ispec(self):
271 return FPNumBase2Ops(self.width)
272
273 def ospec(self):
274 return FPNumOut(self.width, False)
275
276 def setup(self, m, in_a, in_b, out_do_z):
277 """ links module to inputs and outputs
278 """
279 m.submodules.specialcases = self
280 m.d.comb += self.i.a.eq(in_a)
281 m.d.comb += self.i.b.eq(in_b)
282 m.d.comb += out_do_z.eq(self.out_do_z)
283
284 def elaborate(self, platform):
285 m = Module()
286
287 m.submodules.sc_in_a = self.i.a
288 m.submodules.sc_in_b = self.i.b
289 m.submodules.sc_out_z = self.out_z
290
291 s_nomatch = Signal()
292 m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
293
294 m_match = Signal()
295 m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
296
297 # if a is NaN or b is NaN return NaN
298 with m.If(self.i.a.is_nan | self.i.b.is_nan):
299 m.d.comb += self.out_do_z.eq(1)
300 m.d.comb += self.out_z.nan(0)
301
302 # XXX WEIRDNESS for FP16 non-canonical NaN handling
303 # under review
304
305 ## if a is zero and b is NaN return -b
306 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
307 # m.d.comb += self.out_do_z.eq(1)
308 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
309
310 ## if b is zero and a is NaN return -a
311 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
312 # m.d.comb += self.out_do_z.eq(1)
313 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
314
315 ## if a is -zero and b is NaN return -b
316 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
317 # m.d.comb += self.out_do_z.eq(1)
318 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
319
320 ## if b is -zero and a is NaN return -a
321 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
322 # m.d.comb += self.out_do_z.eq(1)
323 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
324
325 # if a is inf return inf (or NaN)
326 with m.Elif(self.i.a.is_inf):
327 m.d.comb += self.out_do_z.eq(1)
328 m.d.comb += self.out_z.inf(self.i.a.s)
329 # if a is inf and signs don't match return NaN
330 with m.If(self.i.b.exp_128 & s_nomatch):
331 m.d.comb += self.out_z.nan(0)
332
333 # if b is inf return inf
334 with m.Elif(self.i.b.is_inf):
335 m.d.comb += self.out_do_z.eq(1)
336 m.d.comb += self.out_z.inf(self.i.b.s)
337
338 # if a is zero and b zero return signed-a/b
339 with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
340 m.d.comb += self.out_do_z.eq(1)
341 m.d.comb += self.out_z.create(self.i.a.s & self.i.b.s,
342 self.i.b.e,
343 self.i.b.m[3:-1])
344
345 # if a is zero return b
346 with m.Elif(self.i.a.is_zero):
347 m.d.comb += self.out_do_z.eq(1)
348 m.d.comb += self.out_z.create(self.i.b.s, self.i.b.e,
349 self.i.b.m[3:-1])
350
351 # if b is zero return a
352 with m.Elif(self.i.b.is_zero):
353 m.d.comb += self.out_do_z.eq(1)
354 m.d.comb += self.out_z.create(self.i.a.s, self.i.a.e,
355 self.i.a.m[3:-1])
356
357 # if a equal to -b return zero (+ve zero)
358 with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
359 m.d.comb += self.out_do_z.eq(1)
360 m.d.comb += self.out_z.zero(0)
361
362 # Denormalised Number checks
363 with m.Else():
364 m.d.comb += self.out_do_z.eq(0)
365
366 return m
367
368
369 class FPID:
370 def __init__(self, id_wid):
371 self.id_wid = id_wid
372 if self.id_wid:
373 self.in_mid = Signal(id_wid, reset_less=True)
374 self.out_mid = Signal(id_wid, reset_less=True)
375 else:
376 self.in_mid = None
377 self.out_mid = None
378
379 def idsync(self, m):
380 if self.id_wid is not None:
381 m.d.sync += self.out_mid.eq(self.in_mid)
382
383
384 class FPAddSpecialCases(FPState, FPID):
385 """ special cases: NaNs, infs, zeros, denormalised
386 NOTE: some of these are unique to add. see "Special Operations"
387 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
388 """
389
390 def __init__(self, width, id_wid):
391 FPState.__init__(self, "special_cases")
392 FPID.__init__(self, id_wid)
393 self.mod = FPAddSpecialCasesMod(width)
394 self.out_z = self.mod.ospec()
395 self.out_do_z = Signal(reset_less=True)
396
397 def setup(self, m, in_a, in_b, in_mid):
398 """ links module to inputs and outputs
399 """
400 self.mod.setup(m, in_a, in_b, self.out_do_z)
401 if self.in_mid is not None:
402 m.d.comb += self.in_mid.eq(in_mid)
403
404 def action(self, m):
405 self.idsync(m)
406 with m.If(self.out_do_z):
407 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
408 m.next = "put_z"
409 with m.Else():
410 m.next = "denormalise"
411
412
413 class FPAddSpecialCasesDeNorm(FPState, FPID):
414 """ special cases: NaNs, infs, zeros, denormalised
415 NOTE: some of these are unique to add. see "Special Operations"
416 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
417 """
418
419 def __init__(self, width, id_wid):
420 FPState.__init__(self, "special_cases")
421 FPID.__init__(self, id_wid)
422 self.smod = FPAddSpecialCasesMod(width)
423 self.out_z = self.smod.ospec()
424 self.out_do_z = Signal(reset_less=True)
425
426 self.dmod = FPAddDeNormMod(width)
427 self.o = self.dmod.ospec()
428
429 def setup(self, m, in_a, in_b, in_mid):
430 """ links module to inputs and outputs
431 """
432 self.smod.setup(m, in_a, in_b, self.out_do_z)
433 self.dmod.setup(m, in_a, in_b)
434 if self.in_mid is not None:
435 m.d.comb += self.in_mid.eq(in_mid)
436
437 def action(self, m):
438 self.idsync(m)
439 with m.If(self.out_do_z):
440 m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
441 m.next = "put_z"
442 with m.Else():
443 m.next = "align"
444 m.d.sync += self.o.a.eq(self.dmod.o.a)
445 m.d.sync += self.o.b.eq(self.dmod.o.b)
446
447
448 class FPAddDeNormMod(FPState):
449
450 def __init__(self, width):
451 self.width = width
452 self.i = self.ispec()
453 self.o = self.ospec()
454
455 def ispec(self):
456 return FPNumBase2Ops(self.width)
457
458 def ospec(self):
459 return FPNumBase2Ops(self.width)
460
461 def setup(self, m, in_a, in_b):
462 """ links module to inputs and outputs
463 """
464 m.submodules.denormalise = self
465 m.d.comb += self.i.a.eq(in_a)
466 m.d.comb += self.i.b.eq(in_b)
467
468 def elaborate(self, platform):
469 m = Module()
470 m.submodules.denorm_in_a = self.i.a
471 m.submodules.denorm_in_b = self.i.b
472 m.submodules.denorm_out_a = self.o.a
473 m.submodules.denorm_out_b = self.o.b
474 # hmmm, don't like repeating identical code
475 m.d.comb += self.o.a.eq(self.i.a)
476 with m.If(self.i.a.exp_n127):
477 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
478 with m.Else():
479 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
480
481 m.d.comb += self.o.b.eq(self.i.b)
482 with m.If(self.i.b.exp_n127):
483 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
484 with m.Else():
485 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
486
487 return m
488
489
490 class FPAddDeNorm(FPState, FPID):
491
492 def __init__(self, width, id_wid):
493 FPState.__init__(self, "denormalise")
494 FPID.__init__(self, id_wid)
495 self.mod = FPAddDeNormMod(width)
496 self.out_a = FPNumBase(width)
497 self.out_b = FPNumBase(width)
498
499 def setup(self, m, in_a, in_b, in_mid):
500 """ links module to inputs and outputs
501 """
502 self.mod.setup(m, in_a, in_b)
503 if self.in_mid is not None:
504 m.d.comb += self.in_mid.eq(in_mid)
505
506 def action(self, m):
507 self.idsync(m)
508 # Denormalised Number checks
509 m.next = "align"
510 m.d.sync += self.out_a.eq(self.mod.out_a)
511 m.d.sync += self.out_b.eq(self.mod.out_b)
512
513
514 class FPAddAlignMultiMod(FPState):
515
516 def __init__(self, width):
517 self.in_a = FPNumBase(width)
518 self.in_b = FPNumBase(width)
519 self.out_a = FPNumIn(None, width)
520 self.out_b = FPNumIn(None, width)
521 self.exp_eq = Signal(reset_less=True)
522
523 def elaborate(self, platform):
524 # This one however (single-cycle) will do the shift
525 # in one go.
526
527 m = Module()
528
529 m.submodules.align_in_a = self.in_a
530 m.submodules.align_in_b = self.in_b
531 m.submodules.align_out_a = self.out_a
532 m.submodules.align_out_b = self.out_b
533
534 # NOTE: this does *not* do single-cycle multi-shifting,
535 # it *STAYS* in the align state until exponents match
536
537 # exponent of a greater than b: shift b down
538 m.d.comb += self.exp_eq.eq(0)
539 m.d.comb += self.out_a.eq(self.in_a)
540 m.d.comb += self.out_b.eq(self.in_b)
541 agtb = Signal(reset_less=True)
542 altb = Signal(reset_less=True)
543 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
544 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
545 with m.If(agtb):
546 m.d.comb += self.out_b.shift_down(self.in_b)
547 # exponent of b greater than a: shift a down
548 with m.Elif(altb):
549 m.d.comb += self.out_a.shift_down(self.in_a)
550 # exponents equal: move to next stage.
551 with m.Else():
552 m.d.comb += self.exp_eq.eq(1)
553 return m
554
555
556 class FPAddAlignMulti(FPState, FPID):
557
558 def __init__(self, width, id_wid):
559 FPID.__init__(self, id_wid)
560 FPState.__init__(self, "align")
561 self.mod = FPAddAlignMultiMod(width)
562 self.out_a = FPNumIn(None, width)
563 self.out_b = FPNumIn(None, width)
564 self.exp_eq = Signal(reset_less=True)
565
566 def setup(self, m, in_a, in_b, in_mid):
567 """ links module to inputs and outputs
568 """
569 m.submodules.align = self.mod
570 m.d.comb += self.mod.in_a.eq(in_a)
571 m.d.comb += self.mod.in_b.eq(in_b)
572 #m.d.comb += self.out_a.eq(self.mod.out_a)
573 #m.d.comb += self.out_b.eq(self.mod.out_b)
574 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
575 if self.in_mid is not None:
576 m.d.comb += self.in_mid.eq(in_mid)
577
578 def action(self, m):
579 self.idsync(m)
580 m.d.sync += self.out_a.eq(self.mod.out_a)
581 m.d.sync += self.out_b.eq(self.mod.out_b)
582 with m.If(self.exp_eq):
583 m.next = "add_0"
584
585
586 class FPNumIn2Ops:
587
588 def __init__(self, width):
589 self.a = FPNumIn(None, width)
590 self.b = FPNumIn(None, width)
591
592 def eq(self, i):
593 return [self.a.eq(i.a), self.b.eq(i.b)]
594
595
596 class FPAddAlignSingleMod:
597
598 def __init__(self, width):
599 self.width = width
600 self.i = self.ispec()
601 self.o = self.ospec()
602
603 def ispec(self):
604 return FPNumBase2Ops(self.width)
605
606 def ospec(self):
607 return FPNumIn2Ops(self.width)
608
609 def setup(self, m, in_a, in_b):
610 """ links module to inputs and outputs
611 """
612 m.submodules.align = self
613 m.d.comb += self.i.a.eq(in_a)
614 m.d.comb += self.i.b.eq(in_b)
615
616 def elaborate(self, platform):
617 """ Aligns A against B or B against A, depending on which has the
618 greater exponent. This is done in a *single* cycle using
619 variable-width bit-shift
620
621 the shifter used here is quite expensive in terms of gates.
622 Mux A or B in (and out) into temporaries, as only one of them
623 needs to be aligned against the other
624 """
625 m = Module()
626
627 m.submodules.align_in_a = self.i.a
628 m.submodules.align_in_b = self.i.b
629 m.submodules.align_out_a = self.o.a
630 m.submodules.align_out_b = self.o.b
631
632 # temporary (muxed) input and output to be shifted
633 t_inp = FPNumBase(self.width)
634 t_out = FPNumIn(None, self.width)
635 espec = (len(self.i.a.e), True)
636 msr = MultiShiftRMerge(self.i.a.m_width, espec)
637 m.submodules.align_t_in = t_inp
638 m.submodules.align_t_out = t_out
639 m.submodules.multishift_r = msr
640
641 ediff = Signal(espec, reset_less=True)
642 ediffr = Signal(espec, reset_less=True)
643 tdiff = Signal(espec, reset_less=True)
644 elz = Signal(reset_less=True)
645 egz = Signal(reset_less=True)
646
647 # connect multi-shifter to t_inp/out mantissa (and tdiff)
648 m.d.comb += msr.inp.eq(t_inp.m)
649 m.d.comb += msr.diff.eq(tdiff)
650 m.d.comb += t_out.m.eq(msr.m)
651 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
652 m.d.comb += t_out.s.eq(t_inp.s)
653
654 m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
655 m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
656 m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
657 m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
658
659 # default: A-exp == B-exp, A and B untouched (fall through)
660 m.d.comb += self.o.a.eq(self.i.a)
661 m.d.comb += self.o.b.eq(self.i.b)
662 # only one shifter (muxed)
663 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
664 # exponent of a greater than b: shift b down
665 with m.If(egz):
666 m.d.comb += [t_inp.eq(self.i.b),
667 tdiff.eq(ediff),
668 self.o.b.eq(t_out),
669 self.o.b.s.eq(self.i.b.s), # whoops forgot sign
670 ]
671 # exponent of b greater than a: shift a down
672 with m.Elif(elz):
673 m.d.comb += [t_inp.eq(self.i.a),
674 tdiff.eq(ediffr),
675 self.o.a.eq(t_out),
676 self.o.a.s.eq(self.i.a.s), # whoops forgot sign
677 ]
678 return m
679
680
681 class FPAddAlignSingle(FPState, FPID):
682
683 def __init__(self, width, id_wid):
684 FPState.__init__(self, "align")
685 FPID.__init__(self, id_wid)
686 self.mod = FPAddAlignSingleMod(width)
687 self.out_a = FPNumIn(None, width)
688 self.out_b = FPNumIn(None, width)
689
690 def setup(self, m, in_a, in_b, in_mid):
691 """ links module to inputs and outputs
692 """
693 self.mod.setup(m, in_a, in_b)
694 if self.in_mid is not None:
695 m.d.comb += self.in_mid.eq(in_mid)
696
697 def action(self, m):
698 self.idsync(m)
699 # NOTE: could be done as comb
700 m.d.sync += self.out_a.eq(self.mod.out_a)
701 m.d.sync += self.out_b.eq(self.mod.out_b)
702 m.next = "add_0"
703
704
705 class FPAddAlignSingleAdd(FPState, FPID):
706
707 def __init__(self, width, id_wid):
708 FPState.__init__(self, "align")
709 FPID.__init__(self, id_wid)
710 self.mod = FPAddAlignSingleMod(width)
711 self.o = self.mod.ospec()
712
713 self.a0mod = FPAddStage0Mod(width)
714 self.a0o = self.a0mod.ospec()
715
716 self.a1mod = FPAddStage1Mod(width)
717 self.a1o = self.a1mod.ospec()
718
719 def setup(self, m, in_a, in_b, in_mid):
720 """ links module to inputs and outputs
721 """
722 self.mod.setup(m, in_a, in_b)
723 m.d.comb += self.o.eq(self.mod.o)
724
725 self.a0mod.setup(m, self.o.a, self.o.b)
726 m.d.comb += self.a0o.eq(self.a0mod.o)
727
728 self.a1mod.setup(m, self.a0o.tot, self.a0o.z)
729
730 if self.in_mid is not None:
731 m.d.comb += self.in_mid.eq(in_mid)
732
733 def action(self, m):
734 self.idsync(m)
735 m.d.sync += self.a1o.eq(self.a1mod.o)
736 m.next = "normalise_1"
737
738
739 class FPAddStage0Data:
740
741 def __init__(self, width):
742 self.z = FPNumBase(width, False)
743 self.tot = Signal(self.z.m_width + 4, reset_less=True)
744
745 def eq(self, i):
746 return [self.z.eq(i.z), self.tot.eq(i.tot)]
747
748
749 class FPAddStage0Mod:
750
751 def __init__(self, width):
752 self.width = width
753 self.i = self.ispec()
754 self.o = self.ospec()
755
756 def ispec(self):
757 return FPNumBase2Ops(self.width)
758
759 def ospec(self):
760 return FPAddStage0Data(self.width)
761
762 def setup(self, m, in_a, in_b):
763 """ links module to inputs and outputs
764 """
765 m.submodules.add0 = self
766 m.d.comb += self.i.a.eq(in_a)
767 m.d.comb += self.i.b.eq(in_b)
768
769 def elaborate(self, platform):
770 m = Module()
771 m.submodules.add0_in_a = self.i.a
772 m.submodules.add0_in_b = self.i.b
773 m.submodules.add0_out_z = self.o.z
774
775 m.d.comb += self.o.z.e.eq(self.i.a.e)
776
777 # store intermediate tests (and zero-extended mantissas)
778 seq = Signal(reset_less=True)
779 mge = Signal(reset_less=True)
780 am0 = Signal(len(self.i.a.m)+1, reset_less=True)
781 bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
782 m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
783 mge.eq(self.i.a.m >= self.i.b.m),
784 am0.eq(Cat(self.i.a.m, 0)),
785 bm0.eq(Cat(self.i.b.m, 0))
786 ]
787 # same-sign (both negative or both positive) add mantissas
788 with m.If(seq):
789 m.d.comb += [
790 self.o.tot.eq(am0 + bm0),
791 self.o.z.s.eq(self.i.a.s)
792 ]
793 # a mantissa greater than b, use a
794 with m.Elif(mge):
795 m.d.comb += [
796 self.o.tot.eq(am0 - bm0),
797 self.o.z.s.eq(self.i.a.s)
798 ]
799 # b mantissa greater than a, use b
800 with m.Else():
801 m.d.comb += [
802 self.o.tot.eq(bm0 - am0),
803 self.o.z.s.eq(self.i.b.s)
804 ]
805 return m
806
807
808 class FPAddStage0(FPState, FPID):
809 """ First stage of add. covers same-sign (add) and subtract
810 special-casing when mantissas are greater or equal, to
811 give greatest accuracy.
812 """
813
814 def __init__(self, width, id_wid):
815 FPState.__init__(self, "add_0")
816 FPID.__init__(self, id_wid)
817 self.mod = FPAddStage0Mod(width)
818 self.o = self.mod.ospec()
819
820 def setup(self, m, in_a, in_b, in_mid):
821 """ links module to inputs and outputs
822 """
823 self.mod.setup(m, in_a, in_b)
824 if self.in_mid is not None:
825 m.d.comb += self.in_mid.eq(in_mid)
826
827 def action(self, m):
828 self.idsync(m)
829 # NOTE: these could be done as combinatorial (merge add0+add1)
830 m.d.sync += self.o.eq(self.mod.o)
831 m.next = "add_1"
832
833
834 class FPAddStage1Data:
835
836 def __init__(self, width):
837 self.z = FPNumBase(width, False)
838 self.of = Overflow()
839
840 def eq(self, i):
841 return [self.z.eq(i.z), self.of.eq(i.of)]
842
843
844
845 class FPAddStage1Mod(FPState):
846 """ Second stage of add: preparation for normalisation.
847 detects when tot sum is too big (tot[27] is kinda a carry bit)
848 """
849
850 def __init__(self, width):
851 self.width = width
852 self.i = self.ispec()
853 self.o = self.ospec()
854
855 def ispec(self):
856 return FPAddStage0Data(self.width)
857
858 def ospec(self):
859 return FPAddStage1Data(self.width)
860
861 def setup(self, m, in_tot, in_z):
862 """ links module to inputs and outputs
863 """
864 m.submodules.add1 = self
865 m.submodules.add1_out_overflow = self.o.of
866
867 m.d.comb += self.i.z.eq(in_z)
868 m.d.comb += self.i.tot.eq(in_tot)
869
870 def elaborate(self, platform):
871 m = Module()
872 #m.submodules.norm1_in_overflow = self.in_of
873 #m.submodules.norm1_out_overflow = self.out_of
874 #m.submodules.norm1_in_z = self.in_z
875 #m.submodules.norm1_out_z = self.out_z
876 m.d.comb += self.o.z.eq(self.i.z)
877 # tot[-1] (MSB) gets set when the sum overflows. shift result down
878 with m.If(self.i.tot[-1]):
879 m.d.comb += [
880 self.o.z.m.eq(self.i.tot[4:]),
881 self.o.of.m0.eq(self.i.tot[4]),
882 self.o.of.guard.eq(self.i.tot[3]),
883 self.o.of.round_bit.eq(self.i.tot[2]),
884 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
885 self.o.z.e.eq(self.i.z.e + 1)
886 ]
887 # tot[-1] (MSB) zero case
888 with m.Else():
889 m.d.comb += [
890 self.o.z.m.eq(self.i.tot[3:]),
891 self.o.of.m0.eq(self.i.tot[3]),
892 self.o.of.guard.eq(self.i.tot[2]),
893 self.o.of.round_bit.eq(self.i.tot[1]),
894 self.o.of.sticky.eq(self.i.tot[0])
895 ]
896 return m
897
898
899 class FPAddStage1(FPState, FPID):
900
901 def __init__(self, width, id_wid):
902 FPState.__init__(self, "add_1")
903 FPID.__init__(self, id_wid)
904 self.mod = FPAddStage1Mod(width)
905 self.out_z = FPNumBase(width, False)
906 self.out_of = Overflow()
907 self.norm_stb = Signal()
908
909 def setup(self, m, in_tot, in_z, in_mid):
910 """ links module to inputs and outputs
911 """
912 self.mod.setup(m, in_tot, in_z)
913
914 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
915
916 if self.in_mid is not None:
917 m.d.comb += self.in_mid.eq(in_mid)
918
919 def action(self, m):
920 self.idsync(m)
921 m.d.sync += self.out_of.eq(self.mod.out_of)
922 m.d.sync += self.out_z.eq(self.mod.out_z)
923 m.d.sync += self.norm_stb.eq(1)
924 m.next = "normalise_1"
925
926
927 class FPNormaliseModSingle:
928
929 def __init__(self, width):
930 self.width = width
931 self.in_z = FPNumBase(width, False)
932 self.out_z = FPNumBase(width, False)
933
934 def setup(self, m, in_z, out_z, modname):
935 """ links module to inputs and outputs
936 """
937 m.submodules.normalise = self
938 m.d.comb += self.in_z.eq(in_z)
939 m.d.comb += out_z.eq(self.out_z)
940
941 def elaborate(self, platform):
942 m = Module()
943
944 mwid = self.out_z.m_width+2
945 pe = PriorityEncoder(mwid)
946 m.submodules.norm_pe = pe
947
948 m.submodules.norm1_out_z = self.out_z
949 m.submodules.norm1_in_z = self.in_z
950
951 in_z = FPNumBase(self.width, False)
952 in_of = Overflow()
953 m.submodules.norm1_insel_z = in_z
954 m.submodules.norm1_insel_overflow = in_of
955
956 espec = (len(in_z.e), True)
957 ediff_n126 = Signal(espec, reset_less=True)
958 msr = MultiShiftRMerge(mwid, espec)
959 m.submodules.multishift_r = msr
960
961 m.d.comb += in_z.eq(self.in_z)
962 m.d.comb += in_of.eq(self.in_of)
963 # initialise out from in (overridden below)
964 m.d.comb += self.out_z.eq(in_z)
965 m.d.comb += self.out_of.eq(in_of)
966 # normalisation increase/decrease conditions
967 decrease = Signal(reset_less=True)
968 m.d.comb += decrease.eq(in_z.m_msbzero)
969 # decrease exponent
970 with m.If(decrease):
971 # *sigh* not entirely obvious: count leading zeros (clz)
972 # with a PriorityEncoder: to find from the MSB
973 # we reverse the order of the bits.
974 temp_m = Signal(mwid, reset_less=True)
975 temp_s = Signal(mwid+1, reset_less=True)
976 clz = Signal((len(in_z.e), True), reset_less=True)
977 m.d.comb += [
978 # cat round and guard bits back into the mantissa
979 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
980 pe.i.eq(temp_m[::-1]), # inverted
981 clz.eq(pe.o), # count zeros from MSB down
982 temp_s.eq(temp_m << clz), # shift mantissa UP
983 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
984 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
985 ]
986
987 return m
988
989
990 class FPNorm1ModSingle:
991
992 def __init__(self, width):
993 self.width = width
994 self.out_norm = Signal(reset_less=True)
995 self.in_z = FPNumBase(width, False)
996 self.in_of = Overflow()
997 self.out_z = FPNumBase(width, False)
998 self.out_of = Overflow()
999
1000 def setup(self, m, in_z, in_of, out_z):
1001 """ links module to inputs and outputs
1002 """
1003 m.submodules.normalise_1 = self
1004
1005 m.d.comb += self.in_z.eq(in_z)
1006 m.d.comb += self.in_of.eq(in_of)
1007
1008 m.d.comb += out_z.eq(self.out_z)
1009
1010 def elaborate(self, platform):
1011 m = Module()
1012
1013 mwid = self.out_z.m_width+2
1014 pe = PriorityEncoder(mwid)
1015 m.submodules.norm_pe = pe
1016
1017 m.submodules.norm1_out_z = self.out_z
1018 m.submodules.norm1_out_overflow = self.out_of
1019 m.submodules.norm1_in_z = self.in_z
1020 m.submodules.norm1_in_overflow = self.in_of
1021
1022 in_z = FPNumBase(self.width, False)
1023 in_of = Overflow()
1024 m.submodules.norm1_insel_z = in_z
1025 m.submodules.norm1_insel_overflow = in_of
1026
1027 espec = (len(in_z.e), True)
1028 ediff_n126 = Signal(espec, reset_less=True)
1029 msr = MultiShiftRMerge(mwid, espec)
1030 m.submodules.multishift_r = msr
1031
1032 m.d.comb += in_z.eq(self.in_z)
1033 m.d.comb += in_of.eq(self.in_of)
1034 # initialise out from in (overridden below)
1035 m.d.comb += self.out_z.eq(in_z)
1036 m.d.comb += self.out_of.eq(in_of)
1037 # normalisation increase/decrease conditions
1038 decrease = Signal(reset_less=True)
1039 increase = Signal(reset_less=True)
1040 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1041 m.d.comb += increase.eq(in_z.exp_lt_n126)
1042 # decrease exponent
1043 with m.If(decrease):
1044 # *sigh* not entirely obvious: count leading zeros (clz)
1045 # with a PriorityEncoder: to find from the MSB
1046 # we reverse the order of the bits.
1047 temp_m = Signal(mwid, reset_less=True)
1048 temp_s = Signal(mwid+1, reset_less=True)
1049 clz = Signal((len(in_z.e), True), reset_less=True)
1050 # make sure that the amount to decrease by does NOT
1051 # go below the minimum non-INF/NaN exponent
1052 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
1053 in_z.exp_sub_n126)
1054 m.d.comb += [
1055 # cat round and guard bits back into the mantissa
1056 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1057 pe.i.eq(temp_m[::-1]), # inverted
1058 clz.eq(limclz), # count zeros from MSB down
1059 temp_s.eq(temp_m << clz), # shift mantissa UP
1060 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
1061 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
1062 self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
1063 # overflow in bits 0..1: got shifted too (leave sticky)
1064 self.out_of.guard.eq(temp_s[1]), # guard
1065 self.out_of.round_bit.eq(temp_s[0]), # round
1066 ]
1067 # increase exponent
1068 with m.Elif(increase):
1069 temp_m = Signal(mwid+1, reset_less=True)
1070 m.d.comb += [
1071 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
1072 in_z.m)),
1073 ediff_n126.eq(in_z.N126 - in_z.e),
1074 # connect multi-shifter to inp/out mantissa (and ediff)
1075 msr.inp.eq(temp_m),
1076 msr.diff.eq(ediff_n126),
1077 self.out_z.m.eq(msr.m[3:]),
1078 self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
1079 # overflow in bits 0..1: got shifted too (leave sticky)
1080 self.out_of.guard.eq(temp_s[2]), # guard
1081 self.out_of.round_bit.eq(temp_s[1]), # round
1082 self.out_of.sticky.eq(temp_s[0]), # sticky
1083 self.out_z.e.eq(in_z.e + ediff_n126),
1084 ]
1085
1086 return m
1087
1088
1089 class FPNorm1ModMulti:
1090
1091 def __init__(self, width, single_cycle=True):
1092 self.width = width
1093 self.in_select = Signal(reset_less=True)
1094 self.in_z = FPNumBase(width, False)
1095 self.in_of = Overflow()
1096 self.temp_z = FPNumBase(width, False)
1097 self.temp_of = Overflow()
1098 self.out_z = FPNumBase(width, False)
1099 self.out_of = Overflow()
1100
1101 def elaborate(self, platform):
1102 m = Module()
1103
1104 m.submodules.norm1_out_z = self.out_z
1105 m.submodules.norm1_out_overflow = self.out_of
1106 m.submodules.norm1_temp_z = self.temp_z
1107 m.submodules.norm1_temp_of = self.temp_of
1108 m.submodules.norm1_in_z = self.in_z
1109 m.submodules.norm1_in_overflow = self.in_of
1110
1111 in_z = FPNumBase(self.width, False)
1112 in_of = Overflow()
1113 m.submodules.norm1_insel_z = in_z
1114 m.submodules.norm1_insel_overflow = in_of
1115
1116 # select which of temp or in z/of to use
1117 with m.If(self.in_select):
1118 m.d.comb += in_z.eq(self.in_z)
1119 m.d.comb += in_of.eq(self.in_of)
1120 with m.Else():
1121 m.d.comb += in_z.eq(self.temp_z)
1122 m.d.comb += in_of.eq(self.temp_of)
1123 # initialise out from in (overridden below)
1124 m.d.comb += self.out_z.eq(in_z)
1125 m.d.comb += self.out_of.eq(in_of)
1126 # normalisation increase/decrease conditions
1127 decrease = Signal(reset_less=True)
1128 increase = Signal(reset_less=True)
1129 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1130 m.d.comb += increase.eq(in_z.exp_lt_n126)
1131 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1132 # decrease exponent
1133 with m.If(decrease):
1134 m.d.comb += [
1135 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
1136 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1137 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1138 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1139 self.out_of.round_bit.eq(0), # reset round bit
1140 self.out_of.m0.eq(in_of.guard),
1141 ]
1142 # increase exponent
1143 with m.Elif(increase):
1144 m.d.comb += [
1145 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
1146 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1147 self.out_of.guard.eq(in_z.m[0]),
1148 self.out_of.m0.eq(in_z.m[1]),
1149 self.out_of.round_bit.eq(in_of.guard),
1150 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1151 ]
1152
1153 return m
1154
1155
1156 class FPNorm1Single(FPState, FPID):
1157
1158 def __init__(self, width, id_wid, single_cycle=True):
1159 FPID.__init__(self, id_wid)
1160 FPState.__init__(self, "normalise_1")
1161 self.mod = FPNorm1ModSingle(width)
1162 self.out_norm = Signal(reset_less=True)
1163 self.out_z = FPNumBase(width)
1164 self.out_roundz = Signal(reset_less=True)
1165
1166 def setup(self, m, in_z, in_of, in_mid):
1167 """ links module to inputs and outputs
1168 """
1169 self.mod.setup(m, in_z, in_of, self.out_z)
1170
1171 if self.in_mid is not None:
1172 m.d.comb += self.in_mid.eq(in_mid)
1173
1174 def action(self, m):
1175 self.idsync(m)
1176 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1177 m.next = "round"
1178
1179
1180 class FPNorm1Multi(FPState, FPID):
1181
1182 def __init__(self, width, id_wid):
1183 FPID.__init__(self, id_wid)
1184 FPState.__init__(self, "normalise_1")
1185 self.mod = FPNorm1ModMulti(width)
1186 self.stb = Signal(reset_less=True)
1187 self.ack = Signal(reset=0, reset_less=True)
1188 self.out_norm = Signal(reset_less=True)
1189 self.in_accept = Signal(reset_less=True)
1190 self.temp_z = FPNumBase(width)
1191 self.temp_of = Overflow()
1192 self.out_z = FPNumBase(width)
1193 self.out_roundz = Signal(reset_less=True)
1194
1195 def setup(self, m, in_z, in_of, norm_stb, in_mid):
1196 """ links module to inputs and outputs
1197 """
1198 self.mod.setup(m, in_z, in_of, norm_stb,
1199 self.in_accept, self.temp_z, self.temp_of,
1200 self.out_z, self.out_norm)
1201
1202 m.d.comb += self.stb.eq(norm_stb)
1203 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1204
1205 if self.in_mid is not None:
1206 m.d.comb += self.in_mid.eq(in_mid)
1207
1208 def action(self, m):
1209 self.idsync(m)
1210 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1211 m.d.sync += self.temp_of.eq(self.mod.out_of)
1212 m.d.sync += self.temp_z.eq(self.out_z)
1213 with m.If(self.out_norm):
1214 with m.If(self.in_accept):
1215 m.d.sync += [
1216 self.ack.eq(1),
1217 ]
1218 with m.Else():
1219 m.d.sync += self.ack.eq(0)
1220 with m.Else():
1221 # normalisation not required (or done).
1222 m.next = "round"
1223 m.d.sync += self.ack.eq(1)
1224 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1225
1226
1227 class FPNormToPack(FPState, FPID):
1228
1229 def __init__(self, width, id_wid):
1230 FPID.__init__(self, id_wid)
1231 FPState.__init__(self, "normalise_1")
1232 self.width = width
1233
1234 def setup(self, m, in_z, in_of, in_mid):
1235 """ links module to inputs and outputs
1236 """
1237
1238 # Normalisation (chained to input in_z+in_of)
1239 nmod = FPNorm1ModSingle(self.width)
1240 n_out_z = FPNumBase(self.width)
1241 n_out_roundz = Signal(reset_less=True)
1242 nmod.setup(m, in_z, in_of, n_out_z)
1243
1244 # Rounding (chained to normalisation)
1245 rmod = FPRoundMod(self.width)
1246 r_out_z = FPNumBase(self.width)
1247 rmod.setup(m, n_out_z, n_out_roundz)
1248 m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
1249 m.d.comb += r_out_z.eq(rmod.out_z)
1250
1251 # Corrections (chained to rounding)
1252 cmod = FPCorrectionsMod(self.width)
1253 c_out_z = FPNumBase(self.width)
1254 cmod.setup(m, r_out_z)
1255 m.d.comb += c_out_z.eq(cmod.out_z)
1256
1257 # Pack (chained to corrections)
1258 self.pmod = FPPackMod(self.width)
1259 self.out_z = FPNumBase(self.width)
1260 self.pmod.setup(m, c_out_z)
1261
1262 # Multiplex ID
1263 if self.in_mid is not None:
1264 m.d.comb += self.in_mid.eq(in_mid)
1265
1266 def action(self, m):
1267 self.idsync(m) # copies incoming ID to outgoing
1268 m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
1269 m.next = "pack_put_z"
1270
1271
1272 class FPRoundMod:
1273
1274 def __init__(self, width):
1275 self.in_roundz = Signal(reset_less=True)
1276 self.in_z = FPNumBase(width, False)
1277 self.out_z = FPNumBase(width, False)
1278
1279 def setup(self, m, in_z, roundz):
1280 m.submodules.roundz = self
1281
1282 m.d.comb += self.in_z.eq(in_z)
1283 m.d.comb += self.in_roundz.eq(roundz)
1284
1285 def elaborate(self, platform):
1286 m = Module()
1287 m.d.comb += self.out_z.eq(self.in_z)
1288 with m.If(self.in_roundz):
1289 m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
1290 with m.If(self.in_z.m == self.in_z.m1s): # all 1s
1291 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
1292 return m
1293
1294
1295 class FPRound(FPState, FPID):
1296
1297 def __init__(self, width, id_wid):
1298 FPState.__init__(self, "round")
1299 FPID.__init__(self, id_wid)
1300 self.mod = FPRoundMod(width)
1301 self.out_z = FPNumBase(width)
1302
1303 def setup(self, m, in_z, roundz, in_mid):
1304 """ links module to inputs and outputs
1305 """
1306 self.mod.setup(m, in_z, roundz)
1307
1308 if self.in_mid is not None:
1309 m.d.comb += self.in_mid.eq(in_mid)
1310
1311 def action(self, m):
1312 self.idsync(m)
1313 m.d.sync += self.out_z.eq(self.mod.out_z)
1314 m.next = "corrections"
1315
1316
1317 class FPCorrectionsMod:
1318
1319 def __init__(self, width):
1320 self.in_z = FPNumOut(width, False)
1321 self.out_z = FPNumOut(width, False)
1322
1323 def setup(self, m, in_z):
1324 """ links module to inputs and outputs
1325 """
1326 m.submodules.corrections = self
1327 m.d.comb += self.in_z.eq(in_z)
1328
1329 def elaborate(self, platform):
1330 m = Module()
1331 m.submodules.corr_in_z = self.in_z
1332 m.submodules.corr_out_z = self.out_z
1333 m.d.comb += self.out_z.eq(self.in_z)
1334 with m.If(self.in_z.is_denormalised):
1335 m.d.comb += self.out_z.e.eq(self.in_z.N127)
1336 return m
1337
1338
1339 class FPCorrections(FPState, FPID):
1340
1341 def __init__(self, width, id_wid):
1342 FPState.__init__(self, "corrections")
1343 FPID.__init__(self, id_wid)
1344 self.mod = FPCorrectionsMod(width)
1345 self.out_z = FPNumBase(width)
1346
1347 def setup(self, m, in_z, in_mid):
1348 """ links module to inputs and outputs
1349 """
1350 self.mod.setup(m, in_z)
1351 if self.in_mid is not None:
1352 m.d.comb += self.in_mid.eq(in_mid)
1353
1354 def action(self, m):
1355 self.idsync(m)
1356 m.d.sync += self.out_z.eq(self.mod.out_z)
1357 m.next = "pack"
1358
1359
1360 class FPPackMod:
1361
1362 def __init__(self, width):
1363 self.in_z = FPNumOut(width, False)
1364 self.out_z = FPNumOut(width, False)
1365
1366 def setup(self, m, in_z):
1367 """ links module to inputs and outputs
1368 """
1369 m.submodules.pack = self
1370 m.d.comb += self.in_z.eq(in_z)
1371
1372 def elaborate(self, platform):
1373 m = Module()
1374 m.submodules.pack_in_z = self.in_z
1375 with m.If(self.in_z.is_overflowed):
1376 m.d.comb += self.out_z.inf(self.in_z.s)
1377 with m.Else():
1378 m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
1379 return m
1380
1381
1382 class FPPack(FPState, FPID):
1383
1384 def __init__(self, width, id_wid):
1385 FPState.__init__(self, "pack")
1386 FPID.__init__(self, id_wid)
1387 self.mod = FPPackMod(width)
1388 self.out_z = FPNumOut(width, False)
1389
1390 def setup(self, m, in_z, in_mid):
1391 """ links module to inputs and outputs
1392 """
1393 self.mod.setup(m, in_z)
1394 if self.in_mid is not None:
1395 m.d.comb += self.in_mid.eq(in_mid)
1396
1397 def action(self, m):
1398 self.idsync(m)
1399 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1400 m.next = "pack_put_z"
1401
1402
1403 class FPPutZ(FPState):
1404
1405 def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1406 FPState.__init__(self, state)
1407 if to_state is None:
1408 to_state = "get_ops"
1409 self.to_state = to_state
1410 self.in_z = in_z
1411 self.out_z = out_z
1412 self.in_mid = in_mid
1413 self.out_mid = out_mid
1414
1415 def action(self, m):
1416 if self.in_mid is not None:
1417 m.d.sync += self.out_mid.eq(self.in_mid)
1418 m.d.sync += [
1419 self.out_z.v.eq(self.in_z.v)
1420 ]
1421 with m.If(self.out_z.stb & self.out_z.ack):
1422 m.d.sync += self.out_z.stb.eq(0)
1423 m.next = self.to_state
1424 with m.Else():
1425 m.d.sync += self.out_z.stb.eq(1)
1426
1427
1428 class FPPutZIdx(FPState):
1429
1430 def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1431 FPState.__init__(self, state)
1432 if to_state is None:
1433 to_state = "get_ops"
1434 self.to_state = to_state
1435 self.in_z = in_z
1436 self.out_zs = out_zs
1437 self.in_mid = in_mid
1438
1439 def action(self, m):
1440 outz_stb = Signal(reset_less=True)
1441 outz_ack = Signal(reset_less=True)
1442 m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1443 outz_ack.eq(self.out_zs[self.in_mid].ack),
1444 ]
1445 m.d.sync += [
1446 self.out_zs[self.in_mid].v.eq(self.in_z.v)
1447 ]
1448 with m.If(outz_stb & outz_ack):
1449 m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1450 m.next = self.to_state
1451 with m.Else():
1452 m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1453
1454
1455 class FPADDBaseMod(FPID):
1456
1457 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1458 """ IEEE754 FP Add
1459
1460 * width: bit-width of IEEE754. supported: 16, 32, 64
1461 * id_wid: an identifier that is sync-connected to the input
1462 * single_cycle: True indicates each stage to complete in 1 clock
1463 * compact: True indicates a reduced number of stages
1464 """
1465 FPID.__init__(self, id_wid)
1466 self.width = width
1467 self.single_cycle = single_cycle
1468 self.compact = compact
1469
1470 self.in_t = Trigger()
1471 self.in_a = Signal(width)
1472 self.in_b = Signal(width)
1473 self.out_z = FPOp(width)
1474
1475 self.states = []
1476
1477 def add_state(self, state):
1478 self.states.append(state)
1479 return state
1480
1481 def get_fragment(self, platform=None):
1482 """ creates the HDL code-fragment for FPAdd
1483 """
1484 m = Module()
1485 m.submodules.out_z = self.out_z
1486 m.submodules.in_t = self.in_t
1487 if self.compact:
1488 self.get_compact_fragment(m, platform)
1489 else:
1490 self.get_longer_fragment(m, platform)
1491
1492 with m.FSM() as fsm:
1493
1494 for state in self.states:
1495 with m.State(state.state_from):
1496 state.action(m)
1497
1498 return m
1499
1500 def get_longer_fragment(self, m, platform=None):
1501
1502 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1503 self.in_a, self.in_b, self.width))
1504 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1505 a = get.out_op1
1506 b = get.out_op2
1507
1508 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1509 sc.setup(m, a, b, self.in_mid)
1510
1511 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1512 dn.setup(m, a, b, sc.in_mid)
1513
1514 if self.single_cycle:
1515 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1516 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1517 else:
1518 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1519 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1520
1521 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1522 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1523
1524 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1525 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1526
1527 if self.single_cycle:
1528 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1529 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1530 else:
1531 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1532 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1533
1534 rn = self.add_state(FPRound(self.width, self.id_wid))
1535 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1536
1537 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1538 cor.setup(m, rn.out_z, rn.in_mid)
1539
1540 pa = self.add_state(FPPack(self.width, self.id_wid))
1541 pa.setup(m, cor.out_z, rn.in_mid)
1542
1543 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1544 pa.in_mid, self.out_mid))
1545
1546 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1547 pa.in_mid, self.out_mid))
1548
1549 def get_compact_fragment(self, m, platform=None):
1550
1551 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1552 self.in_a, self.in_b, self.width))
1553 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1554 a = get.out_op1
1555 b = get.out_op2
1556
1557 sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1558 sc.setup(m, a, b, self.in_mid)
1559
1560 alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1561 alm.setup(m, sc.o.a, sc.o.b, sc.in_mid)
1562
1563 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1564 n1.setup(m, alm.a1o.z, alm.a1o.of, alm.in_mid)
1565
1566 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
1567 n1.in_mid, self.out_mid))
1568
1569 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1570 sc.in_mid, self.out_mid))
1571
1572
1573 class FPADDBase(FPState, FPID):
1574
1575 def __init__(self, width, id_wid=None, single_cycle=False):
1576 """ IEEE754 FP Add
1577
1578 * width: bit-width of IEEE754. supported: 16, 32, 64
1579 * id_wid: an identifier that is sync-connected to the input
1580 * single_cycle: True indicates each stage to complete in 1 clock
1581 """
1582 FPID.__init__(self, id_wid)
1583 FPState.__init__(self, "fpadd")
1584 self.width = width
1585 self.single_cycle = single_cycle
1586 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1587
1588 self.in_t = Trigger()
1589 self.in_a = Signal(width)
1590 self.in_b = Signal(width)
1591 #self.out_z = FPOp(width)
1592
1593 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1594 self.in_accept = Signal(reset_less=True)
1595 self.add_stb = Signal(reset_less=True)
1596 self.add_ack = Signal(reset=0, reset_less=True)
1597
1598 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1599 self.out_z = out_z
1600 self.out_mid = out_mid
1601 m.d.comb += [self.in_a.eq(a),
1602 self.in_b.eq(b),
1603 self.mod.in_a.eq(self.in_a),
1604 self.mod.in_b.eq(self.in_b),
1605 self.in_mid.eq(in_mid),
1606 self.mod.in_mid.eq(self.in_mid),
1607 self.z_done.eq(self.mod.out_z.trigger),
1608 #self.add_stb.eq(add_stb),
1609 self.mod.in_t.stb.eq(self.in_t.stb),
1610 self.in_t.ack.eq(self.mod.in_t.ack),
1611 self.out_mid.eq(self.mod.out_mid),
1612 self.out_z.v.eq(self.mod.out_z.v),
1613 self.out_z.stb.eq(self.mod.out_z.stb),
1614 self.mod.out_z.ack.eq(self.out_z.ack),
1615 ]
1616
1617 m.d.sync += self.add_stb.eq(add_stb)
1618 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1619 m.d.sync += self.out_z.ack.eq(0) # likewise
1620 #m.d.sync += self.in_t.stb.eq(0)
1621
1622 m.submodules.fpadd = self.mod
1623
1624 def action(self, m):
1625
1626 # in_accept is set on incoming strobe HIGH and ack LOW.
1627 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1628
1629 #with m.If(self.in_t.ack):
1630 # m.d.sync += self.in_t.stb.eq(0)
1631 with m.If(~self.z_done):
1632 # not done: test for accepting an incoming operand pair
1633 with m.If(self.in_accept):
1634 m.d.sync += [
1635 self.add_ack.eq(1), # acknowledge receipt...
1636 self.in_t.stb.eq(1), # initiate add
1637 ]
1638 with m.Else():
1639 m.d.sync += [self.add_ack.eq(0),
1640 self.in_t.stb.eq(0),
1641 self.out_z.ack.eq(1),
1642 ]
1643 with m.Else():
1644 # done: acknowledge, and write out id and value
1645 m.d.sync += [self.add_ack.eq(1),
1646 self.in_t.stb.eq(0)
1647 ]
1648 m.next = "put_z"
1649
1650 return
1651
1652 if self.in_mid is not None:
1653 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1654
1655 m.d.sync += [
1656 self.out_z.v.eq(self.mod.out_z.v)
1657 ]
1658 # move to output state on detecting z ack
1659 with m.If(self.out_z.trigger):
1660 m.d.sync += self.out_z.stb.eq(0)
1661 m.next = "put_z"
1662 with m.Else():
1663 m.d.sync += self.out_z.stb.eq(1)
1664
1665 class ResArray:
1666 def __init__(self, width, id_wid):
1667 self.width = width
1668 self.id_wid = id_wid
1669 res = []
1670 for i in range(rs_sz):
1671 out_z = FPOp(width)
1672 out_z.name = "out_z_%d" % i
1673 res.append(out_z)
1674 self.res = Array(res)
1675 self.in_z = FPOp(width)
1676 self.in_mid = Signal(self.id_wid, reset_less=True)
1677
1678 def setup(self, m, in_z, in_mid):
1679 m.d.comb += [self.in_z.eq(in_z),
1680 self.in_mid.eq(in_mid)]
1681
1682 def get_fragment(self, platform=None):
1683 """ creates the HDL code-fragment for FPAdd
1684 """
1685 m = Module()
1686 m.submodules.res_in_z = self.in_z
1687 m.submodules += self.res
1688
1689 return m
1690
1691 def ports(self):
1692 res = []
1693 for z in self.res:
1694 res += z.ports()
1695 return res
1696
1697
1698 class FPADD(FPID):
1699 """ FPADD: stages as follows:
1700
1701 FPGetOp (a)
1702 |
1703 FPGetOp (b)
1704 |
1705 FPAddBase---> FPAddBaseMod
1706 | |
1707 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1708
1709 FPAddBase is tricky: it is both a stage and *has* stages.
1710 Connection to FPAddBaseMod therefore requires an in stb/ack
1711 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1712 needs to be the thing that raises the incoming stb.
1713 """
1714
1715 def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1716 """ IEEE754 FP Add
1717
1718 * width: bit-width of IEEE754. supported: 16, 32, 64
1719 * id_wid: an identifier that is sync-connected to the input
1720 * single_cycle: True indicates each stage to complete in 1 clock
1721 """
1722 self.width = width
1723 self.id_wid = id_wid
1724 self.single_cycle = single_cycle
1725
1726 #self.out_z = FPOp(width)
1727 self.ids = FPID(id_wid)
1728
1729 rs = []
1730 for i in range(rs_sz):
1731 in_a = FPOp(width)
1732 in_b = FPOp(width)
1733 in_a.name = "in_a_%d" % i
1734 in_b.name = "in_b_%d" % i
1735 rs.append((in_a, in_b))
1736 self.rs = Array(rs)
1737
1738 res = []
1739 for i in range(rs_sz):
1740 out_z = FPOp(width)
1741 out_z.name = "out_z_%d" % i
1742 res.append(out_z)
1743 self.res = Array(res)
1744
1745 self.states = []
1746
1747 def add_state(self, state):
1748 self.states.append(state)
1749 return state
1750
1751 def get_fragment(self, platform=None):
1752 """ creates the HDL code-fragment for FPAdd
1753 """
1754 m = Module()
1755 m.submodules += self.rs
1756
1757 in_a = self.rs[0][0]
1758 in_b = self.rs[0][1]
1759
1760 out_z = FPOp(self.width)
1761 out_mid = Signal(self.id_wid, reset_less=True)
1762 m.submodules.out_z = out_z
1763
1764 geta = self.add_state(FPGetOp("get_a", "get_b",
1765 in_a, self.width))
1766 geta.setup(m, in_a)
1767 a = geta.out_op
1768
1769 getb = self.add_state(FPGetOp("get_b", "fpadd",
1770 in_b, self.width))
1771 getb.setup(m, in_b)
1772 b = getb.out_op
1773
1774 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1775 ab = self.add_state(ab)
1776 ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1777 out_z, out_mid)
1778
1779 pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1780 out_mid, "get_a"))
1781
1782 with m.FSM() as fsm:
1783
1784 for state in self.states:
1785 with m.State(state.state_from):
1786 state.action(m)
1787
1788 return m
1789
1790
1791 if __name__ == "__main__":
1792 if True:
1793 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1794 main(alu, ports=alu.rs[0][0].ports() + \
1795 alu.rs[0][1].ports() + \
1796 alu.res[0].ports() + \
1797 [alu.ids.in_mid, alu.ids.out_mid])
1798 else:
1799 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1800 main(alu, ports=[alu.in_a, alu.in_b] + \
1801 alu.in_t.ports() + \
1802 alu.out_z.ports() + \
1803 [alu.in_mid, alu.out_mid])
1804
1805
1806 # works... but don't use, just do "python fname.py convert -t v"
1807 #print (verilog.convert(alu, ports=[
1808 # ports=alu.in_a.ports() + \
1809 # alu.in_b.ports() + \
1810 # alu.out_z.ports())