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remove unneeded variable
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 #from fpbase import FPNumShiftMultiRight
13
14
15 class FPState(FPBase):
16 def __init__(self, state_from):
17 self.state_from = state_from
18
19 def set_inputs(self, inputs):
20 self.inputs = inputs
21 for k,v in inputs.items():
22 setattr(self, k, v)
23
24 def set_outputs(self, outputs):
25 self.outputs = outputs
26 for k,v in outputs.items():
27 setattr(self, k, v)
28
29
30 class FPGetSyncOpsMod:
31 def __init__(self, width, num_ops=2):
32 self.width = width
33 self.num_ops = num_ops
34 inops = []
35 outops = []
36 for i in range(num_ops):
37 inops.append(Signal(width, reset_less=True))
38 outops.append(Signal(width, reset_less=True))
39 self.in_op = inops
40 self.out_op = outops
41 self.stb = Signal(num_ops)
42 self.ack = Signal()
43 self.ready = Signal(reset_less=True)
44 self.out_decode = Signal(reset_less=True)
45
46 def elaborate(self, platform):
47 m = Module()
48 m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
49 m.d.comb += self.out_decode.eq(self.ack & self.ready)
50 with m.If(self.out_decode):
51 for i in range(self.num_ops):
52 m.d.comb += [
53 self.out_op[i].eq(self.in_op[i]),
54 ]
55 return m
56
57 def ports(self):
58 return self.in_op + self.out_op + [self.stb, self.ack]
59
60
61 class FPOps(Trigger):
62 def __init__(self, width, num_ops):
63 Trigger.__init__(self)
64 self.width = width
65 self.num_ops = num_ops
66
67 res = []
68 for i in range(num_ops):
69 res.append(Signal(width))
70 self.v = Array(res)
71
72 def ports(self):
73 res = []
74 for i in range(self.num_ops):
75 res.append(self.v[i])
76 res.append(self.ack)
77 res.append(self.stb)
78 return res
79
80
81 class InputGroup:
82 def __init__(self, width, num_ops=2, num_rows=4):
83 self.width = width
84 self.num_ops = num_ops
85 self.num_rows = num_rows
86 self.mmax = int(log(self.num_rows) / log(2))
87 self.rs = []
88 self.mid = Signal(self.mmax, reset_less=True) # multiplex id
89 for i in range(num_rows):
90 self.rs.append(FPGetSyncOpsMod(width, num_ops))
91 self.rs = Array(self.rs)
92
93 self.out_op = FPOps(width, num_ops)
94
95 def elaborate(self, platform):
96 m = Module()
97
98 pe = PriorityEncoder(self.num_rows)
99 m.submodules.selector = pe
100 m.submodules.out_op = self.out_op
101 m.submodules += self.rs
102
103 # connect priority encoder
104 in_ready = []
105 for i in range(self.num_rows):
106 in_ready.append(self.rs[i].ready)
107 m.d.comb += pe.i.eq(Cat(*in_ready))
108
109 active = Signal(reset_less=True)
110 out_en = Signal(reset_less=True)
111 m.d.comb += active.eq(~pe.n) # encoder active
112 m.d.comb += out_en.eq(active & self.out_op.trigger)
113
114 # encoder active: ack relevant input, record MID, pass output
115 with m.If(out_en):
116 rs = self.rs[pe.o]
117 m.d.sync += self.mid.eq(pe.o)
118 m.d.sync += rs.ack.eq(0)
119 m.d.sync += self.out_op.stb.eq(0)
120 for j in range(self.num_ops):
121 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
122 with m.Else():
123 m.d.sync += self.out_op.stb.eq(1)
124 # acks all default to zero
125 for i in range(self.num_rows):
126 m.d.sync += self.rs[i].ack.eq(1)
127
128 return m
129
130 def ports(self):
131 res = []
132 for i in range(self.num_rows):
133 inop = self.rs[i]
134 res += inop.in_op + [inop.stb]
135 return self.out_op.ports() + res + [self.mid]
136
137
138 class FPGetOpMod:
139 def __init__(self, width):
140 self.in_op = FPOp(width)
141 self.out_op = Signal(width)
142 self.out_decode = Signal(reset_less=True)
143
144 def elaborate(self, platform):
145 m = Module()
146 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
147 m.submodules.get_op_in = self.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m.If(self.out_decode):
150 m.d.comb += [
151 self.out_op.eq(self.in_op.v),
152 ]
153 return m
154
155
156 class FPGetOp(FPState):
157 """ gets operand
158 """
159
160 def __init__(self, in_state, out_state, in_op, width):
161 FPState.__init__(self, in_state)
162 self.out_state = out_state
163 self.mod = FPGetOpMod(width)
164 self.in_op = in_op
165 self.out_op = Signal(width)
166 self.out_decode = Signal(reset_less=True)
167
168 def setup(self, m, in_op):
169 """ links module to inputs and outputs
170 """
171 setattr(m.submodules, self.state_from, self.mod)
172 m.d.comb += self.mod.in_op.eq(in_op)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m.d.comb += self.out_decode.eq(self.mod.out_decode)
175
176 def action(self, m):
177 with m.If(self.out_decode):
178 m.next = self.out_state
179 m.d.sync += [
180 self.in_op.ack.eq(0),
181 self.out_op.eq(self.mod.out_op)
182 ]
183 with m.Else():
184 m.d.sync += self.in_op.ack.eq(1)
185
186
187 class FPGet2OpMod(Trigger):
188 def __init__(self, width):
189 Trigger.__init__(self)
190 self.in_op1 = Signal(width, reset_less=True)
191 self.in_op2 = Signal(width, reset_less=True)
192 self.out_op1 = FPNumIn(None, width)
193 self.out_op2 = FPNumIn(None, width)
194
195 def elaborate(self, platform):
196 m = Trigger.elaborate(self, platform)
197 #m.submodules.get_op_in = self.in_op
198 m.submodules.get_op1_out = self.out_op1
199 m.submodules.get_op2_out = self.out_op2
200 with m.If(self.trigger):
201 m.d.comb += [
202 self.out_op1.decode(self.in_op1),
203 self.out_op2.decode(self.in_op2),
204 ]
205 return m
206
207
208 class FPGet2Op(FPState):
209 """ gets operands
210 """
211
212 def __init__(self, in_state, out_state, in_op1, in_op2, width):
213 FPState.__init__(self, in_state)
214 self.out_state = out_state
215 self.mod = FPGet2OpMod(width)
216 self.in_op1 = in_op1
217 self.in_op2 = in_op2
218 self.out_op1 = FPNumIn(None, width)
219 self.out_op2 = FPNumIn(None, width)
220 self.in_stb = Signal(reset_less=True)
221 self.out_ack = Signal(reset_less=True)
222 self.out_decode = Signal(reset_less=True)
223
224 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
225 """ links module to inputs and outputs
226 """
227 m.submodules.get_ops = self.mod
228 m.d.comb += self.mod.in_op1.eq(in_op1)
229 m.d.comb += self.mod.in_op2.eq(in_op2)
230 m.d.comb += self.mod.stb.eq(in_stb)
231 m.d.comb += self.out_ack.eq(self.mod.ack)
232 m.d.comb += self.out_decode.eq(self.mod.trigger)
233 m.d.comb += in_ack.eq(self.mod.ack)
234
235 def action(self, m):
236 with m.If(self.out_decode):
237 m.next = self.out_state
238 m.d.sync += [
239 self.mod.ack.eq(0),
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self.out_op1.eq(self.mod.out_op1),
243 self.out_op2.eq(self.mod.out_op2)
244 ]
245 with m.Else():
246 m.d.sync += self.mod.ack.eq(1)
247
248 class FPNumBase2Ops:
249
250 def __init__(self, width, m_extra=True):
251 self.a = FPNumBase(width, m_extra)
252 self.b = FPNumBase(width, m_extra)
253
254 def eq(self, i):
255 return [self.a.eq(i.a), self.b.eq(i.b)]
256
257
258 class FPAddSpecialCasesMod:
259 """ special cases: NaNs, infs, zeros, denormalised
260 NOTE: some of these are unique to add. see "Special Operations"
261 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
262 """
263
264 def __init__(self, width):
265 self.width = width
266 self.i = self.ispec()
267 self.out_z = self.ospec()
268 self.out_do_z = Signal(reset_less=True)
269
270 def ispec(self):
271 return FPNumBase2Ops(self.width)
272
273 def ospec(self):
274 return FPNumOut(self.width, False)
275
276 def setup(self, m, in_a, in_b, out_do_z):
277 """ links module to inputs and outputs
278 """
279 m.submodules.specialcases = self
280 m.d.comb += self.i.a.eq(in_a)
281 m.d.comb += self.i.b.eq(in_b)
282 m.d.comb += out_do_z.eq(self.out_do_z)
283
284 def elaborate(self, platform):
285 m = Module()
286
287 m.submodules.sc_in_a = self.i.a
288 m.submodules.sc_in_b = self.i.b
289 m.submodules.sc_out_z = self.out_z
290
291 s_nomatch = Signal()
292 m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
293
294 m_match = Signal()
295 m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
296
297 # if a is NaN or b is NaN return NaN
298 with m.If(self.i.a.is_nan | self.i.b.is_nan):
299 m.d.comb += self.out_do_z.eq(1)
300 m.d.comb += self.out_z.nan(0)
301
302 # XXX WEIRDNESS for FP16 non-canonical NaN handling
303 # under review
304
305 ## if a is zero and b is NaN return -b
306 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
307 # m.d.comb += self.out_do_z.eq(1)
308 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
309
310 ## if b is zero and a is NaN return -a
311 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
312 # m.d.comb += self.out_do_z.eq(1)
313 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
314
315 ## if a is -zero and b is NaN return -b
316 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
317 # m.d.comb += self.out_do_z.eq(1)
318 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
319
320 ## if b is -zero and a is NaN return -a
321 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
322 # m.d.comb += self.out_do_z.eq(1)
323 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
324
325 # if a is inf return inf (or NaN)
326 with m.Elif(self.i.a.is_inf):
327 m.d.comb += self.out_do_z.eq(1)
328 m.d.comb += self.out_z.inf(self.i.a.s)
329 # if a is inf and signs don't match return NaN
330 with m.If(self.i.b.exp_128 & s_nomatch):
331 m.d.comb += self.out_z.nan(0)
332
333 # if b is inf return inf
334 with m.Elif(self.i.b.is_inf):
335 m.d.comb += self.out_do_z.eq(1)
336 m.d.comb += self.out_z.inf(self.i.b.s)
337
338 # if a is zero and b zero return signed-a/b
339 with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
340 m.d.comb += self.out_do_z.eq(1)
341 m.d.comb += self.out_z.create(self.i.a.s & self.i.b.s,
342 self.i.b.e,
343 self.i.b.m[3:-1])
344
345 # if a is zero return b
346 with m.Elif(self.i.a.is_zero):
347 m.d.comb += self.out_do_z.eq(1)
348 m.d.comb += self.out_z.create(self.i.b.s, self.i.b.e,
349 self.i.b.m[3:-1])
350
351 # if b is zero return a
352 with m.Elif(self.i.b.is_zero):
353 m.d.comb += self.out_do_z.eq(1)
354 m.d.comb += self.out_z.create(self.i.a.s, self.i.a.e,
355 self.i.a.m[3:-1])
356
357 # if a equal to -b return zero (+ve zero)
358 with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
359 m.d.comb += self.out_do_z.eq(1)
360 m.d.comb += self.out_z.zero(0)
361
362 # Denormalised Number checks
363 with m.Else():
364 m.d.comb += self.out_do_z.eq(0)
365
366 return m
367
368
369 class FPID:
370 def __init__(self, id_wid):
371 self.id_wid = id_wid
372 if self.id_wid:
373 self.in_mid = Signal(id_wid, reset_less=True)
374 self.out_mid = Signal(id_wid, reset_less=True)
375 else:
376 self.in_mid = None
377 self.out_mid = None
378
379 def idsync(self, m):
380 if self.id_wid is not None:
381 m.d.sync += self.out_mid.eq(self.in_mid)
382
383
384 class FPAddSpecialCases(FPState, FPID):
385 """ special cases: NaNs, infs, zeros, denormalised
386 NOTE: some of these are unique to add. see "Special Operations"
387 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
388 """
389
390 def __init__(self, width, id_wid):
391 FPState.__init__(self, "special_cases")
392 FPID.__init__(self, id_wid)
393 self.mod = FPAddSpecialCasesMod(width)
394 self.out_z = self.mod.ospec()
395 self.out_do_z = Signal(reset_less=True)
396
397 def setup(self, m, in_a, in_b, in_mid):
398 """ links module to inputs and outputs
399 """
400 self.mod.setup(m, in_a, in_b, self.out_do_z)
401 if self.in_mid is not None:
402 m.d.comb += self.in_mid.eq(in_mid)
403
404 def action(self, m):
405 self.idsync(m)
406 with m.If(self.out_do_z):
407 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
408 m.next = "put_z"
409 with m.Else():
410 m.next = "denormalise"
411
412
413 class FPAddSpecialCasesDeNorm(FPState, FPID):
414 """ special cases: NaNs, infs, zeros, denormalised
415 NOTE: some of these are unique to add. see "Special Operations"
416 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
417 """
418
419 def __init__(self, width, id_wid):
420 FPState.__init__(self, "special_cases")
421 FPID.__init__(self, id_wid)
422 self.smod = FPAddSpecialCasesMod(width)
423 self.out_z = self.smod.ospec()
424 self.out_do_z = Signal(reset_less=True)
425
426 self.dmod = FPAddDeNormMod(width)
427 self.o = self.dmod.ospec()
428
429 def setup(self, m, in_a, in_b, in_mid):
430 """ links module to inputs and outputs
431 """
432 self.smod.setup(m, in_a, in_b, self.out_do_z)
433 self.dmod.setup(m, in_a, in_b)
434 if self.in_mid is not None:
435 m.d.comb += self.in_mid.eq(in_mid)
436
437 def action(self, m):
438 self.idsync(m)
439 with m.If(self.out_do_z):
440 m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
441 m.next = "put_z"
442 with m.Else():
443 m.next = "align"
444 m.d.sync += self.o.a.eq(self.dmod.o.a)
445 m.d.sync += self.o.b.eq(self.dmod.o.b)
446
447
448 class FPAddDeNormMod(FPState):
449
450 def __init__(self, width):
451 self.width = width
452 self.i = self.ispec()
453 self.o = self.ospec()
454
455 def ispec(self):
456 return FPNumBase2Ops(self.width)
457
458 def ospec(self):
459 return FPNumBase2Ops(self.width)
460
461 def setup(self, m, in_a, in_b):
462 """ links module to inputs and outputs
463 """
464 m.submodules.denormalise = self
465 m.d.comb += self.i.a.eq(in_a)
466 m.d.comb += self.i.b.eq(in_b)
467
468 def elaborate(self, platform):
469 m = Module()
470 m.submodules.denorm_in_a = self.i.a
471 m.submodules.denorm_in_b = self.i.b
472 m.submodules.denorm_out_a = self.o.a
473 m.submodules.denorm_out_b = self.o.b
474 # hmmm, don't like repeating identical code
475 m.d.comb += self.o.a.eq(self.i.a)
476 with m.If(self.i.a.exp_n127):
477 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
478 with m.Else():
479 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
480
481 m.d.comb += self.o.b.eq(self.i.b)
482 with m.If(self.i.b.exp_n127):
483 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
484 with m.Else():
485 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
486
487 return m
488
489
490 class FPAddDeNorm(FPState, FPID):
491
492 def __init__(self, width, id_wid):
493 FPState.__init__(self, "denormalise")
494 FPID.__init__(self, id_wid)
495 self.mod = FPAddDeNormMod(width)
496 self.out_a = FPNumBase(width)
497 self.out_b = FPNumBase(width)
498
499 def setup(self, m, in_a, in_b, in_mid):
500 """ links module to inputs and outputs
501 """
502 self.mod.setup(m, in_a, in_b)
503 if self.in_mid is not None:
504 m.d.comb += self.in_mid.eq(in_mid)
505
506 def action(self, m):
507 self.idsync(m)
508 # Denormalised Number checks
509 m.next = "align"
510 m.d.sync += self.out_a.eq(self.mod.out_a)
511 m.d.sync += self.out_b.eq(self.mod.out_b)
512
513
514 class FPAddAlignMultiMod(FPState):
515
516 def __init__(self, width):
517 self.in_a = FPNumBase(width)
518 self.in_b = FPNumBase(width)
519 self.out_a = FPNumIn(None, width)
520 self.out_b = FPNumIn(None, width)
521 self.exp_eq = Signal(reset_less=True)
522
523 def elaborate(self, platform):
524 # This one however (single-cycle) will do the shift
525 # in one go.
526
527 m = Module()
528
529 m.submodules.align_in_a = self.in_a
530 m.submodules.align_in_b = self.in_b
531 m.submodules.align_out_a = self.out_a
532 m.submodules.align_out_b = self.out_b
533
534 # NOTE: this does *not* do single-cycle multi-shifting,
535 # it *STAYS* in the align state until exponents match
536
537 # exponent of a greater than b: shift b down
538 m.d.comb += self.exp_eq.eq(0)
539 m.d.comb += self.out_a.eq(self.in_a)
540 m.d.comb += self.out_b.eq(self.in_b)
541 agtb = Signal(reset_less=True)
542 altb = Signal(reset_less=True)
543 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
544 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
545 with m.If(agtb):
546 m.d.comb += self.out_b.shift_down(self.in_b)
547 # exponent of b greater than a: shift a down
548 with m.Elif(altb):
549 m.d.comb += self.out_a.shift_down(self.in_a)
550 # exponents equal: move to next stage.
551 with m.Else():
552 m.d.comb += self.exp_eq.eq(1)
553 return m
554
555
556 class FPAddAlignMulti(FPState, FPID):
557
558 def __init__(self, width, id_wid):
559 FPID.__init__(self, id_wid)
560 FPState.__init__(self, "align")
561 self.mod = FPAddAlignMultiMod(width)
562 self.out_a = FPNumIn(None, width)
563 self.out_b = FPNumIn(None, width)
564 self.exp_eq = Signal(reset_less=True)
565
566 def setup(self, m, in_a, in_b, in_mid):
567 """ links module to inputs and outputs
568 """
569 m.submodules.align = self.mod
570 m.d.comb += self.mod.in_a.eq(in_a)
571 m.d.comb += self.mod.in_b.eq(in_b)
572 #m.d.comb += self.out_a.eq(self.mod.out_a)
573 #m.d.comb += self.out_b.eq(self.mod.out_b)
574 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
575 if self.in_mid is not None:
576 m.d.comb += self.in_mid.eq(in_mid)
577
578 def action(self, m):
579 self.idsync(m)
580 m.d.sync += self.out_a.eq(self.mod.out_a)
581 m.d.sync += self.out_b.eq(self.mod.out_b)
582 with m.If(self.exp_eq):
583 m.next = "add_0"
584
585
586 class FPNumIn2Ops:
587
588 def __init__(self, width):
589 self.a = FPNumIn(None, width)
590 self.b = FPNumIn(None, width)
591
592 def eq(self, i):
593 return [self.a.eq(i.a), self.b.eq(i.b)]
594
595
596 class FPAddAlignSingleMod:
597
598 def __init__(self, width):
599 self.width = width
600 self.i = self.ispec()
601 self.o = self.ospec()
602
603 def ispec(self):
604 return FPNumBase2Ops(self.width)
605
606 def ospec(self):
607 return FPNumIn2Ops(self.width)
608
609 def setup(self, m, in_a, in_b):
610 """ links module to inputs and outputs
611 """
612 m.submodules.align = self
613 m.d.comb += self.i.a.eq(in_a)
614 m.d.comb += self.i.b.eq(in_b)
615
616 def elaborate(self, platform):
617 """ Aligns A against B or B against A, depending on which has the
618 greater exponent. This is done in a *single* cycle using
619 variable-width bit-shift
620
621 the shifter used here is quite expensive in terms of gates.
622 Mux A or B in (and out) into temporaries, as only one of them
623 needs to be aligned against the other
624 """
625 m = Module()
626
627 m.submodules.align_in_a = self.i.a
628 m.submodules.align_in_b = self.i.b
629 m.submodules.align_out_a = self.o.a
630 m.submodules.align_out_b = self.o.b
631
632 # temporary (muxed) input and output to be shifted
633 t_inp = FPNumBase(self.width)
634 t_out = FPNumIn(None, self.width)
635 espec = (len(self.i.a.e), True)
636 msr = MultiShiftRMerge(self.i.a.m_width, espec)
637 m.submodules.align_t_in = t_inp
638 m.submodules.align_t_out = t_out
639 m.submodules.multishift_r = msr
640
641 ediff = Signal(espec, reset_less=True)
642 ediffr = Signal(espec, reset_less=True)
643 tdiff = Signal(espec, reset_less=True)
644 elz = Signal(reset_less=True)
645 egz = Signal(reset_less=True)
646
647 # connect multi-shifter to t_inp/out mantissa (and tdiff)
648 m.d.comb += msr.inp.eq(t_inp.m)
649 m.d.comb += msr.diff.eq(tdiff)
650 m.d.comb += t_out.m.eq(msr.m)
651 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
652 m.d.comb += t_out.s.eq(t_inp.s)
653
654 m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
655 m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
656 m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
657 m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
658
659 # default: A-exp == B-exp, A and B untouched (fall through)
660 m.d.comb += self.o.a.eq(self.i.a)
661 m.d.comb += self.o.b.eq(self.i.b)
662 # only one shifter (muxed)
663 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
664 # exponent of a greater than b: shift b down
665 with m.If(egz):
666 m.d.comb += [t_inp.eq(self.i.b),
667 tdiff.eq(ediff),
668 self.o.b.eq(t_out),
669 self.o.b.s.eq(self.i.b.s), # whoops forgot sign
670 ]
671 # exponent of b greater than a: shift a down
672 with m.Elif(elz):
673 m.d.comb += [t_inp.eq(self.i.a),
674 tdiff.eq(ediffr),
675 self.o.a.eq(t_out),
676 self.o.a.s.eq(self.i.a.s), # whoops forgot sign
677 ]
678 return m
679
680
681 class FPAddAlignSingle(FPState, FPID):
682
683 def __init__(self, width, id_wid):
684 FPState.__init__(self, "align")
685 FPID.__init__(self, id_wid)
686 self.mod = FPAddAlignSingleMod(width)
687 self.out_a = FPNumIn(None, width)
688 self.out_b = FPNumIn(None, width)
689
690 def setup(self, m, in_a, in_b, in_mid):
691 """ links module to inputs and outputs
692 """
693 self.mod.setup(m, in_a, in_b)
694 if self.in_mid is not None:
695 m.d.comb += self.in_mid.eq(in_mid)
696
697 def action(self, m):
698 self.idsync(m)
699 # NOTE: could be done as comb
700 m.d.sync += self.out_a.eq(self.mod.out_a)
701 m.d.sync += self.out_b.eq(self.mod.out_b)
702 m.next = "add_0"
703
704
705 class FPAddAlignSingleAdd(FPState, FPID):
706
707 def __init__(self, width, id_wid):
708 FPState.__init__(self, "align")
709 FPID.__init__(self, id_wid)
710 self.mod = FPAddAlignSingleMod(width)
711 self.o = self.mod.ospec()
712
713 self.a0mod = FPAddStage0Mod(width)
714 self.a0_out_z = FPNumBase(width, False)
715 self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
716 self.a0_out_z = FPNumBase(width, False)
717
718 self.a1mod = FPAddStage1Mod(width)
719 self.out_z = FPNumBase(width, False)
720 self.out_of = Overflow()
721
722 def setup(self, m, in_a, in_b, in_mid):
723 """ links module to inputs and outputs
724 """
725 self.mod.setup(m, in_a, in_b)
726 m.d.comb += self.o.eq(self.mod.o)
727
728 self.a0mod.setup(m, self.o.a, self.o.b)
729 m.d.comb += self.a0_out_z.eq(self.a0mod.o.z)
730 m.d.comb += self.out_tot.eq(self.a0mod.o.tot)
731
732 self.a1mod.setup(m, self.out_tot, self.a0_out_z)
733
734 if self.in_mid is not None:
735 m.d.comb += self.in_mid.eq(in_mid)
736
737 def action(self, m):
738 self.idsync(m)
739 m.d.sync += self.out_of.eq(self.a1mod.o.of)
740 m.d.sync += self.out_z.eq(self.a1mod.o.z)
741 m.next = "normalise_1"
742
743
744 class FPAddStage0Data:
745
746 def __init__(self, width):
747 self.z = FPNumBase(width, False)
748 self.tot = Signal(self.z.m_width + 4, reset_less=True)
749
750 def eq(self, i):
751 return [self.z.eq(i.z), self.tot.eq(i.tot)]
752
753
754 class FPAddStage0Mod:
755
756 def __init__(self, width):
757 self.width = width
758 self.i = self.ispec()
759 self.o = self.ospec()
760
761 def ispec(self):
762 return FPNumBase2Ops(self.width)
763
764 def ospec(self):
765 return FPAddStage0Data(self.width)
766
767 def setup(self, m, in_a, in_b):
768 """ links module to inputs and outputs
769 """
770 m.submodules.add0 = self
771 m.d.comb += self.i.a.eq(in_a)
772 m.d.comb += self.i.b.eq(in_b)
773
774 def elaborate(self, platform):
775 m = Module()
776 m.submodules.add0_in_a = self.i.a
777 m.submodules.add0_in_b = self.i.b
778 m.submodules.add0_out_z = self.o.z
779
780 m.d.comb += self.o.z.e.eq(self.i.a.e)
781
782 # store intermediate tests (and zero-extended mantissas)
783 seq = Signal(reset_less=True)
784 mge = Signal(reset_less=True)
785 am0 = Signal(len(self.i.a.m)+1, reset_less=True)
786 bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
787 m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
788 mge.eq(self.i.a.m >= self.i.b.m),
789 am0.eq(Cat(self.i.a.m, 0)),
790 bm0.eq(Cat(self.i.b.m, 0))
791 ]
792 # same-sign (both negative or both positive) add mantissas
793 with m.If(seq):
794 m.d.comb += [
795 self.o.tot.eq(am0 + bm0),
796 self.o.z.s.eq(self.i.a.s)
797 ]
798 # a mantissa greater than b, use a
799 with m.Elif(mge):
800 m.d.comb += [
801 self.o.tot.eq(am0 - bm0),
802 self.o.z.s.eq(self.i.a.s)
803 ]
804 # b mantissa greater than a, use b
805 with m.Else():
806 m.d.comb += [
807 self.o.tot.eq(bm0 - am0),
808 self.o.z.s.eq(self.i.b.s)
809 ]
810 return m
811
812
813 class FPAddStage0(FPState, FPID):
814 """ First stage of add. covers same-sign (add) and subtract
815 special-casing when mantissas are greater or equal, to
816 give greatest accuracy.
817 """
818
819 def __init__(self, width, id_wid):
820 FPState.__init__(self, "add_0")
821 FPID.__init__(self, id_wid)
822 self.mod = FPAddStage0Mod(width)
823 self.o = self.mod.ospec()
824
825 def setup(self, m, in_a, in_b, in_mid):
826 """ links module to inputs and outputs
827 """
828 self.mod.setup(m, in_a, in_b)
829 if self.in_mid is not None:
830 m.d.comb += self.in_mid.eq(in_mid)
831
832 def action(self, m):
833 self.idsync(m)
834 # NOTE: these could be done as combinatorial (merge add0+add1)
835 m.d.sync += self.o.eq(self.mod.o)
836 m.next = "add_1"
837
838
839 class FPAddStage1Data:
840
841 def __init__(self, width):
842 self.z = FPNumBase(width, False)
843 self.of = Overflow()
844
845 def eq(self, i):
846 return [self.z.eq(i.z), self.of.eq(i.of)]
847
848
849
850 class FPAddStage1Mod(FPState):
851 """ Second stage of add: preparation for normalisation.
852 detects when tot sum is too big (tot[27] is kinda a carry bit)
853 """
854
855 def __init__(self, width):
856 self.width = width
857 self.i = self.ispec()
858 self.o = self.ospec()
859
860 def ispec(self):
861 return FPAddStage0Data(self.width)
862
863 def ospec(self):
864 return FPAddStage1Data(self.width)
865
866 def setup(self, m, in_tot, in_z):
867 """ links module to inputs and outputs
868 """
869 m.submodules.add1 = self
870 m.submodules.add1_out_overflow = self.o.of
871
872 m.d.comb += self.i.z.eq(in_z)
873 m.d.comb += self.i.tot.eq(in_tot)
874
875 def elaborate(self, platform):
876 m = Module()
877 #m.submodules.norm1_in_overflow = self.in_of
878 #m.submodules.norm1_out_overflow = self.out_of
879 #m.submodules.norm1_in_z = self.in_z
880 #m.submodules.norm1_out_z = self.out_z
881 m.d.comb += self.o.z.eq(self.i.z)
882 # tot[-1] (MSB) gets set when the sum overflows. shift result down
883 with m.If(self.i.tot[-1]):
884 m.d.comb += [
885 self.o.z.m.eq(self.i.tot[4:]),
886 self.o.of.m0.eq(self.i.tot[4]),
887 self.o.of.guard.eq(self.i.tot[3]),
888 self.o.of.round_bit.eq(self.i.tot[2]),
889 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
890 self.o.z.e.eq(self.i.z.e + 1)
891 ]
892 # tot[-1] (MSB) zero case
893 with m.Else():
894 m.d.comb += [
895 self.o.z.m.eq(self.i.tot[3:]),
896 self.o.of.m0.eq(self.i.tot[3]),
897 self.o.of.guard.eq(self.i.tot[2]),
898 self.o.of.round_bit.eq(self.i.tot[1]),
899 self.o.of.sticky.eq(self.i.tot[0])
900 ]
901 return m
902
903
904 class FPAddStage1(FPState, FPID):
905
906 def __init__(self, width, id_wid):
907 FPState.__init__(self, "add_1")
908 FPID.__init__(self, id_wid)
909 self.mod = FPAddStage1Mod(width)
910 self.out_z = FPNumBase(width, False)
911 self.out_of = Overflow()
912 self.norm_stb = Signal()
913
914 def setup(self, m, in_tot, in_z, in_mid):
915 """ links module to inputs and outputs
916 """
917 self.mod.setup(m, in_tot, in_z)
918
919 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
920
921 if self.in_mid is not None:
922 m.d.comb += self.in_mid.eq(in_mid)
923
924 def action(self, m):
925 self.idsync(m)
926 m.d.sync += self.out_of.eq(self.mod.out_of)
927 m.d.sync += self.out_z.eq(self.mod.out_z)
928 m.d.sync += self.norm_stb.eq(1)
929 m.next = "normalise_1"
930
931
932 class FPNormaliseModSingle:
933
934 def __init__(self, width):
935 self.width = width
936 self.in_z = FPNumBase(width, False)
937 self.out_z = FPNumBase(width, False)
938
939 def setup(self, m, in_z, out_z, modname):
940 """ links module to inputs and outputs
941 """
942 m.submodules.normalise = self
943 m.d.comb += self.in_z.eq(in_z)
944 m.d.comb += out_z.eq(self.out_z)
945
946 def elaborate(self, platform):
947 m = Module()
948
949 mwid = self.out_z.m_width+2
950 pe = PriorityEncoder(mwid)
951 m.submodules.norm_pe = pe
952
953 m.submodules.norm1_out_z = self.out_z
954 m.submodules.norm1_in_z = self.in_z
955
956 in_z = FPNumBase(self.width, False)
957 in_of = Overflow()
958 m.submodules.norm1_insel_z = in_z
959 m.submodules.norm1_insel_overflow = in_of
960
961 espec = (len(in_z.e), True)
962 ediff_n126 = Signal(espec, reset_less=True)
963 msr = MultiShiftRMerge(mwid, espec)
964 m.submodules.multishift_r = msr
965
966 m.d.comb += in_z.eq(self.in_z)
967 m.d.comb += in_of.eq(self.in_of)
968 # initialise out from in (overridden below)
969 m.d.comb += self.out_z.eq(in_z)
970 m.d.comb += self.out_of.eq(in_of)
971 # normalisation increase/decrease conditions
972 decrease = Signal(reset_less=True)
973 m.d.comb += decrease.eq(in_z.m_msbzero)
974 # decrease exponent
975 with m.If(decrease):
976 # *sigh* not entirely obvious: count leading zeros (clz)
977 # with a PriorityEncoder: to find from the MSB
978 # we reverse the order of the bits.
979 temp_m = Signal(mwid, reset_less=True)
980 temp_s = Signal(mwid+1, reset_less=True)
981 clz = Signal((len(in_z.e), True), reset_less=True)
982 m.d.comb += [
983 # cat round and guard bits back into the mantissa
984 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
985 pe.i.eq(temp_m[::-1]), # inverted
986 clz.eq(pe.o), # count zeros from MSB down
987 temp_s.eq(temp_m << clz), # shift mantissa UP
988 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
989 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
990 ]
991
992 return m
993
994
995 class FPNorm1ModSingle:
996
997 def __init__(self, width):
998 self.width = width
999 self.out_norm = Signal(reset_less=True)
1000 self.in_z = FPNumBase(width, False)
1001 self.in_of = Overflow()
1002 self.out_z = FPNumBase(width, False)
1003 self.out_of = Overflow()
1004
1005 def setup(self, m, in_z, in_of, out_z):
1006 """ links module to inputs and outputs
1007 """
1008 m.submodules.normalise_1 = self
1009
1010 m.d.comb += self.in_z.eq(in_z)
1011 m.d.comb += self.in_of.eq(in_of)
1012
1013 m.d.comb += out_z.eq(self.out_z)
1014
1015 def elaborate(self, platform):
1016 m = Module()
1017
1018 mwid = self.out_z.m_width+2
1019 pe = PriorityEncoder(mwid)
1020 m.submodules.norm_pe = pe
1021
1022 m.submodules.norm1_out_z = self.out_z
1023 m.submodules.norm1_out_overflow = self.out_of
1024 m.submodules.norm1_in_z = self.in_z
1025 m.submodules.norm1_in_overflow = self.in_of
1026
1027 in_z = FPNumBase(self.width, False)
1028 in_of = Overflow()
1029 m.submodules.norm1_insel_z = in_z
1030 m.submodules.norm1_insel_overflow = in_of
1031
1032 espec = (len(in_z.e), True)
1033 ediff_n126 = Signal(espec, reset_less=True)
1034 msr = MultiShiftRMerge(mwid, espec)
1035 m.submodules.multishift_r = msr
1036
1037 m.d.comb += in_z.eq(self.in_z)
1038 m.d.comb += in_of.eq(self.in_of)
1039 # initialise out from in (overridden below)
1040 m.d.comb += self.out_z.eq(in_z)
1041 m.d.comb += self.out_of.eq(in_of)
1042 # normalisation increase/decrease conditions
1043 decrease = Signal(reset_less=True)
1044 increase = Signal(reset_less=True)
1045 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1046 m.d.comb += increase.eq(in_z.exp_lt_n126)
1047 # decrease exponent
1048 with m.If(decrease):
1049 # *sigh* not entirely obvious: count leading zeros (clz)
1050 # with a PriorityEncoder: to find from the MSB
1051 # we reverse the order of the bits.
1052 temp_m = Signal(mwid, reset_less=True)
1053 temp_s = Signal(mwid+1, reset_less=True)
1054 clz = Signal((len(in_z.e), True), reset_less=True)
1055 # make sure that the amount to decrease by does NOT
1056 # go below the minimum non-INF/NaN exponent
1057 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
1058 in_z.exp_sub_n126)
1059 m.d.comb += [
1060 # cat round and guard bits back into the mantissa
1061 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1062 pe.i.eq(temp_m[::-1]), # inverted
1063 clz.eq(limclz), # count zeros from MSB down
1064 temp_s.eq(temp_m << clz), # shift mantissa UP
1065 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
1066 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
1067 self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
1068 # overflow in bits 0..1: got shifted too (leave sticky)
1069 self.out_of.guard.eq(temp_s[1]), # guard
1070 self.out_of.round_bit.eq(temp_s[0]), # round
1071 ]
1072 # increase exponent
1073 with m.Elif(increase):
1074 temp_m = Signal(mwid+1, reset_less=True)
1075 m.d.comb += [
1076 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
1077 in_z.m)),
1078 ediff_n126.eq(in_z.N126 - in_z.e),
1079 # connect multi-shifter to inp/out mantissa (and ediff)
1080 msr.inp.eq(temp_m),
1081 msr.diff.eq(ediff_n126),
1082 self.out_z.m.eq(msr.m[3:]),
1083 self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
1084 # overflow in bits 0..1: got shifted too (leave sticky)
1085 self.out_of.guard.eq(temp_s[2]), # guard
1086 self.out_of.round_bit.eq(temp_s[1]), # round
1087 self.out_of.sticky.eq(temp_s[0]), # sticky
1088 self.out_z.e.eq(in_z.e + ediff_n126),
1089 ]
1090
1091 return m
1092
1093
1094 class FPNorm1ModMulti:
1095
1096 def __init__(self, width, single_cycle=True):
1097 self.width = width
1098 self.in_select = Signal(reset_less=True)
1099 self.in_z = FPNumBase(width, False)
1100 self.in_of = Overflow()
1101 self.temp_z = FPNumBase(width, False)
1102 self.temp_of = Overflow()
1103 self.out_z = FPNumBase(width, False)
1104 self.out_of = Overflow()
1105
1106 def elaborate(self, platform):
1107 m = Module()
1108
1109 m.submodules.norm1_out_z = self.out_z
1110 m.submodules.norm1_out_overflow = self.out_of
1111 m.submodules.norm1_temp_z = self.temp_z
1112 m.submodules.norm1_temp_of = self.temp_of
1113 m.submodules.norm1_in_z = self.in_z
1114 m.submodules.norm1_in_overflow = self.in_of
1115
1116 in_z = FPNumBase(self.width, False)
1117 in_of = Overflow()
1118 m.submodules.norm1_insel_z = in_z
1119 m.submodules.norm1_insel_overflow = in_of
1120
1121 # select which of temp or in z/of to use
1122 with m.If(self.in_select):
1123 m.d.comb += in_z.eq(self.in_z)
1124 m.d.comb += in_of.eq(self.in_of)
1125 with m.Else():
1126 m.d.comb += in_z.eq(self.temp_z)
1127 m.d.comb += in_of.eq(self.temp_of)
1128 # initialise out from in (overridden below)
1129 m.d.comb += self.out_z.eq(in_z)
1130 m.d.comb += self.out_of.eq(in_of)
1131 # normalisation increase/decrease conditions
1132 decrease = Signal(reset_less=True)
1133 increase = Signal(reset_less=True)
1134 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1135 m.d.comb += increase.eq(in_z.exp_lt_n126)
1136 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1137 # decrease exponent
1138 with m.If(decrease):
1139 m.d.comb += [
1140 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
1141 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1142 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1143 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1144 self.out_of.round_bit.eq(0), # reset round bit
1145 self.out_of.m0.eq(in_of.guard),
1146 ]
1147 # increase exponent
1148 with m.Elif(increase):
1149 m.d.comb += [
1150 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
1151 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1152 self.out_of.guard.eq(in_z.m[0]),
1153 self.out_of.m0.eq(in_z.m[1]),
1154 self.out_of.round_bit.eq(in_of.guard),
1155 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1156 ]
1157
1158 return m
1159
1160
1161 class FPNorm1Single(FPState, FPID):
1162
1163 def __init__(self, width, id_wid, single_cycle=True):
1164 FPID.__init__(self, id_wid)
1165 FPState.__init__(self, "normalise_1")
1166 self.mod = FPNorm1ModSingle(width)
1167 self.out_norm = Signal(reset_less=True)
1168 self.out_z = FPNumBase(width)
1169 self.out_roundz = Signal(reset_less=True)
1170
1171 def setup(self, m, in_z, in_of, in_mid):
1172 """ links module to inputs and outputs
1173 """
1174 self.mod.setup(m, in_z, in_of, self.out_z)
1175
1176 if self.in_mid is not None:
1177 m.d.comb += self.in_mid.eq(in_mid)
1178
1179 def action(self, m):
1180 self.idsync(m)
1181 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1182 m.next = "round"
1183
1184
1185 class FPNorm1Multi(FPState, FPID):
1186
1187 def __init__(self, width, id_wid):
1188 FPID.__init__(self, id_wid)
1189 FPState.__init__(self, "normalise_1")
1190 self.mod = FPNorm1ModMulti(width)
1191 self.stb = Signal(reset_less=True)
1192 self.ack = Signal(reset=0, reset_less=True)
1193 self.out_norm = Signal(reset_less=True)
1194 self.in_accept = Signal(reset_less=True)
1195 self.temp_z = FPNumBase(width)
1196 self.temp_of = Overflow()
1197 self.out_z = FPNumBase(width)
1198 self.out_roundz = Signal(reset_less=True)
1199
1200 def setup(self, m, in_z, in_of, norm_stb, in_mid):
1201 """ links module to inputs and outputs
1202 """
1203 self.mod.setup(m, in_z, in_of, norm_stb,
1204 self.in_accept, self.temp_z, self.temp_of,
1205 self.out_z, self.out_norm)
1206
1207 m.d.comb += self.stb.eq(norm_stb)
1208 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1209
1210 if self.in_mid is not None:
1211 m.d.comb += self.in_mid.eq(in_mid)
1212
1213 def action(self, m):
1214 self.idsync(m)
1215 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1216 m.d.sync += self.temp_of.eq(self.mod.out_of)
1217 m.d.sync += self.temp_z.eq(self.out_z)
1218 with m.If(self.out_norm):
1219 with m.If(self.in_accept):
1220 m.d.sync += [
1221 self.ack.eq(1),
1222 ]
1223 with m.Else():
1224 m.d.sync += self.ack.eq(0)
1225 with m.Else():
1226 # normalisation not required (or done).
1227 m.next = "round"
1228 m.d.sync += self.ack.eq(1)
1229 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1230
1231
1232 class FPNormToPack(FPState, FPID):
1233
1234 def __init__(self, width, id_wid):
1235 FPID.__init__(self, id_wid)
1236 FPState.__init__(self, "normalise_1")
1237 self.width = width
1238
1239 def setup(self, m, in_z, in_of, in_mid):
1240 """ links module to inputs and outputs
1241 """
1242
1243 # Normalisation (chained to input in_z+in_of)
1244 nmod = FPNorm1ModSingle(self.width)
1245 n_out_z = FPNumBase(self.width)
1246 n_out_roundz = Signal(reset_less=True)
1247 nmod.setup(m, in_z, in_of, n_out_z)
1248
1249 # Rounding (chained to normalisation)
1250 rmod = FPRoundMod(self.width)
1251 r_out_z = FPNumBase(self.width)
1252 rmod.setup(m, n_out_z, n_out_roundz)
1253 m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
1254 m.d.comb += r_out_z.eq(rmod.out_z)
1255
1256 # Corrections (chained to rounding)
1257 cmod = FPCorrectionsMod(self.width)
1258 c_out_z = FPNumBase(self.width)
1259 cmod.setup(m, r_out_z)
1260 m.d.comb += c_out_z.eq(cmod.out_z)
1261
1262 # Pack (chained to corrections)
1263 self.pmod = FPPackMod(self.width)
1264 self.out_z = FPNumBase(self.width)
1265 self.pmod.setup(m, c_out_z)
1266
1267 # Multiplex ID
1268 if self.in_mid is not None:
1269 m.d.comb += self.in_mid.eq(in_mid)
1270
1271 def action(self, m):
1272 self.idsync(m) # copies incoming ID to outgoing
1273 m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
1274 m.next = "pack_put_z"
1275
1276
1277 class FPRoundMod:
1278
1279 def __init__(self, width):
1280 self.in_roundz = Signal(reset_less=True)
1281 self.in_z = FPNumBase(width, False)
1282 self.out_z = FPNumBase(width, False)
1283
1284 def setup(self, m, in_z, roundz):
1285 m.submodules.roundz = self
1286
1287 m.d.comb += self.in_z.eq(in_z)
1288 m.d.comb += self.in_roundz.eq(roundz)
1289
1290 def elaborate(self, platform):
1291 m = Module()
1292 m.d.comb += self.out_z.eq(self.in_z)
1293 with m.If(self.in_roundz):
1294 m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
1295 with m.If(self.in_z.m == self.in_z.m1s): # all 1s
1296 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
1297 return m
1298
1299
1300 class FPRound(FPState, FPID):
1301
1302 def __init__(self, width, id_wid):
1303 FPState.__init__(self, "round")
1304 FPID.__init__(self, id_wid)
1305 self.mod = FPRoundMod(width)
1306 self.out_z = FPNumBase(width)
1307
1308 def setup(self, m, in_z, roundz, in_mid):
1309 """ links module to inputs and outputs
1310 """
1311 self.mod.setup(m, in_z, roundz)
1312
1313 if self.in_mid is not None:
1314 m.d.comb += self.in_mid.eq(in_mid)
1315
1316 def action(self, m):
1317 self.idsync(m)
1318 m.d.sync += self.out_z.eq(self.mod.out_z)
1319 m.next = "corrections"
1320
1321
1322 class FPCorrectionsMod:
1323
1324 def __init__(self, width):
1325 self.in_z = FPNumOut(width, False)
1326 self.out_z = FPNumOut(width, False)
1327
1328 def setup(self, m, in_z):
1329 """ links module to inputs and outputs
1330 """
1331 m.submodules.corrections = self
1332 m.d.comb += self.in_z.eq(in_z)
1333
1334 def elaborate(self, platform):
1335 m = Module()
1336 m.submodules.corr_in_z = self.in_z
1337 m.submodules.corr_out_z = self.out_z
1338 m.d.comb += self.out_z.eq(self.in_z)
1339 with m.If(self.in_z.is_denormalised):
1340 m.d.comb += self.out_z.e.eq(self.in_z.N127)
1341 return m
1342
1343
1344 class FPCorrections(FPState, FPID):
1345
1346 def __init__(self, width, id_wid):
1347 FPState.__init__(self, "corrections")
1348 FPID.__init__(self, id_wid)
1349 self.mod = FPCorrectionsMod(width)
1350 self.out_z = FPNumBase(width)
1351
1352 def setup(self, m, in_z, in_mid):
1353 """ links module to inputs and outputs
1354 """
1355 self.mod.setup(m, in_z)
1356 if self.in_mid is not None:
1357 m.d.comb += self.in_mid.eq(in_mid)
1358
1359 def action(self, m):
1360 self.idsync(m)
1361 m.d.sync += self.out_z.eq(self.mod.out_z)
1362 m.next = "pack"
1363
1364
1365 class FPPackMod:
1366
1367 def __init__(self, width):
1368 self.in_z = FPNumOut(width, False)
1369 self.out_z = FPNumOut(width, False)
1370
1371 def setup(self, m, in_z):
1372 """ links module to inputs and outputs
1373 """
1374 m.submodules.pack = self
1375 m.d.comb += self.in_z.eq(in_z)
1376
1377 def elaborate(self, platform):
1378 m = Module()
1379 m.submodules.pack_in_z = self.in_z
1380 with m.If(self.in_z.is_overflowed):
1381 m.d.comb += self.out_z.inf(self.in_z.s)
1382 with m.Else():
1383 m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
1384 return m
1385
1386
1387 class FPPack(FPState, FPID):
1388
1389 def __init__(self, width, id_wid):
1390 FPState.__init__(self, "pack")
1391 FPID.__init__(self, id_wid)
1392 self.mod = FPPackMod(width)
1393 self.out_z = FPNumOut(width, False)
1394
1395 def setup(self, m, in_z, in_mid):
1396 """ links module to inputs and outputs
1397 """
1398 self.mod.setup(m, in_z)
1399 if self.in_mid is not None:
1400 m.d.comb += self.in_mid.eq(in_mid)
1401
1402 def action(self, m):
1403 self.idsync(m)
1404 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1405 m.next = "pack_put_z"
1406
1407
1408 class FPPutZ(FPState):
1409
1410 def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1411 FPState.__init__(self, state)
1412 if to_state is None:
1413 to_state = "get_ops"
1414 self.to_state = to_state
1415 self.in_z = in_z
1416 self.out_z = out_z
1417 self.in_mid = in_mid
1418 self.out_mid = out_mid
1419
1420 def action(self, m):
1421 if self.in_mid is not None:
1422 m.d.sync += self.out_mid.eq(self.in_mid)
1423 m.d.sync += [
1424 self.out_z.v.eq(self.in_z.v)
1425 ]
1426 with m.If(self.out_z.stb & self.out_z.ack):
1427 m.d.sync += self.out_z.stb.eq(0)
1428 m.next = self.to_state
1429 with m.Else():
1430 m.d.sync += self.out_z.stb.eq(1)
1431
1432
1433 class FPPutZIdx(FPState):
1434
1435 def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1436 FPState.__init__(self, state)
1437 if to_state is None:
1438 to_state = "get_ops"
1439 self.to_state = to_state
1440 self.in_z = in_z
1441 self.out_zs = out_zs
1442 self.in_mid = in_mid
1443
1444 def action(self, m):
1445 outz_stb = Signal(reset_less=True)
1446 outz_ack = Signal(reset_less=True)
1447 m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1448 outz_ack.eq(self.out_zs[self.in_mid].ack),
1449 ]
1450 m.d.sync += [
1451 self.out_zs[self.in_mid].v.eq(self.in_z.v)
1452 ]
1453 with m.If(outz_stb & outz_ack):
1454 m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1455 m.next = self.to_state
1456 with m.Else():
1457 m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1458
1459
1460 class FPADDBaseMod(FPID):
1461
1462 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1463 """ IEEE754 FP Add
1464
1465 * width: bit-width of IEEE754. supported: 16, 32, 64
1466 * id_wid: an identifier that is sync-connected to the input
1467 * single_cycle: True indicates each stage to complete in 1 clock
1468 * compact: True indicates a reduced number of stages
1469 """
1470 FPID.__init__(self, id_wid)
1471 self.width = width
1472 self.single_cycle = single_cycle
1473 self.compact = compact
1474
1475 self.in_t = Trigger()
1476 self.in_a = Signal(width)
1477 self.in_b = Signal(width)
1478 self.out_z = FPOp(width)
1479
1480 self.states = []
1481
1482 def add_state(self, state):
1483 self.states.append(state)
1484 return state
1485
1486 def get_fragment(self, platform=None):
1487 """ creates the HDL code-fragment for FPAdd
1488 """
1489 m = Module()
1490 m.submodules.out_z = self.out_z
1491 m.submodules.in_t = self.in_t
1492 if self.compact:
1493 self.get_compact_fragment(m, platform)
1494 else:
1495 self.get_longer_fragment(m, platform)
1496
1497 with m.FSM() as fsm:
1498
1499 for state in self.states:
1500 with m.State(state.state_from):
1501 state.action(m)
1502
1503 return m
1504
1505 def get_longer_fragment(self, m, platform=None):
1506
1507 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1508 self.in_a, self.in_b, self.width))
1509 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1510 a = get.out_op1
1511 b = get.out_op2
1512
1513 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1514 sc.setup(m, a, b, self.in_mid)
1515
1516 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1517 dn.setup(m, a, b, sc.in_mid)
1518
1519 if self.single_cycle:
1520 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1521 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1522 else:
1523 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1524 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1525
1526 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1527 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1528
1529 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1530 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1531
1532 if self.single_cycle:
1533 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1534 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1535 else:
1536 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1537 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1538
1539 rn = self.add_state(FPRound(self.width, self.id_wid))
1540 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1541
1542 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1543 cor.setup(m, rn.out_z, rn.in_mid)
1544
1545 pa = self.add_state(FPPack(self.width, self.id_wid))
1546 pa.setup(m, cor.out_z, rn.in_mid)
1547
1548 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1549 pa.in_mid, self.out_mid))
1550
1551 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1552 pa.in_mid, self.out_mid))
1553
1554 def get_compact_fragment(self, m, platform=None):
1555
1556 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1557 self.in_a, self.in_b, self.width))
1558 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1559 a = get.out_op1
1560 b = get.out_op2
1561
1562 sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1563 sc.setup(m, a, b, self.in_mid)
1564
1565 alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1566 alm.setup(m, sc.o.a, sc.o.b, sc.in_mid)
1567
1568 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1569 n1.setup(m, alm.out_z, alm.out_of, alm.in_mid)
1570
1571 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
1572 n1.in_mid, self.out_mid))
1573
1574 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1575 sc.in_mid, self.out_mid))
1576
1577
1578 class FPADDBase(FPState, FPID):
1579
1580 def __init__(self, width, id_wid=None, single_cycle=False):
1581 """ IEEE754 FP Add
1582
1583 * width: bit-width of IEEE754. supported: 16, 32, 64
1584 * id_wid: an identifier that is sync-connected to the input
1585 * single_cycle: True indicates each stage to complete in 1 clock
1586 """
1587 FPID.__init__(self, id_wid)
1588 FPState.__init__(self, "fpadd")
1589 self.width = width
1590 self.single_cycle = single_cycle
1591 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1592
1593 self.in_t = Trigger()
1594 self.in_a = Signal(width)
1595 self.in_b = Signal(width)
1596 #self.out_z = FPOp(width)
1597
1598 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1599 self.in_accept = Signal(reset_less=True)
1600 self.add_stb = Signal(reset_less=True)
1601 self.add_ack = Signal(reset=0, reset_less=True)
1602
1603 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1604 self.out_z = out_z
1605 self.out_mid = out_mid
1606 m.d.comb += [self.in_a.eq(a),
1607 self.in_b.eq(b),
1608 self.mod.in_a.eq(self.in_a),
1609 self.mod.in_b.eq(self.in_b),
1610 self.in_mid.eq(in_mid),
1611 self.mod.in_mid.eq(self.in_mid),
1612 self.z_done.eq(self.mod.out_z.trigger),
1613 #self.add_stb.eq(add_stb),
1614 self.mod.in_t.stb.eq(self.in_t.stb),
1615 self.in_t.ack.eq(self.mod.in_t.ack),
1616 self.out_mid.eq(self.mod.out_mid),
1617 self.out_z.v.eq(self.mod.out_z.v),
1618 self.out_z.stb.eq(self.mod.out_z.stb),
1619 self.mod.out_z.ack.eq(self.out_z.ack),
1620 ]
1621
1622 m.d.sync += self.add_stb.eq(add_stb)
1623 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1624 m.d.sync += self.out_z.ack.eq(0) # likewise
1625 #m.d.sync += self.in_t.stb.eq(0)
1626
1627 m.submodules.fpadd = self.mod
1628
1629 def action(self, m):
1630
1631 # in_accept is set on incoming strobe HIGH and ack LOW.
1632 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1633
1634 #with m.If(self.in_t.ack):
1635 # m.d.sync += self.in_t.stb.eq(0)
1636 with m.If(~self.z_done):
1637 # not done: test for accepting an incoming operand pair
1638 with m.If(self.in_accept):
1639 m.d.sync += [
1640 self.add_ack.eq(1), # acknowledge receipt...
1641 self.in_t.stb.eq(1), # initiate add
1642 ]
1643 with m.Else():
1644 m.d.sync += [self.add_ack.eq(0),
1645 self.in_t.stb.eq(0),
1646 self.out_z.ack.eq(1),
1647 ]
1648 with m.Else():
1649 # done: acknowledge, and write out id and value
1650 m.d.sync += [self.add_ack.eq(1),
1651 self.in_t.stb.eq(0)
1652 ]
1653 m.next = "put_z"
1654
1655 return
1656
1657 if self.in_mid is not None:
1658 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1659
1660 m.d.sync += [
1661 self.out_z.v.eq(self.mod.out_z.v)
1662 ]
1663 # move to output state on detecting z ack
1664 with m.If(self.out_z.trigger):
1665 m.d.sync += self.out_z.stb.eq(0)
1666 m.next = "put_z"
1667 with m.Else():
1668 m.d.sync += self.out_z.stb.eq(1)
1669
1670 class ResArray:
1671 def __init__(self, width, id_wid):
1672 self.width = width
1673 self.id_wid = id_wid
1674 res = []
1675 for i in range(rs_sz):
1676 out_z = FPOp(width)
1677 out_z.name = "out_z_%d" % i
1678 res.append(out_z)
1679 self.res = Array(res)
1680 self.in_z = FPOp(width)
1681 self.in_mid = Signal(self.id_wid, reset_less=True)
1682
1683 def setup(self, m, in_z, in_mid):
1684 m.d.comb += [self.in_z.eq(in_z),
1685 self.in_mid.eq(in_mid)]
1686
1687 def get_fragment(self, platform=None):
1688 """ creates the HDL code-fragment for FPAdd
1689 """
1690 m = Module()
1691 m.submodules.res_in_z = self.in_z
1692 m.submodules += self.res
1693
1694 return m
1695
1696 def ports(self):
1697 res = []
1698 for z in self.res:
1699 res += z.ports()
1700 return res
1701
1702
1703 class FPADD(FPID):
1704 """ FPADD: stages as follows:
1705
1706 FPGetOp (a)
1707 |
1708 FPGetOp (b)
1709 |
1710 FPAddBase---> FPAddBaseMod
1711 | |
1712 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1713
1714 FPAddBase is tricky: it is both a stage and *has* stages.
1715 Connection to FPAddBaseMod therefore requires an in stb/ack
1716 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1717 needs to be the thing that raises the incoming stb.
1718 """
1719
1720 def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1721 """ IEEE754 FP Add
1722
1723 * width: bit-width of IEEE754. supported: 16, 32, 64
1724 * id_wid: an identifier that is sync-connected to the input
1725 * single_cycle: True indicates each stage to complete in 1 clock
1726 """
1727 self.width = width
1728 self.id_wid = id_wid
1729 self.single_cycle = single_cycle
1730
1731 #self.out_z = FPOp(width)
1732 self.ids = FPID(id_wid)
1733
1734 rs = []
1735 for i in range(rs_sz):
1736 in_a = FPOp(width)
1737 in_b = FPOp(width)
1738 in_a.name = "in_a_%d" % i
1739 in_b.name = "in_b_%d" % i
1740 rs.append((in_a, in_b))
1741 self.rs = Array(rs)
1742
1743 res = []
1744 for i in range(rs_sz):
1745 out_z = FPOp(width)
1746 out_z.name = "out_z_%d" % i
1747 res.append(out_z)
1748 self.res = Array(res)
1749
1750 self.states = []
1751
1752 def add_state(self, state):
1753 self.states.append(state)
1754 return state
1755
1756 def get_fragment(self, platform=None):
1757 """ creates the HDL code-fragment for FPAdd
1758 """
1759 m = Module()
1760 m.submodules += self.rs
1761
1762 in_a = self.rs[0][0]
1763 in_b = self.rs[0][1]
1764
1765 out_z = FPOp(self.width)
1766 out_mid = Signal(self.id_wid, reset_less=True)
1767 m.submodules.out_z = out_z
1768
1769 geta = self.add_state(FPGetOp("get_a", "get_b",
1770 in_a, self.width))
1771 geta.setup(m, in_a)
1772 a = geta.out_op
1773
1774 getb = self.add_state(FPGetOp("get_b", "fpadd",
1775 in_b, self.width))
1776 getb.setup(m, in_b)
1777 b = getb.out_op
1778
1779 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1780 ab = self.add_state(ab)
1781 ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1782 out_z, out_mid)
1783
1784 pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1785 out_mid, "get_a"))
1786
1787 with m.FSM() as fsm:
1788
1789 for state in self.states:
1790 with m.State(state.state_from):
1791 state.action(m)
1792
1793 return m
1794
1795
1796 if __name__ == "__main__":
1797 if True:
1798 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1799 main(alu, ports=alu.rs[0][0].ports() + \
1800 alu.rs[0][1].ports() + \
1801 alu.res[0].ports() + \
1802 [alu.ids.in_mid, alu.ids.out_mid])
1803 else:
1804 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1805 main(alu, ports=[alu.in_a, alu.in_b] + \
1806 alu.in_t.ports() + \
1807 alu.out_z.ports() + \
1808 [alu.in_mid, alu.out_mid])
1809
1810
1811 # works... but don't use, just do "python fname.py convert -t v"
1812 #print (verilog.convert(alu, ports=[
1813 # ports=alu.in_a.ports() + \
1814 # alu.in_b.ports() + \
1815 # alu.out_z.ports())