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use ospec in FPAddAlignSingleAdd
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 #from fpbase import FPNumShiftMultiRight
13
14
15 class FPState(FPBase):
16 def __init__(self, state_from):
17 self.state_from = state_from
18
19 def set_inputs(self, inputs):
20 self.inputs = inputs
21 for k,v in inputs.items():
22 setattr(self, k, v)
23
24 def set_outputs(self, outputs):
25 self.outputs = outputs
26 for k,v in outputs.items():
27 setattr(self, k, v)
28
29
30 class FPGetSyncOpsMod:
31 def __init__(self, width, num_ops=2):
32 self.width = width
33 self.num_ops = num_ops
34 inops = []
35 outops = []
36 for i in range(num_ops):
37 inops.append(Signal(width, reset_less=True))
38 outops.append(Signal(width, reset_less=True))
39 self.in_op = inops
40 self.out_op = outops
41 self.stb = Signal(num_ops)
42 self.ack = Signal()
43 self.ready = Signal(reset_less=True)
44 self.out_decode = Signal(reset_less=True)
45
46 def elaborate(self, platform):
47 m = Module()
48 m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
49 m.d.comb += self.out_decode.eq(self.ack & self.ready)
50 with m.If(self.out_decode):
51 for i in range(self.num_ops):
52 m.d.comb += [
53 self.out_op[i].eq(self.in_op[i]),
54 ]
55 return m
56
57 def ports(self):
58 return self.in_op + self.out_op + [self.stb, self.ack]
59
60
61 class FPOps(Trigger):
62 def __init__(self, width, num_ops):
63 Trigger.__init__(self)
64 self.width = width
65 self.num_ops = num_ops
66
67 res = []
68 for i in range(num_ops):
69 res.append(Signal(width))
70 self.v = Array(res)
71
72 def ports(self):
73 res = []
74 for i in range(self.num_ops):
75 res.append(self.v[i])
76 res.append(self.ack)
77 res.append(self.stb)
78 return res
79
80
81 class InputGroup:
82 def __init__(self, width, num_ops=2, num_rows=4):
83 self.width = width
84 self.num_ops = num_ops
85 self.num_rows = num_rows
86 self.mmax = int(log(self.num_rows) / log(2))
87 self.rs = []
88 self.mid = Signal(self.mmax, reset_less=True) # multiplex id
89 for i in range(num_rows):
90 self.rs.append(FPGetSyncOpsMod(width, num_ops))
91 self.rs = Array(self.rs)
92
93 self.out_op = FPOps(width, num_ops)
94
95 def elaborate(self, platform):
96 m = Module()
97
98 pe = PriorityEncoder(self.num_rows)
99 m.submodules.selector = pe
100 m.submodules.out_op = self.out_op
101 m.submodules += self.rs
102
103 # connect priority encoder
104 in_ready = []
105 for i in range(self.num_rows):
106 in_ready.append(self.rs[i].ready)
107 m.d.comb += pe.i.eq(Cat(*in_ready))
108
109 active = Signal(reset_less=True)
110 out_en = Signal(reset_less=True)
111 m.d.comb += active.eq(~pe.n) # encoder active
112 m.d.comb += out_en.eq(active & self.out_op.trigger)
113
114 # encoder active: ack relevant input, record MID, pass output
115 with m.If(out_en):
116 rs = self.rs[pe.o]
117 m.d.sync += self.mid.eq(pe.o)
118 m.d.sync += rs.ack.eq(0)
119 m.d.sync += self.out_op.stb.eq(0)
120 for j in range(self.num_ops):
121 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
122 with m.Else():
123 m.d.sync += self.out_op.stb.eq(1)
124 # acks all default to zero
125 for i in range(self.num_rows):
126 m.d.sync += self.rs[i].ack.eq(1)
127
128 return m
129
130 def ports(self):
131 res = []
132 for i in range(self.num_rows):
133 inop = self.rs[i]
134 res += inop.in_op + [inop.stb]
135 return self.out_op.ports() + res + [self.mid]
136
137
138 class FPGetOpMod:
139 def __init__(self, width):
140 self.in_op = FPOp(width)
141 self.out_op = Signal(width)
142 self.out_decode = Signal(reset_less=True)
143
144 def elaborate(self, platform):
145 m = Module()
146 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
147 m.submodules.get_op_in = self.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m.If(self.out_decode):
150 m.d.comb += [
151 self.out_op.eq(self.in_op.v),
152 ]
153 return m
154
155
156 class FPGetOp(FPState):
157 """ gets operand
158 """
159
160 def __init__(self, in_state, out_state, in_op, width):
161 FPState.__init__(self, in_state)
162 self.out_state = out_state
163 self.mod = FPGetOpMod(width)
164 self.in_op = in_op
165 self.out_op = Signal(width)
166 self.out_decode = Signal(reset_less=True)
167
168 def setup(self, m, in_op):
169 """ links module to inputs and outputs
170 """
171 setattr(m.submodules, self.state_from, self.mod)
172 m.d.comb += self.mod.in_op.eq(in_op)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m.d.comb += self.out_decode.eq(self.mod.out_decode)
175
176 def action(self, m):
177 with m.If(self.out_decode):
178 m.next = self.out_state
179 m.d.sync += [
180 self.in_op.ack.eq(0),
181 self.out_op.eq(self.mod.out_op)
182 ]
183 with m.Else():
184 m.d.sync += self.in_op.ack.eq(1)
185
186
187 class FPGet2OpMod(Trigger):
188 def __init__(self, width):
189 Trigger.__init__(self)
190 self.in_op1 = Signal(width, reset_less=True)
191 self.in_op2 = Signal(width, reset_less=True)
192 self.out_op1 = FPNumIn(None, width)
193 self.out_op2 = FPNumIn(None, width)
194
195 def elaborate(self, platform):
196 m = Trigger.elaborate(self, platform)
197 #m.submodules.get_op_in = self.in_op
198 m.submodules.get_op1_out = self.out_op1
199 m.submodules.get_op2_out = self.out_op2
200 with m.If(self.trigger):
201 m.d.comb += [
202 self.out_op1.decode(self.in_op1),
203 self.out_op2.decode(self.in_op2),
204 ]
205 return m
206
207
208 class FPGet2Op(FPState):
209 """ gets operands
210 """
211
212 def __init__(self, in_state, out_state, in_op1, in_op2, width):
213 FPState.__init__(self, in_state)
214 self.out_state = out_state
215 self.mod = FPGet2OpMod(width)
216 self.in_op1 = in_op1
217 self.in_op2 = in_op2
218 self.out_op1 = FPNumIn(None, width)
219 self.out_op2 = FPNumIn(None, width)
220 self.in_stb = Signal(reset_less=True)
221 self.out_ack = Signal(reset_less=True)
222 self.out_decode = Signal(reset_less=True)
223
224 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
225 """ links module to inputs and outputs
226 """
227 m.submodules.get_ops = self.mod
228 m.d.comb += self.mod.in_op1.eq(in_op1)
229 m.d.comb += self.mod.in_op2.eq(in_op2)
230 m.d.comb += self.mod.stb.eq(in_stb)
231 m.d.comb += self.out_ack.eq(self.mod.ack)
232 m.d.comb += self.out_decode.eq(self.mod.trigger)
233 m.d.comb += in_ack.eq(self.mod.ack)
234
235 def action(self, m):
236 with m.If(self.out_decode):
237 m.next = self.out_state
238 m.d.sync += [
239 self.mod.ack.eq(0),
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self.out_op1.eq(self.mod.out_op1),
243 self.out_op2.eq(self.mod.out_op2)
244 ]
245 with m.Else():
246 m.d.sync += self.mod.ack.eq(1)
247
248 class FPNumBase2Ops:
249
250 def __init__(self, width, m_extra=True):
251 self.a = FPNumBase(width, m_extra)
252 self.b = FPNumBase(width, m_extra)
253
254 def eq(self, i):
255 return [self.a.eq(i.a), self.b.eq(i.b)]
256
257
258 class FPAddSpecialCasesMod:
259 """ special cases: NaNs, infs, zeros, denormalised
260 NOTE: some of these are unique to add. see "Special Operations"
261 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
262 """
263
264 def __init__(self, width):
265 self.width = width
266 self.i = self.ispec()
267 self.out_z = self.ospec()
268 self.out_do_z = Signal(reset_less=True)
269
270 def ispec(self):
271 return FPNumBase2Ops(self.width)
272
273 def ospec(self):
274 return FPNumOut(self.width, False)
275
276 def setup(self, m, in_a, in_b, out_do_z):
277 """ links module to inputs and outputs
278 """
279 m.submodules.specialcases = self
280 m.d.comb += self.i.a.eq(in_a)
281 m.d.comb += self.i.b.eq(in_b)
282 m.d.comb += out_do_z.eq(self.out_do_z)
283
284 def elaborate(self, platform):
285 m = Module()
286
287 m.submodules.sc_in_a = self.i.a
288 m.submodules.sc_in_b = self.i.b
289 m.submodules.sc_out_z = self.out_z
290
291 s_nomatch = Signal()
292 m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
293
294 m_match = Signal()
295 m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
296
297 # if a is NaN or b is NaN return NaN
298 with m.If(self.i.a.is_nan | self.i.b.is_nan):
299 m.d.comb += self.out_do_z.eq(1)
300 m.d.comb += self.out_z.nan(0)
301
302 # XXX WEIRDNESS for FP16 non-canonical NaN handling
303 # under review
304
305 ## if a is zero and b is NaN return -b
306 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
307 # m.d.comb += self.out_do_z.eq(1)
308 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
309
310 ## if b is zero and a is NaN return -a
311 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
312 # m.d.comb += self.out_do_z.eq(1)
313 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
314
315 ## if a is -zero and b is NaN return -b
316 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
317 # m.d.comb += self.out_do_z.eq(1)
318 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
319
320 ## if b is -zero and a is NaN return -a
321 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
322 # m.d.comb += self.out_do_z.eq(1)
323 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
324
325 # if a is inf return inf (or NaN)
326 with m.Elif(self.i.a.is_inf):
327 m.d.comb += self.out_do_z.eq(1)
328 m.d.comb += self.out_z.inf(self.i.a.s)
329 # if a is inf and signs don't match return NaN
330 with m.If(self.i.b.exp_128 & s_nomatch):
331 m.d.comb += self.out_z.nan(0)
332
333 # if b is inf return inf
334 with m.Elif(self.i.b.is_inf):
335 m.d.comb += self.out_do_z.eq(1)
336 m.d.comb += self.out_z.inf(self.i.b.s)
337
338 # if a is zero and b zero return signed-a/b
339 with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
340 m.d.comb += self.out_do_z.eq(1)
341 m.d.comb += self.out_z.create(self.i.a.s & self.i.b.s,
342 self.i.b.e,
343 self.i.b.m[3:-1])
344
345 # if a is zero return b
346 with m.Elif(self.i.a.is_zero):
347 m.d.comb += self.out_do_z.eq(1)
348 m.d.comb += self.out_z.create(self.i.b.s, self.i.b.e,
349 self.i.b.m[3:-1])
350
351 # if b is zero return a
352 with m.Elif(self.i.b.is_zero):
353 m.d.comb += self.out_do_z.eq(1)
354 m.d.comb += self.out_z.create(self.i.a.s, self.i.a.e,
355 self.i.a.m[3:-1])
356
357 # if a equal to -b return zero (+ve zero)
358 with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
359 m.d.comb += self.out_do_z.eq(1)
360 m.d.comb += self.out_z.zero(0)
361
362 # Denormalised Number checks
363 with m.Else():
364 m.d.comb += self.out_do_z.eq(0)
365
366 return m
367
368
369 class FPID:
370 def __init__(self, id_wid):
371 self.id_wid = id_wid
372 if self.id_wid:
373 self.in_mid = Signal(id_wid, reset_less=True)
374 self.out_mid = Signal(id_wid, reset_less=True)
375 else:
376 self.in_mid = None
377 self.out_mid = None
378
379 def idsync(self, m):
380 if self.id_wid is not None:
381 m.d.sync += self.out_mid.eq(self.in_mid)
382
383
384 class FPAddSpecialCases(FPState, FPID):
385 """ special cases: NaNs, infs, zeros, denormalised
386 NOTE: some of these are unique to add. see "Special Operations"
387 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
388 """
389
390 def __init__(self, width, id_wid):
391 FPState.__init__(self, "special_cases")
392 FPID.__init__(self, id_wid)
393 self.mod = FPAddSpecialCasesMod(width)
394 self.out_z = self.mod.ospec()
395 self.out_do_z = Signal(reset_less=True)
396
397 def setup(self, m, in_a, in_b, in_mid):
398 """ links module to inputs and outputs
399 """
400 self.mod.setup(m, in_a, in_b, self.out_do_z)
401 if self.in_mid is not None:
402 m.d.comb += self.in_mid.eq(in_mid)
403
404 def action(self, m):
405 self.idsync(m)
406 with m.If(self.out_do_z):
407 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
408 m.next = "put_z"
409 with m.Else():
410 m.next = "denormalise"
411
412
413 class FPAddSpecialCasesDeNorm(FPState, FPID):
414 """ special cases: NaNs, infs, zeros, denormalised
415 NOTE: some of these are unique to add. see "Special Operations"
416 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
417 """
418
419 def __init__(self, width, id_wid):
420 FPState.__init__(self, "special_cases")
421 FPID.__init__(self, id_wid)
422 self.smod = FPAddSpecialCasesMod(width)
423 self.out_z = self.smod.ospec()
424 self.out_do_z = Signal(reset_less=True)
425
426 self.dmod = FPAddDeNormMod(width)
427 self.o = self.dmod.ospec()
428
429 def setup(self, m, in_a, in_b, in_mid):
430 """ links module to inputs and outputs
431 """
432 self.smod.setup(m, in_a, in_b, self.out_do_z)
433 self.dmod.setup(m, in_a, in_b)
434 if self.in_mid is not None:
435 m.d.comb += self.in_mid.eq(in_mid)
436
437 def action(self, m):
438 self.idsync(m)
439 with m.If(self.out_do_z):
440 m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
441 m.next = "put_z"
442 with m.Else():
443 m.next = "align"
444 m.d.sync += self.o.a.eq(self.dmod.o.a)
445 m.d.sync += self.o.b.eq(self.dmod.o.b)
446
447
448 class FPAddDeNormMod(FPState):
449
450 def __init__(self, width):
451 self.width = width
452 self.i = self.ispec()
453 self.o = self.ospec()
454
455 def ispec(self):
456 return FPNumBase2Ops(self.width)
457
458 def ospec(self):
459 return FPNumBase2Ops(self.width)
460
461 def setup(self, m, in_a, in_b):
462 """ links module to inputs and outputs
463 """
464 m.submodules.denormalise = self
465 m.d.comb += self.i.a.eq(in_a)
466 m.d.comb += self.i.b.eq(in_b)
467
468 def elaborate(self, platform):
469 m = Module()
470 m.submodules.denorm_in_a = self.i.a
471 m.submodules.denorm_in_b = self.i.b
472 m.submodules.denorm_out_a = self.o.a
473 m.submodules.denorm_out_b = self.o.b
474 # hmmm, don't like repeating identical code
475 m.d.comb += self.o.a.eq(self.i.a)
476 with m.If(self.i.a.exp_n127):
477 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
478 with m.Else():
479 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
480
481 m.d.comb += self.o.b.eq(self.i.b)
482 with m.If(self.i.b.exp_n127):
483 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
484 with m.Else():
485 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
486
487 return m
488
489
490 class FPAddDeNorm(FPState, FPID):
491
492 def __init__(self, width, id_wid):
493 FPState.__init__(self, "denormalise")
494 FPID.__init__(self, id_wid)
495 self.mod = FPAddDeNormMod(width)
496 self.out_a = FPNumBase(width)
497 self.out_b = FPNumBase(width)
498
499 def setup(self, m, in_a, in_b, in_mid):
500 """ links module to inputs and outputs
501 """
502 self.mod.setup(m, in_a, in_b)
503 if self.in_mid is not None:
504 m.d.comb += self.in_mid.eq(in_mid)
505
506 def action(self, m):
507 self.idsync(m)
508 # Denormalised Number checks
509 m.next = "align"
510 m.d.sync += self.out_a.eq(self.mod.out_a)
511 m.d.sync += self.out_b.eq(self.mod.out_b)
512
513
514 class FPAddAlignMultiMod(FPState):
515
516 def __init__(self, width):
517 self.in_a = FPNumBase(width)
518 self.in_b = FPNumBase(width)
519 self.out_a = FPNumIn(None, width)
520 self.out_b = FPNumIn(None, width)
521 self.exp_eq = Signal(reset_less=True)
522
523 def elaborate(self, platform):
524 # This one however (single-cycle) will do the shift
525 # in one go.
526
527 m = Module()
528
529 m.submodules.align_in_a = self.in_a
530 m.submodules.align_in_b = self.in_b
531 m.submodules.align_out_a = self.out_a
532 m.submodules.align_out_b = self.out_b
533
534 # NOTE: this does *not* do single-cycle multi-shifting,
535 # it *STAYS* in the align state until exponents match
536
537 # exponent of a greater than b: shift b down
538 m.d.comb += self.exp_eq.eq(0)
539 m.d.comb += self.out_a.eq(self.in_a)
540 m.d.comb += self.out_b.eq(self.in_b)
541 agtb = Signal(reset_less=True)
542 altb = Signal(reset_less=True)
543 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
544 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
545 with m.If(agtb):
546 m.d.comb += self.out_b.shift_down(self.in_b)
547 # exponent of b greater than a: shift a down
548 with m.Elif(altb):
549 m.d.comb += self.out_a.shift_down(self.in_a)
550 # exponents equal: move to next stage.
551 with m.Else():
552 m.d.comb += self.exp_eq.eq(1)
553 return m
554
555
556 class FPAddAlignMulti(FPState, FPID):
557
558 def __init__(self, width, id_wid):
559 FPID.__init__(self, id_wid)
560 FPState.__init__(self, "align")
561 self.mod = FPAddAlignMultiMod(width)
562 self.out_a = FPNumIn(None, width)
563 self.out_b = FPNumIn(None, width)
564 self.exp_eq = Signal(reset_less=True)
565
566 def setup(self, m, in_a, in_b, in_mid):
567 """ links module to inputs and outputs
568 """
569 m.submodules.align = self.mod
570 m.d.comb += self.mod.in_a.eq(in_a)
571 m.d.comb += self.mod.in_b.eq(in_b)
572 #m.d.comb += self.out_a.eq(self.mod.out_a)
573 #m.d.comb += self.out_b.eq(self.mod.out_b)
574 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
575 if self.in_mid is not None:
576 m.d.comb += self.in_mid.eq(in_mid)
577
578 def action(self, m):
579 self.idsync(m)
580 m.d.sync += self.out_a.eq(self.mod.out_a)
581 m.d.sync += self.out_b.eq(self.mod.out_b)
582 with m.If(self.exp_eq):
583 m.next = "add_0"
584
585
586 class FPNumIn2Ops:
587
588 def __init__(self, width):
589 self.a = FPNumIn(None, width)
590 self.b = FPNumIn(None, width)
591
592 def eq(self, i):
593 return [self.a.eq(i.a), self.b.eq(i.b)]
594
595
596 class FPAddAlignSingleMod:
597
598 def __init__(self, width):
599 self.width = width
600 self.i = self.ispec()
601 self.o = self.ospec()
602
603 def ispec(self):
604 return FPNumBase2Ops(self.width)
605
606 def ospec(self):
607 return FPNumIn2Ops(self.width)
608
609 def setup(self, m, in_a, in_b):
610 """ links module to inputs and outputs
611 """
612 m.submodules.align = self
613 m.d.comb += self.i.a.eq(in_a)
614 m.d.comb += self.i.b.eq(in_b)
615
616 def elaborate(self, platform):
617 """ Aligns A against B or B against A, depending on which has the
618 greater exponent. This is done in a *single* cycle using
619 variable-width bit-shift
620
621 the shifter used here is quite expensive in terms of gates.
622 Mux A or B in (and out) into temporaries, as only one of them
623 needs to be aligned against the other
624 """
625 m = Module()
626
627 m.submodules.align_in_a = self.i.a
628 m.submodules.align_in_b = self.i.b
629 m.submodules.align_out_a = self.o.a
630 m.submodules.align_out_b = self.o.b
631
632 # temporary (muxed) input and output to be shifted
633 t_inp = FPNumBase(self.width)
634 t_out = FPNumIn(None, self.width)
635 espec = (len(self.i.a.e), True)
636 msr = MultiShiftRMerge(self.i.a.m_width, espec)
637 m.submodules.align_t_in = t_inp
638 m.submodules.align_t_out = t_out
639 m.submodules.multishift_r = msr
640
641 ediff = Signal(espec, reset_less=True)
642 ediffr = Signal(espec, reset_less=True)
643 tdiff = Signal(espec, reset_less=True)
644 elz = Signal(reset_less=True)
645 egz = Signal(reset_less=True)
646
647 # connect multi-shifter to t_inp/out mantissa (and tdiff)
648 m.d.comb += msr.inp.eq(t_inp.m)
649 m.d.comb += msr.diff.eq(tdiff)
650 m.d.comb += t_out.m.eq(msr.m)
651 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
652 m.d.comb += t_out.s.eq(t_inp.s)
653
654 m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
655 m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
656 m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
657 m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
658
659 # default: A-exp == B-exp, A and B untouched (fall through)
660 m.d.comb += self.o.a.eq(self.i.a)
661 m.d.comb += self.o.b.eq(self.i.b)
662 # only one shifter (muxed)
663 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
664 # exponent of a greater than b: shift b down
665 with m.If(egz):
666 m.d.comb += [t_inp.eq(self.i.b),
667 tdiff.eq(ediff),
668 self.o.b.eq(t_out),
669 self.o.b.s.eq(self.i.b.s), # whoops forgot sign
670 ]
671 # exponent of b greater than a: shift a down
672 with m.Elif(elz):
673 m.d.comb += [t_inp.eq(self.i.a),
674 tdiff.eq(ediffr),
675 self.o.a.eq(t_out),
676 self.o.a.s.eq(self.i.a.s), # whoops forgot sign
677 ]
678 return m
679
680
681 class FPAddAlignSingle(FPState, FPID):
682
683 def __init__(self, width, id_wid):
684 FPState.__init__(self, "align")
685 FPID.__init__(self, id_wid)
686 self.mod = FPAddAlignSingleMod(width)
687 self.out_a = FPNumIn(None, width)
688 self.out_b = FPNumIn(None, width)
689
690 def setup(self, m, in_a, in_b, in_mid):
691 """ links module to inputs and outputs
692 """
693 self.mod.setup(m, in_a, in_b)
694 if self.in_mid is not None:
695 m.d.comb += self.in_mid.eq(in_mid)
696
697 def action(self, m):
698 self.idsync(m)
699 # NOTE: could be done as comb
700 m.d.sync += self.out_a.eq(self.mod.out_a)
701 m.d.sync += self.out_b.eq(self.mod.out_b)
702 m.next = "add_0"
703
704
705 class FPAddAlignSingleAdd(FPState, FPID):
706
707 def __init__(self, width, id_wid):
708 FPState.__init__(self, "align")
709 FPID.__init__(self, id_wid)
710 self.mod = FPAddAlignSingleMod(width)
711 self.o = self.mod.ospec()
712
713 self.a0mod = FPAddStage0Mod(width)
714 self.a0_out_z = FPNumBase(width, False)
715 self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
716 self.a0_out_z = FPNumBase(width, False)
717
718 self.a1mod = FPAddStage1Mod(width)
719 self.a1o = self.a1mod.ospec()
720
721 def setup(self, m, in_a, in_b, in_mid):
722 """ links module to inputs and outputs
723 """
724 self.mod.setup(m, in_a, in_b)
725 m.d.comb += self.o.eq(self.mod.o)
726
727 self.a0mod.setup(m, self.o.a, self.o.b)
728 m.d.comb += self.a0_out_z.eq(self.a0mod.o.z)
729 m.d.comb += self.out_tot.eq(self.a0mod.o.tot)
730
731 self.a1mod.setup(m, self.out_tot, self.a0_out_z)
732
733 if self.in_mid is not None:
734 m.d.comb += self.in_mid.eq(in_mid)
735
736 def action(self, m):
737 self.idsync(m)
738 m.d.sync += self.a1o.eq(self.a1mod.o)
739 m.next = "normalise_1"
740
741
742 class FPAddStage0Data:
743
744 def __init__(self, width):
745 self.z = FPNumBase(width, False)
746 self.tot = Signal(self.z.m_width + 4, reset_less=True)
747
748 def eq(self, i):
749 return [self.z.eq(i.z), self.tot.eq(i.tot)]
750
751
752 class FPAddStage0Mod:
753
754 def __init__(self, width):
755 self.width = width
756 self.i = self.ispec()
757 self.o = self.ospec()
758
759 def ispec(self):
760 return FPNumBase2Ops(self.width)
761
762 def ospec(self):
763 return FPAddStage0Data(self.width)
764
765 def setup(self, m, in_a, in_b):
766 """ links module to inputs and outputs
767 """
768 m.submodules.add0 = self
769 m.d.comb += self.i.a.eq(in_a)
770 m.d.comb += self.i.b.eq(in_b)
771
772 def elaborate(self, platform):
773 m = Module()
774 m.submodules.add0_in_a = self.i.a
775 m.submodules.add0_in_b = self.i.b
776 m.submodules.add0_out_z = self.o.z
777
778 m.d.comb += self.o.z.e.eq(self.i.a.e)
779
780 # store intermediate tests (and zero-extended mantissas)
781 seq = Signal(reset_less=True)
782 mge = Signal(reset_less=True)
783 am0 = Signal(len(self.i.a.m)+1, reset_less=True)
784 bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
785 m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
786 mge.eq(self.i.a.m >= self.i.b.m),
787 am0.eq(Cat(self.i.a.m, 0)),
788 bm0.eq(Cat(self.i.b.m, 0))
789 ]
790 # same-sign (both negative or both positive) add mantissas
791 with m.If(seq):
792 m.d.comb += [
793 self.o.tot.eq(am0 + bm0),
794 self.o.z.s.eq(self.i.a.s)
795 ]
796 # a mantissa greater than b, use a
797 with m.Elif(mge):
798 m.d.comb += [
799 self.o.tot.eq(am0 - bm0),
800 self.o.z.s.eq(self.i.a.s)
801 ]
802 # b mantissa greater than a, use b
803 with m.Else():
804 m.d.comb += [
805 self.o.tot.eq(bm0 - am0),
806 self.o.z.s.eq(self.i.b.s)
807 ]
808 return m
809
810
811 class FPAddStage0(FPState, FPID):
812 """ First stage of add. covers same-sign (add) and subtract
813 special-casing when mantissas are greater or equal, to
814 give greatest accuracy.
815 """
816
817 def __init__(self, width, id_wid):
818 FPState.__init__(self, "add_0")
819 FPID.__init__(self, id_wid)
820 self.mod = FPAddStage0Mod(width)
821 self.o = self.mod.ospec()
822
823 def setup(self, m, in_a, in_b, in_mid):
824 """ links module to inputs and outputs
825 """
826 self.mod.setup(m, in_a, in_b)
827 if self.in_mid is not None:
828 m.d.comb += self.in_mid.eq(in_mid)
829
830 def action(self, m):
831 self.idsync(m)
832 # NOTE: these could be done as combinatorial (merge add0+add1)
833 m.d.sync += self.o.eq(self.mod.o)
834 m.next = "add_1"
835
836
837 class FPAddStage1Data:
838
839 def __init__(self, width):
840 self.z = FPNumBase(width, False)
841 self.of = Overflow()
842
843 def eq(self, i):
844 return [self.z.eq(i.z), self.of.eq(i.of)]
845
846
847
848 class FPAddStage1Mod(FPState):
849 """ Second stage of add: preparation for normalisation.
850 detects when tot sum is too big (tot[27] is kinda a carry bit)
851 """
852
853 def __init__(self, width):
854 self.width = width
855 self.i = self.ispec()
856 self.o = self.ospec()
857
858 def ispec(self):
859 return FPAddStage0Data(self.width)
860
861 def ospec(self):
862 return FPAddStage1Data(self.width)
863
864 def setup(self, m, in_tot, in_z):
865 """ links module to inputs and outputs
866 """
867 m.submodules.add1 = self
868 m.submodules.add1_out_overflow = self.o.of
869
870 m.d.comb += self.i.z.eq(in_z)
871 m.d.comb += self.i.tot.eq(in_tot)
872
873 def elaborate(self, platform):
874 m = Module()
875 #m.submodules.norm1_in_overflow = self.in_of
876 #m.submodules.norm1_out_overflow = self.out_of
877 #m.submodules.norm1_in_z = self.in_z
878 #m.submodules.norm1_out_z = self.out_z
879 m.d.comb += self.o.z.eq(self.i.z)
880 # tot[-1] (MSB) gets set when the sum overflows. shift result down
881 with m.If(self.i.tot[-1]):
882 m.d.comb += [
883 self.o.z.m.eq(self.i.tot[4:]),
884 self.o.of.m0.eq(self.i.tot[4]),
885 self.o.of.guard.eq(self.i.tot[3]),
886 self.o.of.round_bit.eq(self.i.tot[2]),
887 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
888 self.o.z.e.eq(self.i.z.e + 1)
889 ]
890 # tot[-1] (MSB) zero case
891 with m.Else():
892 m.d.comb += [
893 self.o.z.m.eq(self.i.tot[3:]),
894 self.o.of.m0.eq(self.i.tot[3]),
895 self.o.of.guard.eq(self.i.tot[2]),
896 self.o.of.round_bit.eq(self.i.tot[1]),
897 self.o.of.sticky.eq(self.i.tot[0])
898 ]
899 return m
900
901
902 class FPAddStage1(FPState, FPID):
903
904 def __init__(self, width, id_wid):
905 FPState.__init__(self, "add_1")
906 FPID.__init__(self, id_wid)
907 self.mod = FPAddStage1Mod(width)
908 self.out_z = FPNumBase(width, False)
909 self.out_of = Overflow()
910 self.norm_stb = Signal()
911
912 def setup(self, m, in_tot, in_z, in_mid):
913 """ links module to inputs and outputs
914 """
915 self.mod.setup(m, in_tot, in_z)
916
917 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
918
919 if self.in_mid is not None:
920 m.d.comb += self.in_mid.eq(in_mid)
921
922 def action(self, m):
923 self.idsync(m)
924 m.d.sync += self.out_of.eq(self.mod.out_of)
925 m.d.sync += self.out_z.eq(self.mod.out_z)
926 m.d.sync += self.norm_stb.eq(1)
927 m.next = "normalise_1"
928
929
930 class FPNormaliseModSingle:
931
932 def __init__(self, width):
933 self.width = width
934 self.in_z = FPNumBase(width, False)
935 self.out_z = FPNumBase(width, False)
936
937 def setup(self, m, in_z, out_z, modname):
938 """ links module to inputs and outputs
939 """
940 m.submodules.normalise = self
941 m.d.comb += self.in_z.eq(in_z)
942 m.d.comb += out_z.eq(self.out_z)
943
944 def elaborate(self, platform):
945 m = Module()
946
947 mwid = self.out_z.m_width+2
948 pe = PriorityEncoder(mwid)
949 m.submodules.norm_pe = pe
950
951 m.submodules.norm1_out_z = self.out_z
952 m.submodules.norm1_in_z = self.in_z
953
954 in_z = FPNumBase(self.width, False)
955 in_of = Overflow()
956 m.submodules.norm1_insel_z = in_z
957 m.submodules.norm1_insel_overflow = in_of
958
959 espec = (len(in_z.e), True)
960 ediff_n126 = Signal(espec, reset_less=True)
961 msr = MultiShiftRMerge(mwid, espec)
962 m.submodules.multishift_r = msr
963
964 m.d.comb += in_z.eq(self.in_z)
965 m.d.comb += in_of.eq(self.in_of)
966 # initialise out from in (overridden below)
967 m.d.comb += self.out_z.eq(in_z)
968 m.d.comb += self.out_of.eq(in_of)
969 # normalisation increase/decrease conditions
970 decrease = Signal(reset_less=True)
971 m.d.comb += decrease.eq(in_z.m_msbzero)
972 # decrease exponent
973 with m.If(decrease):
974 # *sigh* not entirely obvious: count leading zeros (clz)
975 # with a PriorityEncoder: to find from the MSB
976 # we reverse the order of the bits.
977 temp_m = Signal(mwid, reset_less=True)
978 temp_s = Signal(mwid+1, reset_less=True)
979 clz = Signal((len(in_z.e), True), reset_less=True)
980 m.d.comb += [
981 # cat round and guard bits back into the mantissa
982 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
983 pe.i.eq(temp_m[::-1]), # inverted
984 clz.eq(pe.o), # count zeros from MSB down
985 temp_s.eq(temp_m << clz), # shift mantissa UP
986 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
987 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
988 ]
989
990 return m
991
992
993 class FPNorm1ModSingle:
994
995 def __init__(self, width):
996 self.width = width
997 self.out_norm = Signal(reset_less=True)
998 self.in_z = FPNumBase(width, False)
999 self.in_of = Overflow()
1000 self.out_z = FPNumBase(width, False)
1001 self.out_of = Overflow()
1002
1003 def setup(self, m, in_z, in_of, out_z):
1004 """ links module to inputs and outputs
1005 """
1006 m.submodules.normalise_1 = self
1007
1008 m.d.comb += self.in_z.eq(in_z)
1009 m.d.comb += self.in_of.eq(in_of)
1010
1011 m.d.comb += out_z.eq(self.out_z)
1012
1013 def elaborate(self, platform):
1014 m = Module()
1015
1016 mwid = self.out_z.m_width+2
1017 pe = PriorityEncoder(mwid)
1018 m.submodules.norm_pe = pe
1019
1020 m.submodules.norm1_out_z = self.out_z
1021 m.submodules.norm1_out_overflow = self.out_of
1022 m.submodules.norm1_in_z = self.in_z
1023 m.submodules.norm1_in_overflow = self.in_of
1024
1025 in_z = FPNumBase(self.width, False)
1026 in_of = Overflow()
1027 m.submodules.norm1_insel_z = in_z
1028 m.submodules.norm1_insel_overflow = in_of
1029
1030 espec = (len(in_z.e), True)
1031 ediff_n126 = Signal(espec, reset_less=True)
1032 msr = MultiShiftRMerge(mwid, espec)
1033 m.submodules.multishift_r = msr
1034
1035 m.d.comb += in_z.eq(self.in_z)
1036 m.d.comb += in_of.eq(self.in_of)
1037 # initialise out from in (overridden below)
1038 m.d.comb += self.out_z.eq(in_z)
1039 m.d.comb += self.out_of.eq(in_of)
1040 # normalisation increase/decrease conditions
1041 decrease = Signal(reset_less=True)
1042 increase = Signal(reset_less=True)
1043 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1044 m.d.comb += increase.eq(in_z.exp_lt_n126)
1045 # decrease exponent
1046 with m.If(decrease):
1047 # *sigh* not entirely obvious: count leading zeros (clz)
1048 # with a PriorityEncoder: to find from the MSB
1049 # we reverse the order of the bits.
1050 temp_m = Signal(mwid, reset_less=True)
1051 temp_s = Signal(mwid+1, reset_less=True)
1052 clz = Signal((len(in_z.e), True), reset_less=True)
1053 # make sure that the amount to decrease by does NOT
1054 # go below the minimum non-INF/NaN exponent
1055 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
1056 in_z.exp_sub_n126)
1057 m.d.comb += [
1058 # cat round and guard bits back into the mantissa
1059 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1060 pe.i.eq(temp_m[::-1]), # inverted
1061 clz.eq(limclz), # count zeros from MSB down
1062 temp_s.eq(temp_m << clz), # shift mantissa UP
1063 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
1064 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
1065 self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
1066 # overflow in bits 0..1: got shifted too (leave sticky)
1067 self.out_of.guard.eq(temp_s[1]), # guard
1068 self.out_of.round_bit.eq(temp_s[0]), # round
1069 ]
1070 # increase exponent
1071 with m.Elif(increase):
1072 temp_m = Signal(mwid+1, reset_less=True)
1073 m.d.comb += [
1074 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
1075 in_z.m)),
1076 ediff_n126.eq(in_z.N126 - in_z.e),
1077 # connect multi-shifter to inp/out mantissa (and ediff)
1078 msr.inp.eq(temp_m),
1079 msr.diff.eq(ediff_n126),
1080 self.out_z.m.eq(msr.m[3:]),
1081 self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
1082 # overflow in bits 0..1: got shifted too (leave sticky)
1083 self.out_of.guard.eq(temp_s[2]), # guard
1084 self.out_of.round_bit.eq(temp_s[1]), # round
1085 self.out_of.sticky.eq(temp_s[0]), # sticky
1086 self.out_z.e.eq(in_z.e + ediff_n126),
1087 ]
1088
1089 return m
1090
1091
1092 class FPNorm1ModMulti:
1093
1094 def __init__(self, width, single_cycle=True):
1095 self.width = width
1096 self.in_select = Signal(reset_less=True)
1097 self.in_z = FPNumBase(width, False)
1098 self.in_of = Overflow()
1099 self.temp_z = FPNumBase(width, False)
1100 self.temp_of = Overflow()
1101 self.out_z = FPNumBase(width, False)
1102 self.out_of = Overflow()
1103
1104 def elaborate(self, platform):
1105 m = Module()
1106
1107 m.submodules.norm1_out_z = self.out_z
1108 m.submodules.norm1_out_overflow = self.out_of
1109 m.submodules.norm1_temp_z = self.temp_z
1110 m.submodules.norm1_temp_of = self.temp_of
1111 m.submodules.norm1_in_z = self.in_z
1112 m.submodules.norm1_in_overflow = self.in_of
1113
1114 in_z = FPNumBase(self.width, False)
1115 in_of = Overflow()
1116 m.submodules.norm1_insel_z = in_z
1117 m.submodules.norm1_insel_overflow = in_of
1118
1119 # select which of temp or in z/of to use
1120 with m.If(self.in_select):
1121 m.d.comb += in_z.eq(self.in_z)
1122 m.d.comb += in_of.eq(self.in_of)
1123 with m.Else():
1124 m.d.comb += in_z.eq(self.temp_z)
1125 m.d.comb += in_of.eq(self.temp_of)
1126 # initialise out from in (overridden below)
1127 m.d.comb += self.out_z.eq(in_z)
1128 m.d.comb += self.out_of.eq(in_of)
1129 # normalisation increase/decrease conditions
1130 decrease = Signal(reset_less=True)
1131 increase = Signal(reset_less=True)
1132 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1133 m.d.comb += increase.eq(in_z.exp_lt_n126)
1134 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1135 # decrease exponent
1136 with m.If(decrease):
1137 m.d.comb += [
1138 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
1139 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1140 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1141 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1142 self.out_of.round_bit.eq(0), # reset round bit
1143 self.out_of.m0.eq(in_of.guard),
1144 ]
1145 # increase exponent
1146 with m.Elif(increase):
1147 m.d.comb += [
1148 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
1149 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1150 self.out_of.guard.eq(in_z.m[0]),
1151 self.out_of.m0.eq(in_z.m[1]),
1152 self.out_of.round_bit.eq(in_of.guard),
1153 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1154 ]
1155
1156 return m
1157
1158
1159 class FPNorm1Single(FPState, FPID):
1160
1161 def __init__(self, width, id_wid, single_cycle=True):
1162 FPID.__init__(self, id_wid)
1163 FPState.__init__(self, "normalise_1")
1164 self.mod = FPNorm1ModSingle(width)
1165 self.out_norm = Signal(reset_less=True)
1166 self.out_z = FPNumBase(width)
1167 self.out_roundz = Signal(reset_less=True)
1168
1169 def setup(self, m, in_z, in_of, in_mid):
1170 """ links module to inputs and outputs
1171 """
1172 self.mod.setup(m, in_z, in_of, self.out_z)
1173
1174 if self.in_mid is not None:
1175 m.d.comb += self.in_mid.eq(in_mid)
1176
1177 def action(self, m):
1178 self.idsync(m)
1179 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1180 m.next = "round"
1181
1182
1183 class FPNorm1Multi(FPState, FPID):
1184
1185 def __init__(self, width, id_wid):
1186 FPID.__init__(self, id_wid)
1187 FPState.__init__(self, "normalise_1")
1188 self.mod = FPNorm1ModMulti(width)
1189 self.stb = Signal(reset_less=True)
1190 self.ack = Signal(reset=0, reset_less=True)
1191 self.out_norm = Signal(reset_less=True)
1192 self.in_accept = Signal(reset_less=True)
1193 self.temp_z = FPNumBase(width)
1194 self.temp_of = Overflow()
1195 self.out_z = FPNumBase(width)
1196 self.out_roundz = Signal(reset_less=True)
1197
1198 def setup(self, m, in_z, in_of, norm_stb, in_mid):
1199 """ links module to inputs and outputs
1200 """
1201 self.mod.setup(m, in_z, in_of, norm_stb,
1202 self.in_accept, self.temp_z, self.temp_of,
1203 self.out_z, self.out_norm)
1204
1205 m.d.comb += self.stb.eq(norm_stb)
1206 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1207
1208 if self.in_mid is not None:
1209 m.d.comb += self.in_mid.eq(in_mid)
1210
1211 def action(self, m):
1212 self.idsync(m)
1213 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1214 m.d.sync += self.temp_of.eq(self.mod.out_of)
1215 m.d.sync += self.temp_z.eq(self.out_z)
1216 with m.If(self.out_norm):
1217 with m.If(self.in_accept):
1218 m.d.sync += [
1219 self.ack.eq(1),
1220 ]
1221 with m.Else():
1222 m.d.sync += self.ack.eq(0)
1223 with m.Else():
1224 # normalisation not required (or done).
1225 m.next = "round"
1226 m.d.sync += self.ack.eq(1)
1227 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1228
1229
1230 class FPNormToPack(FPState, FPID):
1231
1232 def __init__(self, width, id_wid):
1233 FPID.__init__(self, id_wid)
1234 FPState.__init__(self, "normalise_1")
1235 self.width = width
1236
1237 def setup(self, m, in_z, in_of, in_mid):
1238 """ links module to inputs and outputs
1239 """
1240
1241 # Normalisation (chained to input in_z+in_of)
1242 nmod = FPNorm1ModSingle(self.width)
1243 n_out_z = FPNumBase(self.width)
1244 n_out_roundz = Signal(reset_less=True)
1245 nmod.setup(m, in_z, in_of, n_out_z)
1246
1247 # Rounding (chained to normalisation)
1248 rmod = FPRoundMod(self.width)
1249 r_out_z = FPNumBase(self.width)
1250 rmod.setup(m, n_out_z, n_out_roundz)
1251 m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
1252 m.d.comb += r_out_z.eq(rmod.out_z)
1253
1254 # Corrections (chained to rounding)
1255 cmod = FPCorrectionsMod(self.width)
1256 c_out_z = FPNumBase(self.width)
1257 cmod.setup(m, r_out_z)
1258 m.d.comb += c_out_z.eq(cmod.out_z)
1259
1260 # Pack (chained to corrections)
1261 self.pmod = FPPackMod(self.width)
1262 self.out_z = FPNumBase(self.width)
1263 self.pmod.setup(m, c_out_z)
1264
1265 # Multiplex ID
1266 if self.in_mid is not None:
1267 m.d.comb += self.in_mid.eq(in_mid)
1268
1269 def action(self, m):
1270 self.idsync(m) # copies incoming ID to outgoing
1271 m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
1272 m.next = "pack_put_z"
1273
1274
1275 class FPRoundMod:
1276
1277 def __init__(self, width):
1278 self.in_roundz = Signal(reset_less=True)
1279 self.in_z = FPNumBase(width, False)
1280 self.out_z = FPNumBase(width, False)
1281
1282 def setup(self, m, in_z, roundz):
1283 m.submodules.roundz = self
1284
1285 m.d.comb += self.in_z.eq(in_z)
1286 m.d.comb += self.in_roundz.eq(roundz)
1287
1288 def elaborate(self, platform):
1289 m = Module()
1290 m.d.comb += self.out_z.eq(self.in_z)
1291 with m.If(self.in_roundz):
1292 m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
1293 with m.If(self.in_z.m == self.in_z.m1s): # all 1s
1294 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
1295 return m
1296
1297
1298 class FPRound(FPState, FPID):
1299
1300 def __init__(self, width, id_wid):
1301 FPState.__init__(self, "round")
1302 FPID.__init__(self, id_wid)
1303 self.mod = FPRoundMod(width)
1304 self.out_z = FPNumBase(width)
1305
1306 def setup(self, m, in_z, roundz, in_mid):
1307 """ links module to inputs and outputs
1308 """
1309 self.mod.setup(m, in_z, roundz)
1310
1311 if self.in_mid is not None:
1312 m.d.comb += self.in_mid.eq(in_mid)
1313
1314 def action(self, m):
1315 self.idsync(m)
1316 m.d.sync += self.out_z.eq(self.mod.out_z)
1317 m.next = "corrections"
1318
1319
1320 class FPCorrectionsMod:
1321
1322 def __init__(self, width):
1323 self.in_z = FPNumOut(width, False)
1324 self.out_z = FPNumOut(width, False)
1325
1326 def setup(self, m, in_z):
1327 """ links module to inputs and outputs
1328 """
1329 m.submodules.corrections = self
1330 m.d.comb += self.in_z.eq(in_z)
1331
1332 def elaborate(self, platform):
1333 m = Module()
1334 m.submodules.corr_in_z = self.in_z
1335 m.submodules.corr_out_z = self.out_z
1336 m.d.comb += self.out_z.eq(self.in_z)
1337 with m.If(self.in_z.is_denormalised):
1338 m.d.comb += self.out_z.e.eq(self.in_z.N127)
1339 return m
1340
1341
1342 class FPCorrections(FPState, FPID):
1343
1344 def __init__(self, width, id_wid):
1345 FPState.__init__(self, "corrections")
1346 FPID.__init__(self, id_wid)
1347 self.mod = FPCorrectionsMod(width)
1348 self.out_z = FPNumBase(width)
1349
1350 def setup(self, m, in_z, in_mid):
1351 """ links module to inputs and outputs
1352 """
1353 self.mod.setup(m, in_z)
1354 if self.in_mid is not None:
1355 m.d.comb += self.in_mid.eq(in_mid)
1356
1357 def action(self, m):
1358 self.idsync(m)
1359 m.d.sync += self.out_z.eq(self.mod.out_z)
1360 m.next = "pack"
1361
1362
1363 class FPPackMod:
1364
1365 def __init__(self, width):
1366 self.in_z = FPNumOut(width, False)
1367 self.out_z = FPNumOut(width, False)
1368
1369 def setup(self, m, in_z):
1370 """ links module to inputs and outputs
1371 """
1372 m.submodules.pack = self
1373 m.d.comb += self.in_z.eq(in_z)
1374
1375 def elaborate(self, platform):
1376 m = Module()
1377 m.submodules.pack_in_z = self.in_z
1378 with m.If(self.in_z.is_overflowed):
1379 m.d.comb += self.out_z.inf(self.in_z.s)
1380 with m.Else():
1381 m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
1382 return m
1383
1384
1385 class FPPack(FPState, FPID):
1386
1387 def __init__(self, width, id_wid):
1388 FPState.__init__(self, "pack")
1389 FPID.__init__(self, id_wid)
1390 self.mod = FPPackMod(width)
1391 self.out_z = FPNumOut(width, False)
1392
1393 def setup(self, m, in_z, in_mid):
1394 """ links module to inputs and outputs
1395 """
1396 self.mod.setup(m, in_z)
1397 if self.in_mid is not None:
1398 m.d.comb += self.in_mid.eq(in_mid)
1399
1400 def action(self, m):
1401 self.idsync(m)
1402 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1403 m.next = "pack_put_z"
1404
1405
1406 class FPPutZ(FPState):
1407
1408 def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1409 FPState.__init__(self, state)
1410 if to_state is None:
1411 to_state = "get_ops"
1412 self.to_state = to_state
1413 self.in_z = in_z
1414 self.out_z = out_z
1415 self.in_mid = in_mid
1416 self.out_mid = out_mid
1417
1418 def action(self, m):
1419 if self.in_mid is not None:
1420 m.d.sync += self.out_mid.eq(self.in_mid)
1421 m.d.sync += [
1422 self.out_z.v.eq(self.in_z.v)
1423 ]
1424 with m.If(self.out_z.stb & self.out_z.ack):
1425 m.d.sync += self.out_z.stb.eq(0)
1426 m.next = self.to_state
1427 with m.Else():
1428 m.d.sync += self.out_z.stb.eq(1)
1429
1430
1431 class FPPutZIdx(FPState):
1432
1433 def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1434 FPState.__init__(self, state)
1435 if to_state is None:
1436 to_state = "get_ops"
1437 self.to_state = to_state
1438 self.in_z = in_z
1439 self.out_zs = out_zs
1440 self.in_mid = in_mid
1441
1442 def action(self, m):
1443 outz_stb = Signal(reset_less=True)
1444 outz_ack = Signal(reset_less=True)
1445 m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1446 outz_ack.eq(self.out_zs[self.in_mid].ack),
1447 ]
1448 m.d.sync += [
1449 self.out_zs[self.in_mid].v.eq(self.in_z.v)
1450 ]
1451 with m.If(outz_stb & outz_ack):
1452 m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1453 m.next = self.to_state
1454 with m.Else():
1455 m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1456
1457
1458 class FPADDBaseMod(FPID):
1459
1460 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1461 """ IEEE754 FP Add
1462
1463 * width: bit-width of IEEE754. supported: 16, 32, 64
1464 * id_wid: an identifier that is sync-connected to the input
1465 * single_cycle: True indicates each stage to complete in 1 clock
1466 * compact: True indicates a reduced number of stages
1467 """
1468 FPID.__init__(self, id_wid)
1469 self.width = width
1470 self.single_cycle = single_cycle
1471 self.compact = compact
1472
1473 self.in_t = Trigger()
1474 self.in_a = Signal(width)
1475 self.in_b = Signal(width)
1476 self.out_z = FPOp(width)
1477
1478 self.states = []
1479
1480 def add_state(self, state):
1481 self.states.append(state)
1482 return state
1483
1484 def get_fragment(self, platform=None):
1485 """ creates the HDL code-fragment for FPAdd
1486 """
1487 m = Module()
1488 m.submodules.out_z = self.out_z
1489 m.submodules.in_t = self.in_t
1490 if self.compact:
1491 self.get_compact_fragment(m, platform)
1492 else:
1493 self.get_longer_fragment(m, platform)
1494
1495 with m.FSM() as fsm:
1496
1497 for state in self.states:
1498 with m.State(state.state_from):
1499 state.action(m)
1500
1501 return m
1502
1503 def get_longer_fragment(self, m, platform=None):
1504
1505 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1506 self.in_a, self.in_b, self.width))
1507 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1508 a = get.out_op1
1509 b = get.out_op2
1510
1511 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1512 sc.setup(m, a, b, self.in_mid)
1513
1514 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1515 dn.setup(m, a, b, sc.in_mid)
1516
1517 if self.single_cycle:
1518 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1519 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1520 else:
1521 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1522 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1523
1524 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1525 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1526
1527 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1528 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1529
1530 if self.single_cycle:
1531 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1532 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1533 else:
1534 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1535 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1536
1537 rn = self.add_state(FPRound(self.width, self.id_wid))
1538 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1539
1540 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1541 cor.setup(m, rn.out_z, rn.in_mid)
1542
1543 pa = self.add_state(FPPack(self.width, self.id_wid))
1544 pa.setup(m, cor.out_z, rn.in_mid)
1545
1546 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1547 pa.in_mid, self.out_mid))
1548
1549 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1550 pa.in_mid, self.out_mid))
1551
1552 def get_compact_fragment(self, m, platform=None):
1553
1554 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1555 self.in_a, self.in_b, self.width))
1556 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1557 a = get.out_op1
1558 b = get.out_op2
1559
1560 sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1561 sc.setup(m, a, b, self.in_mid)
1562
1563 alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1564 alm.setup(m, sc.o.a, sc.o.b, sc.in_mid)
1565
1566 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1567 n1.setup(m, alm.a1o.z, alm.a1o.of, alm.in_mid)
1568
1569 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
1570 n1.in_mid, self.out_mid))
1571
1572 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1573 sc.in_mid, self.out_mid))
1574
1575
1576 class FPADDBase(FPState, FPID):
1577
1578 def __init__(self, width, id_wid=None, single_cycle=False):
1579 """ IEEE754 FP Add
1580
1581 * width: bit-width of IEEE754. supported: 16, 32, 64
1582 * id_wid: an identifier that is sync-connected to the input
1583 * single_cycle: True indicates each stage to complete in 1 clock
1584 """
1585 FPID.__init__(self, id_wid)
1586 FPState.__init__(self, "fpadd")
1587 self.width = width
1588 self.single_cycle = single_cycle
1589 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1590
1591 self.in_t = Trigger()
1592 self.in_a = Signal(width)
1593 self.in_b = Signal(width)
1594 #self.out_z = FPOp(width)
1595
1596 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1597 self.in_accept = Signal(reset_less=True)
1598 self.add_stb = Signal(reset_less=True)
1599 self.add_ack = Signal(reset=0, reset_less=True)
1600
1601 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1602 self.out_z = out_z
1603 self.out_mid = out_mid
1604 m.d.comb += [self.in_a.eq(a),
1605 self.in_b.eq(b),
1606 self.mod.in_a.eq(self.in_a),
1607 self.mod.in_b.eq(self.in_b),
1608 self.in_mid.eq(in_mid),
1609 self.mod.in_mid.eq(self.in_mid),
1610 self.z_done.eq(self.mod.out_z.trigger),
1611 #self.add_stb.eq(add_stb),
1612 self.mod.in_t.stb.eq(self.in_t.stb),
1613 self.in_t.ack.eq(self.mod.in_t.ack),
1614 self.out_mid.eq(self.mod.out_mid),
1615 self.out_z.v.eq(self.mod.out_z.v),
1616 self.out_z.stb.eq(self.mod.out_z.stb),
1617 self.mod.out_z.ack.eq(self.out_z.ack),
1618 ]
1619
1620 m.d.sync += self.add_stb.eq(add_stb)
1621 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1622 m.d.sync += self.out_z.ack.eq(0) # likewise
1623 #m.d.sync += self.in_t.stb.eq(0)
1624
1625 m.submodules.fpadd = self.mod
1626
1627 def action(self, m):
1628
1629 # in_accept is set on incoming strobe HIGH and ack LOW.
1630 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1631
1632 #with m.If(self.in_t.ack):
1633 # m.d.sync += self.in_t.stb.eq(0)
1634 with m.If(~self.z_done):
1635 # not done: test for accepting an incoming operand pair
1636 with m.If(self.in_accept):
1637 m.d.sync += [
1638 self.add_ack.eq(1), # acknowledge receipt...
1639 self.in_t.stb.eq(1), # initiate add
1640 ]
1641 with m.Else():
1642 m.d.sync += [self.add_ack.eq(0),
1643 self.in_t.stb.eq(0),
1644 self.out_z.ack.eq(1),
1645 ]
1646 with m.Else():
1647 # done: acknowledge, and write out id and value
1648 m.d.sync += [self.add_ack.eq(1),
1649 self.in_t.stb.eq(0)
1650 ]
1651 m.next = "put_z"
1652
1653 return
1654
1655 if self.in_mid is not None:
1656 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1657
1658 m.d.sync += [
1659 self.out_z.v.eq(self.mod.out_z.v)
1660 ]
1661 # move to output state on detecting z ack
1662 with m.If(self.out_z.trigger):
1663 m.d.sync += self.out_z.stb.eq(0)
1664 m.next = "put_z"
1665 with m.Else():
1666 m.d.sync += self.out_z.stb.eq(1)
1667
1668 class ResArray:
1669 def __init__(self, width, id_wid):
1670 self.width = width
1671 self.id_wid = id_wid
1672 res = []
1673 for i in range(rs_sz):
1674 out_z = FPOp(width)
1675 out_z.name = "out_z_%d" % i
1676 res.append(out_z)
1677 self.res = Array(res)
1678 self.in_z = FPOp(width)
1679 self.in_mid = Signal(self.id_wid, reset_less=True)
1680
1681 def setup(self, m, in_z, in_mid):
1682 m.d.comb += [self.in_z.eq(in_z),
1683 self.in_mid.eq(in_mid)]
1684
1685 def get_fragment(self, platform=None):
1686 """ creates the HDL code-fragment for FPAdd
1687 """
1688 m = Module()
1689 m.submodules.res_in_z = self.in_z
1690 m.submodules += self.res
1691
1692 return m
1693
1694 def ports(self):
1695 res = []
1696 for z in self.res:
1697 res += z.ports()
1698 return res
1699
1700
1701 class FPADD(FPID):
1702 """ FPADD: stages as follows:
1703
1704 FPGetOp (a)
1705 |
1706 FPGetOp (b)
1707 |
1708 FPAddBase---> FPAddBaseMod
1709 | |
1710 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1711
1712 FPAddBase is tricky: it is both a stage and *has* stages.
1713 Connection to FPAddBaseMod therefore requires an in stb/ack
1714 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1715 needs to be the thing that raises the incoming stb.
1716 """
1717
1718 def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1719 """ IEEE754 FP Add
1720
1721 * width: bit-width of IEEE754. supported: 16, 32, 64
1722 * id_wid: an identifier that is sync-connected to the input
1723 * single_cycle: True indicates each stage to complete in 1 clock
1724 """
1725 self.width = width
1726 self.id_wid = id_wid
1727 self.single_cycle = single_cycle
1728
1729 #self.out_z = FPOp(width)
1730 self.ids = FPID(id_wid)
1731
1732 rs = []
1733 for i in range(rs_sz):
1734 in_a = FPOp(width)
1735 in_b = FPOp(width)
1736 in_a.name = "in_a_%d" % i
1737 in_b.name = "in_b_%d" % i
1738 rs.append((in_a, in_b))
1739 self.rs = Array(rs)
1740
1741 res = []
1742 for i in range(rs_sz):
1743 out_z = FPOp(width)
1744 out_z.name = "out_z_%d" % i
1745 res.append(out_z)
1746 self.res = Array(res)
1747
1748 self.states = []
1749
1750 def add_state(self, state):
1751 self.states.append(state)
1752 return state
1753
1754 def get_fragment(self, platform=None):
1755 """ creates the HDL code-fragment for FPAdd
1756 """
1757 m = Module()
1758 m.submodules += self.rs
1759
1760 in_a = self.rs[0][0]
1761 in_b = self.rs[0][1]
1762
1763 out_z = FPOp(self.width)
1764 out_mid = Signal(self.id_wid, reset_less=True)
1765 m.submodules.out_z = out_z
1766
1767 geta = self.add_state(FPGetOp("get_a", "get_b",
1768 in_a, self.width))
1769 geta.setup(m, in_a)
1770 a = geta.out_op
1771
1772 getb = self.add_state(FPGetOp("get_b", "fpadd",
1773 in_b, self.width))
1774 getb.setup(m, in_b)
1775 b = getb.out_op
1776
1777 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1778 ab = self.add_state(ab)
1779 ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1780 out_z, out_mid)
1781
1782 pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1783 out_mid, "get_a"))
1784
1785 with m.FSM() as fsm:
1786
1787 for state in self.states:
1788 with m.State(state.state_from):
1789 state.action(m)
1790
1791 return m
1792
1793
1794 if __name__ == "__main__":
1795 if True:
1796 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1797 main(alu, ports=alu.rs[0][0].ports() + \
1798 alu.rs[0][1].ports() + \
1799 alu.res[0].ports() + \
1800 [alu.ids.in_mid, alu.ids.out_mid])
1801 else:
1802 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1803 main(alu, ports=[alu.in_a, alu.in_b] + \
1804 alu.in_t.ports() + \
1805 alu.out_z.ports() + \
1806 [alu.in_mid, alu.out_mid])
1807
1808
1809 # works... but don't use, just do "python fname.py convert -t v"
1810 #print (verilog.convert(alu, ports=[
1811 # ports=alu.in_a.ports() + \
1812 # alu.in_b.ports() + \
1813 # alu.out_z.ports())