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use ospec to make clone of out_z
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 #from fpbase import FPNumShiftMultiRight
13
14
15 class FPState(FPBase):
16 def __init__(self, state_from):
17 self.state_from = state_from
18
19 def set_inputs(self, inputs):
20 self.inputs = inputs
21 for k,v in inputs.items():
22 setattr(self, k, v)
23
24 def set_outputs(self, outputs):
25 self.outputs = outputs
26 for k,v in outputs.items():
27 setattr(self, k, v)
28
29
30 class FPGetSyncOpsMod:
31 def __init__(self, width, num_ops=2):
32 self.width = width
33 self.num_ops = num_ops
34 inops = []
35 outops = []
36 for i in range(num_ops):
37 inops.append(Signal(width, reset_less=True))
38 outops.append(Signal(width, reset_less=True))
39 self.in_op = inops
40 self.out_op = outops
41 self.stb = Signal(num_ops)
42 self.ack = Signal()
43 self.ready = Signal(reset_less=True)
44 self.out_decode = Signal(reset_less=True)
45
46 def elaborate(self, platform):
47 m = Module()
48 m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
49 m.d.comb += self.out_decode.eq(self.ack & self.ready)
50 with m.If(self.out_decode):
51 for i in range(self.num_ops):
52 m.d.comb += [
53 self.out_op[i].eq(self.in_op[i]),
54 ]
55 return m
56
57 def ports(self):
58 return self.in_op + self.out_op + [self.stb, self.ack]
59
60
61 class FPOps(Trigger):
62 def __init__(self, width, num_ops):
63 Trigger.__init__(self)
64 self.width = width
65 self.num_ops = num_ops
66
67 res = []
68 for i in range(num_ops):
69 res.append(Signal(width))
70 self.v = Array(res)
71
72 def ports(self):
73 res = []
74 for i in range(self.num_ops):
75 res.append(self.v[i])
76 res.append(self.ack)
77 res.append(self.stb)
78 return res
79
80
81 class InputGroup:
82 def __init__(self, width, num_ops=2, num_rows=4):
83 self.width = width
84 self.num_ops = num_ops
85 self.num_rows = num_rows
86 self.mmax = int(log(self.num_rows) / log(2))
87 self.rs = []
88 self.mid = Signal(self.mmax, reset_less=True) # multiplex id
89 for i in range(num_rows):
90 self.rs.append(FPGetSyncOpsMod(width, num_ops))
91 self.rs = Array(self.rs)
92
93 self.out_op = FPOps(width, num_ops)
94
95 def elaborate(self, platform):
96 m = Module()
97
98 pe = PriorityEncoder(self.num_rows)
99 m.submodules.selector = pe
100 m.submodules.out_op = self.out_op
101 m.submodules += self.rs
102
103 # connect priority encoder
104 in_ready = []
105 for i in range(self.num_rows):
106 in_ready.append(self.rs[i].ready)
107 m.d.comb += pe.i.eq(Cat(*in_ready))
108
109 active = Signal(reset_less=True)
110 out_en = Signal(reset_less=True)
111 m.d.comb += active.eq(~pe.n) # encoder active
112 m.d.comb += out_en.eq(active & self.out_op.trigger)
113
114 # encoder active: ack relevant input, record MID, pass output
115 with m.If(out_en):
116 rs = self.rs[pe.o]
117 m.d.sync += self.mid.eq(pe.o)
118 m.d.sync += rs.ack.eq(0)
119 m.d.sync += self.out_op.stb.eq(0)
120 for j in range(self.num_ops):
121 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
122 with m.Else():
123 m.d.sync += self.out_op.stb.eq(1)
124 # acks all default to zero
125 for i in range(self.num_rows):
126 m.d.sync += self.rs[i].ack.eq(1)
127
128 return m
129
130 def ports(self):
131 res = []
132 for i in range(self.num_rows):
133 inop = self.rs[i]
134 res += inop.in_op + [inop.stb]
135 return self.out_op.ports() + res + [self.mid]
136
137
138 class FPGetOpMod:
139 def __init__(self, width):
140 self.in_op = FPOp(width)
141 self.out_op = Signal(width)
142 self.out_decode = Signal(reset_less=True)
143
144 def elaborate(self, platform):
145 m = Module()
146 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
147 m.submodules.get_op_in = self.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m.If(self.out_decode):
150 m.d.comb += [
151 self.out_op.eq(self.in_op.v),
152 ]
153 return m
154
155
156 class FPGetOp(FPState):
157 """ gets operand
158 """
159
160 def __init__(self, in_state, out_state, in_op, width):
161 FPState.__init__(self, in_state)
162 self.out_state = out_state
163 self.mod = FPGetOpMod(width)
164 self.in_op = in_op
165 self.out_op = Signal(width)
166 self.out_decode = Signal(reset_less=True)
167
168 def setup(self, m, in_op):
169 """ links module to inputs and outputs
170 """
171 setattr(m.submodules, self.state_from, self.mod)
172 m.d.comb += self.mod.in_op.eq(in_op)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m.d.comb += self.out_decode.eq(self.mod.out_decode)
175
176 def action(self, m):
177 with m.If(self.out_decode):
178 m.next = self.out_state
179 m.d.sync += [
180 self.in_op.ack.eq(0),
181 self.out_op.eq(self.mod.out_op)
182 ]
183 with m.Else():
184 m.d.sync += self.in_op.ack.eq(1)
185
186
187 class FPGet2OpMod(Trigger):
188 def __init__(self, width):
189 Trigger.__init__(self)
190 self.in_op1 = Signal(width, reset_less=True)
191 self.in_op2 = Signal(width, reset_less=True)
192 self.out_op1 = FPNumIn(None, width)
193 self.out_op2 = FPNumIn(None, width)
194
195 def elaborate(self, platform):
196 m = Trigger.elaborate(self, platform)
197 #m.submodules.get_op_in = self.in_op
198 m.submodules.get_op1_out = self.out_op1
199 m.submodules.get_op2_out = self.out_op2
200 with m.If(self.trigger):
201 m.d.comb += [
202 self.out_op1.decode(self.in_op1),
203 self.out_op2.decode(self.in_op2),
204 ]
205 return m
206
207
208 class FPGet2Op(FPState):
209 """ gets operands
210 """
211
212 def __init__(self, in_state, out_state, in_op1, in_op2, width):
213 FPState.__init__(self, in_state)
214 self.out_state = out_state
215 self.mod = FPGet2OpMod(width)
216 self.in_op1 = in_op1
217 self.in_op2 = in_op2
218 self.out_op1 = FPNumIn(None, width)
219 self.out_op2 = FPNumIn(None, width)
220 self.in_stb = Signal(reset_less=True)
221 self.out_ack = Signal(reset_less=True)
222 self.out_decode = Signal(reset_less=True)
223
224 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
225 """ links module to inputs and outputs
226 """
227 m.submodules.get_ops = self.mod
228 m.d.comb += self.mod.in_op1.eq(in_op1)
229 m.d.comb += self.mod.in_op2.eq(in_op2)
230 m.d.comb += self.mod.stb.eq(in_stb)
231 m.d.comb += self.out_ack.eq(self.mod.ack)
232 m.d.comb += self.out_decode.eq(self.mod.trigger)
233 m.d.comb += in_ack.eq(self.mod.ack)
234
235 def action(self, m):
236 with m.If(self.out_decode):
237 m.next = self.out_state
238 m.d.sync += [
239 self.mod.ack.eq(0),
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self.out_op1.eq(self.mod.out_op1),
243 self.out_op2.eq(self.mod.out_op2)
244 ]
245 with m.Else():
246 m.d.sync += self.mod.ack.eq(1)
247
248 class FPNumBase2Ops:
249
250 def __init__(self, width):
251 self.a = FPNumBase(width)
252 self.b = FPNumBase(width)
253
254 def eq(self, i):
255 return [self.a.eq(i.a), self.a.eq(i.b)]
256
257
258 class FPAddSpecialCasesMod:
259 """ special cases: NaNs, infs, zeros, denormalised
260 NOTE: some of these are unique to add. see "Special Operations"
261 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
262 """
263
264 def __init__(self, width):
265 self.width = width
266 self.i = self.ispec()
267 self.out_z = self.ospec()
268 self.out_do_z = Signal(reset_less=True)
269
270 def ispec(self):
271 return FPNumBase2Ops(self.width)
272
273 def ospec(self):
274 return FPNumOut(self.width, False)
275
276 def setup(self, m, in_a, in_b, out_do_z):
277 """ links module to inputs and outputs
278 """
279 m.submodules.specialcases = self
280 m.d.comb += self.i.a.eq(in_a)
281 m.d.comb += self.i.b.eq(in_b)
282 m.d.comb += out_do_z.eq(self.out_do_z)
283
284 def elaborate(self, platform):
285 m = Module()
286
287 m.submodules.sc_in_a = self.i.a
288 m.submodules.sc_in_b = self.i.b
289 m.submodules.sc_out_z = self.out_z
290
291 s_nomatch = Signal()
292 m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
293
294 m_match = Signal()
295 m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
296
297 # if a is NaN or b is NaN return NaN
298 with m.If(self.i.a.is_nan | self.i.b.is_nan):
299 m.d.comb += self.out_do_z.eq(1)
300 m.d.comb += self.out_z.nan(0)
301
302 # XXX WEIRDNESS for FP16 non-canonical NaN handling
303 # under review
304
305 ## if a is zero and b is NaN return -b
306 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
307 # m.d.comb += self.out_do_z.eq(1)
308 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
309
310 ## if b is zero and a is NaN return -a
311 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
312 # m.d.comb += self.out_do_z.eq(1)
313 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
314
315 ## if a is -zero and b is NaN return -b
316 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
317 # m.d.comb += self.out_do_z.eq(1)
318 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
319
320 ## if b is -zero and a is NaN return -a
321 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
322 # m.d.comb += self.out_do_z.eq(1)
323 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
324
325 # if a is inf return inf (or NaN)
326 with m.Elif(self.i.a.is_inf):
327 m.d.comb += self.out_do_z.eq(1)
328 m.d.comb += self.out_z.inf(self.i.a.s)
329 # if a is inf and signs don't match return NaN
330 with m.If(self.i.b.exp_128 & s_nomatch):
331 m.d.comb += self.out_z.nan(0)
332
333 # if b is inf return inf
334 with m.Elif(self.i.b.is_inf):
335 m.d.comb += self.out_do_z.eq(1)
336 m.d.comb += self.out_z.inf(self.i.b.s)
337
338 # if a is zero and b zero return signed-a/b
339 with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
340 m.d.comb += self.out_do_z.eq(1)
341 m.d.comb += self.out_z.create(self.i.a.s & self.i.b.s,
342 self.i.b.e,
343 self.i.b.m[3:-1])
344
345 # if a is zero return b
346 with m.Elif(self.i.a.is_zero):
347 m.d.comb += self.out_do_z.eq(1)
348 m.d.comb += self.out_z.create(self.i.b.s, self.i.b.e,
349 self.i.b.m[3:-1])
350
351 # if b is zero return a
352 with m.Elif(self.i.b.is_zero):
353 m.d.comb += self.out_do_z.eq(1)
354 m.d.comb += self.out_z.create(self.i.a.s, self.i.a.e,
355 self.i.a.m[3:-1])
356
357 # if a equal to -b return zero (+ve zero)
358 with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
359 m.d.comb += self.out_do_z.eq(1)
360 m.d.comb += self.out_z.zero(0)
361
362 # Denormalised Number checks
363 with m.Else():
364 m.d.comb += self.out_do_z.eq(0)
365
366 return m
367
368
369 class FPID:
370 def __init__(self, id_wid):
371 self.id_wid = id_wid
372 if self.id_wid:
373 self.in_mid = Signal(id_wid, reset_less=True)
374 self.out_mid = Signal(id_wid, reset_less=True)
375 else:
376 self.in_mid = None
377 self.out_mid = None
378
379 def idsync(self, m):
380 if self.id_wid is not None:
381 m.d.sync += self.out_mid.eq(self.in_mid)
382
383
384 class FPAddSpecialCases(FPState, FPID):
385 """ special cases: NaNs, infs, zeros, denormalised
386 NOTE: some of these are unique to add. see "Special Operations"
387 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
388 """
389
390 def __init__(self, width, id_wid):
391 FPState.__init__(self, "special_cases")
392 FPID.__init__(self, id_wid)
393 self.mod = FPAddSpecialCasesMod(width)
394 self.out_z = self.mod.ospec()
395 self.out_do_z = Signal(reset_less=True)
396
397 def setup(self, m, in_a, in_b, in_mid):
398 """ links module to inputs and outputs
399 """
400 self.mod.setup(m, in_a, in_b, self.out_do_z)
401 if self.in_mid is not None:
402 m.d.comb += self.in_mid.eq(in_mid)
403
404 def action(self, m):
405 self.idsync(m)
406 with m.If(self.out_do_z):
407 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
408 m.next = "put_z"
409 with m.Else():
410 m.next = "denormalise"
411
412
413 class FPAddSpecialCasesDeNorm(FPState, FPID):
414 """ special cases: NaNs, infs, zeros, denormalised
415 NOTE: some of these are unique to add. see "Special Operations"
416 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
417 """
418
419 def __init__(self, width, id_wid):
420 FPState.__init__(self, "special_cases")
421 FPID.__init__(self, id_wid)
422 self.smod = FPAddSpecialCasesMod(width)
423 self.out_z = FPNumOut(width, False)
424 self.out_do_z = Signal(reset_less=True)
425
426 self.dmod = FPAddDeNormMod(width)
427 self.out_a = FPNumBase(width)
428 self.out_b = FPNumBase(width)
429
430 def setup(self, m, in_a, in_b, in_mid):
431 """ links module to inputs and outputs
432 """
433 self.smod.setup(m, in_a, in_b, self.out_do_z)
434 self.dmod.setup(m, in_a, in_b)
435 if self.in_mid is not None:
436 m.d.comb += self.in_mid.eq(in_mid)
437
438 def action(self, m):
439 self.idsync(m)
440 with m.If(self.out_do_z):
441 m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
442 m.next = "put_z"
443 with m.Else():
444 m.next = "align"
445 m.d.sync += self.out_a.eq(self.dmod.out_a)
446 m.d.sync += self.out_b.eq(self.dmod.out_b)
447
448
449 class FPAddDeNormMod(FPState):
450
451 def __init__(self, width):
452 self.in_a = FPNumBase(width)
453 self.in_b = FPNumBase(width)
454 self.out_a = FPNumBase(width)
455 self.out_b = FPNumBase(width)
456
457 def setup(self, m, in_a, in_b):
458 """ links module to inputs and outputs
459 """
460 m.submodules.denormalise = self
461 m.d.comb += self.in_a.eq(in_a)
462 m.d.comb += self.in_b.eq(in_b)
463
464 def elaborate(self, platform):
465 m = Module()
466 m.submodules.denorm_in_a = self.in_a
467 m.submodules.denorm_in_b = self.in_b
468 m.submodules.denorm_out_a = self.out_a
469 m.submodules.denorm_out_b = self.out_b
470 # hmmm, don't like repeating identical code
471 m.d.comb += self.out_a.eq(self.in_a)
472 with m.If(self.in_a.exp_n127):
473 m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
474 with m.Else():
475 m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
476
477 m.d.comb += self.out_b.eq(self.in_b)
478 with m.If(self.in_b.exp_n127):
479 m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
480 with m.Else():
481 m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
482
483 return m
484
485
486 class FPAddDeNorm(FPState, FPID):
487
488 def __init__(self, width, id_wid):
489 FPState.__init__(self, "denormalise")
490 FPID.__init__(self, id_wid)
491 self.mod = FPAddDeNormMod(width)
492 self.out_a = FPNumBase(width)
493 self.out_b = FPNumBase(width)
494
495 def setup(self, m, in_a, in_b, in_mid):
496 """ links module to inputs and outputs
497 """
498 self.mod.setup(m, in_a, in_b)
499 if self.in_mid is not None:
500 m.d.comb += self.in_mid.eq(in_mid)
501
502 def action(self, m):
503 self.idsync(m)
504 # Denormalised Number checks
505 m.next = "align"
506 m.d.sync += self.out_a.eq(self.mod.out_a)
507 m.d.sync += self.out_b.eq(self.mod.out_b)
508
509
510 class FPAddAlignMultiMod(FPState):
511
512 def __init__(self, width):
513 self.in_a = FPNumBase(width)
514 self.in_b = FPNumBase(width)
515 self.out_a = FPNumIn(None, width)
516 self.out_b = FPNumIn(None, width)
517 self.exp_eq = Signal(reset_less=True)
518
519 def elaborate(self, platform):
520 # This one however (single-cycle) will do the shift
521 # in one go.
522
523 m = Module()
524
525 m.submodules.align_in_a = self.in_a
526 m.submodules.align_in_b = self.in_b
527 m.submodules.align_out_a = self.out_a
528 m.submodules.align_out_b = self.out_b
529
530 # NOTE: this does *not* do single-cycle multi-shifting,
531 # it *STAYS* in the align state until exponents match
532
533 # exponent of a greater than b: shift b down
534 m.d.comb += self.exp_eq.eq(0)
535 m.d.comb += self.out_a.eq(self.in_a)
536 m.d.comb += self.out_b.eq(self.in_b)
537 agtb = Signal(reset_less=True)
538 altb = Signal(reset_less=True)
539 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
540 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
541 with m.If(agtb):
542 m.d.comb += self.out_b.shift_down(self.in_b)
543 # exponent of b greater than a: shift a down
544 with m.Elif(altb):
545 m.d.comb += self.out_a.shift_down(self.in_a)
546 # exponents equal: move to next stage.
547 with m.Else():
548 m.d.comb += self.exp_eq.eq(1)
549 return m
550
551
552 class FPAddAlignMulti(FPState, FPID):
553
554 def __init__(self, width, id_wid):
555 FPID.__init__(self, id_wid)
556 FPState.__init__(self, "align")
557 self.mod = FPAddAlignMultiMod(width)
558 self.out_a = FPNumIn(None, width)
559 self.out_b = FPNumIn(None, width)
560 self.exp_eq = Signal(reset_less=True)
561
562 def setup(self, m, in_a, in_b, in_mid):
563 """ links module to inputs and outputs
564 """
565 m.submodules.align = self.mod
566 m.d.comb += self.mod.in_a.eq(in_a)
567 m.d.comb += self.mod.in_b.eq(in_b)
568 #m.d.comb += self.out_a.eq(self.mod.out_a)
569 #m.d.comb += self.out_b.eq(self.mod.out_b)
570 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
571 if self.in_mid is not None:
572 m.d.comb += self.in_mid.eq(in_mid)
573
574 def action(self, m):
575 self.idsync(m)
576 m.d.sync += self.out_a.eq(self.mod.out_a)
577 m.d.sync += self.out_b.eq(self.mod.out_b)
578 with m.If(self.exp_eq):
579 m.next = "add_0"
580
581
582 class FPAddAlignSingleMod:
583
584 def __init__(self, width):
585 self.width = width
586 self.in_a = FPNumBase(width)
587 self.in_b = FPNumBase(width)
588 self.out_a = FPNumIn(None, width)
589 self.out_b = FPNumIn(None, width)
590
591 def setup(self, m, in_a, in_b):
592 """ links module to inputs and outputs
593 """
594 m.submodules.align = self
595 m.d.comb += self.in_a.eq(in_a)
596 m.d.comb += self.in_b.eq(in_b)
597
598 def elaborate(self, platform):
599 """ Aligns A against B or B against A, depending on which has the
600 greater exponent. This is done in a *single* cycle using
601 variable-width bit-shift
602
603 the shifter used here is quite expensive in terms of gates.
604 Mux A or B in (and out) into temporaries, as only one of them
605 needs to be aligned against the other
606 """
607 m = Module()
608
609 m.submodules.align_in_a = self.in_a
610 m.submodules.align_in_b = self.in_b
611 m.submodules.align_out_a = self.out_a
612 m.submodules.align_out_b = self.out_b
613
614 # temporary (muxed) input and output to be shifted
615 t_inp = FPNumBase(self.width)
616 t_out = FPNumIn(None, self.width)
617 espec = (len(self.in_a.e), True)
618 msr = MultiShiftRMerge(self.in_a.m_width, espec)
619 m.submodules.align_t_in = t_inp
620 m.submodules.align_t_out = t_out
621 m.submodules.multishift_r = msr
622
623 ediff = Signal(espec, reset_less=True)
624 ediffr = Signal(espec, reset_less=True)
625 tdiff = Signal(espec, reset_less=True)
626 elz = Signal(reset_less=True)
627 egz = Signal(reset_less=True)
628
629 # connect multi-shifter to t_inp/out mantissa (and tdiff)
630 m.d.comb += msr.inp.eq(t_inp.m)
631 m.d.comb += msr.diff.eq(tdiff)
632 m.d.comb += t_out.m.eq(msr.m)
633 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
634 m.d.comb += t_out.s.eq(t_inp.s)
635
636 m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
637 m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
638 m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
639 m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
640
641 # default: A-exp == B-exp, A and B untouched (fall through)
642 m.d.comb += self.out_a.eq(self.in_a)
643 m.d.comb += self.out_b.eq(self.in_b)
644 # only one shifter (muxed)
645 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
646 # exponent of a greater than b: shift b down
647 with m.If(egz):
648 m.d.comb += [t_inp.eq(self.in_b),
649 tdiff.eq(ediff),
650 self.out_b.eq(t_out),
651 self.out_b.s.eq(self.in_b.s), # whoops forgot sign
652 ]
653 # exponent of b greater than a: shift a down
654 with m.Elif(elz):
655 m.d.comb += [t_inp.eq(self.in_a),
656 tdiff.eq(ediffr),
657 self.out_a.eq(t_out),
658 self.out_a.s.eq(self.in_a.s), # whoops forgot sign
659 ]
660 return m
661
662
663 class FPAddAlignSingle(FPState, FPID):
664
665 def __init__(self, width, id_wid):
666 FPState.__init__(self, "align")
667 FPID.__init__(self, id_wid)
668 self.mod = FPAddAlignSingleMod(width)
669 self.out_a = FPNumIn(None, width)
670 self.out_b = FPNumIn(None, width)
671
672 def setup(self, m, in_a, in_b, in_mid):
673 """ links module to inputs and outputs
674 """
675 self.mod.setup(m, in_a, in_b)
676 if self.in_mid is not None:
677 m.d.comb += self.in_mid.eq(in_mid)
678
679 def action(self, m):
680 self.idsync(m)
681 # NOTE: could be done as comb
682 m.d.sync += self.out_a.eq(self.mod.out_a)
683 m.d.sync += self.out_b.eq(self.mod.out_b)
684 m.next = "add_0"
685
686
687 class FPAddAlignSingleAdd(FPState, FPID):
688
689 def __init__(self, width, id_wid):
690 FPState.__init__(self, "align")
691 FPID.__init__(self, id_wid)
692 self.mod = FPAddAlignSingleMod(width)
693 self.out_a = FPNumIn(None, width)
694 self.out_b = FPNumIn(None, width)
695
696 self.a0mod = FPAddStage0Mod(width)
697 self.a0_out_z = FPNumBase(width, False)
698 self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
699 self.a0_out_z = FPNumBase(width, False)
700
701 self.a1mod = FPAddStage1Mod(width)
702 self.out_z = FPNumBase(width, False)
703 self.out_of = Overflow()
704
705 def setup(self, m, in_a, in_b, in_mid):
706 """ links module to inputs and outputs
707 """
708 self.mod.setup(m, in_a, in_b)
709 m.d.comb += self.out_a.eq(self.mod.out_a)
710 m.d.comb += self.out_b.eq(self.mod.out_b)
711
712 self.a0mod.setup(m, self.out_a, self.out_b)
713 m.d.comb += self.a0_out_z.eq(self.a0mod.out_z)
714 m.d.comb += self.out_tot.eq(self.a0mod.out_tot)
715
716 self.a1mod.setup(m, self.out_tot, self.a0_out_z)
717
718 if self.in_mid is not None:
719 m.d.comb += self.in_mid.eq(in_mid)
720
721 def action(self, m):
722 self.idsync(m)
723 m.d.sync += self.out_of.eq(self.a1mod.out_of)
724 m.d.sync += self.out_z.eq(self.a1mod.out_z)
725 m.next = "normalise_1"
726
727
728 class FPAddStage0Mod:
729
730 def __init__(self, width):
731 self.in_a = FPNumBase(width)
732 self.in_b = FPNumBase(width)
733 self.in_z = FPNumBase(width, False)
734 self.out_z = FPNumBase(width, False)
735 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
736
737 def setup(self, m, in_a, in_b):
738 """ links module to inputs and outputs
739 """
740 m.submodules.add0 = self
741 m.d.comb += self.in_a.eq(in_a)
742 m.d.comb += self.in_b.eq(in_b)
743
744 def elaborate(self, platform):
745 m = Module()
746 m.submodules.add0_in_a = self.in_a
747 m.submodules.add0_in_b = self.in_b
748 m.submodules.add0_out_z = self.out_z
749
750 m.d.comb += self.out_z.e.eq(self.in_a.e)
751
752 # store intermediate tests (and zero-extended mantissas)
753 seq = Signal(reset_less=True)
754 mge = Signal(reset_less=True)
755 am0 = Signal(len(self.in_a.m)+1, reset_less=True)
756 bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
757 m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
758 mge.eq(self.in_a.m >= self.in_b.m),
759 am0.eq(Cat(self.in_a.m, 0)),
760 bm0.eq(Cat(self.in_b.m, 0))
761 ]
762 # same-sign (both negative or both positive) add mantissas
763 with m.If(seq):
764 m.d.comb += [
765 self.out_tot.eq(am0 + bm0),
766 self.out_z.s.eq(self.in_a.s)
767 ]
768 # a mantissa greater than b, use a
769 with m.Elif(mge):
770 m.d.comb += [
771 self.out_tot.eq(am0 - bm0),
772 self.out_z.s.eq(self.in_a.s)
773 ]
774 # b mantissa greater than a, use b
775 with m.Else():
776 m.d.comb += [
777 self.out_tot.eq(bm0 - am0),
778 self.out_z.s.eq(self.in_b.s)
779 ]
780 return m
781
782
783 class FPAddStage0(FPState, FPID):
784 """ First stage of add. covers same-sign (add) and subtract
785 special-casing when mantissas are greater or equal, to
786 give greatest accuracy.
787 """
788
789 def __init__(self, width, id_wid):
790 FPState.__init__(self, "add_0")
791 FPID.__init__(self, id_wid)
792 self.mod = FPAddStage0Mod(width)
793 self.out_z = FPNumBase(width, False)
794 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
795
796 def setup(self, m, in_a, in_b, in_mid):
797 """ links module to inputs and outputs
798 """
799 self.mod.setup(m, in_a, in_b)
800 if self.in_mid is not None:
801 m.d.comb += self.in_mid.eq(in_mid)
802
803 def action(self, m):
804 self.idsync(m)
805 # NOTE: these could be done as combinatorial (merge add0+add1)
806 m.d.sync += self.out_z.eq(self.mod.out_z)
807 m.d.sync += self.out_tot.eq(self.mod.out_tot)
808 m.next = "add_1"
809
810
811 class FPAddStage1Mod(FPState):
812 """ Second stage of add: preparation for normalisation.
813 detects when tot sum is too big (tot[27] is kinda a carry bit)
814 """
815
816 def __init__(self, width):
817 self.out_norm = Signal(reset_less=True)
818 self.in_z = FPNumBase(width, False)
819 self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
820 self.out_z = FPNumBase(width, False)
821 self.out_of = Overflow()
822
823 def setup(self, m, in_tot, in_z):
824 """ links module to inputs and outputs
825 """
826 m.submodules.add1 = self
827 m.submodules.add1_out_overflow = self.out_of
828
829 m.d.comb += self.in_z.eq(in_z)
830 m.d.comb += self.in_tot.eq(in_tot)
831
832 def elaborate(self, platform):
833 m = Module()
834 #m.submodules.norm1_in_overflow = self.in_of
835 #m.submodules.norm1_out_overflow = self.out_of
836 #m.submodules.norm1_in_z = self.in_z
837 #m.submodules.norm1_out_z = self.out_z
838 m.d.comb += self.out_z.eq(self.in_z)
839 # tot[-1] (MSB) gets set when the sum overflows. shift result down
840 with m.If(self.in_tot[-1]):
841 m.d.comb += [
842 self.out_z.m.eq(self.in_tot[4:]),
843 self.out_of.m0.eq(self.in_tot[4]),
844 self.out_of.guard.eq(self.in_tot[3]),
845 self.out_of.round_bit.eq(self.in_tot[2]),
846 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
847 self.out_z.e.eq(self.in_z.e + 1)
848 ]
849 # tot[-1] (MSB) zero case
850 with m.Else():
851 m.d.comb += [
852 self.out_z.m.eq(self.in_tot[3:]),
853 self.out_of.m0.eq(self.in_tot[3]),
854 self.out_of.guard.eq(self.in_tot[2]),
855 self.out_of.round_bit.eq(self.in_tot[1]),
856 self.out_of.sticky.eq(self.in_tot[0])
857 ]
858 return m
859
860
861 class FPAddStage1(FPState, FPID):
862
863 def __init__(self, width, id_wid):
864 FPState.__init__(self, "add_1")
865 FPID.__init__(self, id_wid)
866 self.mod = FPAddStage1Mod(width)
867 self.out_z = FPNumBase(width, False)
868 self.out_of = Overflow()
869 self.norm_stb = Signal()
870
871 def setup(self, m, in_tot, in_z, in_mid):
872 """ links module to inputs and outputs
873 """
874 self.mod.setup(m, in_tot, in_z)
875
876 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
877
878 if self.in_mid is not None:
879 m.d.comb += self.in_mid.eq(in_mid)
880
881 def action(self, m):
882 self.idsync(m)
883 m.d.sync += self.out_of.eq(self.mod.out_of)
884 m.d.sync += self.out_z.eq(self.mod.out_z)
885 m.d.sync += self.norm_stb.eq(1)
886 m.next = "normalise_1"
887
888
889 class FPNormaliseModSingle:
890
891 def __init__(self, width):
892 self.width = width
893 self.in_z = FPNumBase(width, False)
894 self.out_z = FPNumBase(width, False)
895
896 def setup(self, m, in_z, out_z, modname):
897 """ links module to inputs and outputs
898 """
899 m.submodules.normalise = self
900 m.d.comb += self.in_z.eq(in_z)
901 m.d.comb += out_z.eq(self.out_z)
902
903 def elaborate(self, platform):
904 m = Module()
905
906 mwid = self.out_z.m_width+2
907 pe = PriorityEncoder(mwid)
908 m.submodules.norm_pe = pe
909
910 m.submodules.norm1_out_z = self.out_z
911 m.submodules.norm1_in_z = self.in_z
912
913 in_z = FPNumBase(self.width, False)
914 in_of = Overflow()
915 m.submodules.norm1_insel_z = in_z
916 m.submodules.norm1_insel_overflow = in_of
917
918 espec = (len(in_z.e), True)
919 ediff_n126 = Signal(espec, reset_less=True)
920 msr = MultiShiftRMerge(mwid, espec)
921 m.submodules.multishift_r = msr
922
923 m.d.comb += in_z.eq(self.in_z)
924 m.d.comb += in_of.eq(self.in_of)
925 # initialise out from in (overridden below)
926 m.d.comb += self.out_z.eq(in_z)
927 m.d.comb += self.out_of.eq(in_of)
928 # normalisation increase/decrease conditions
929 decrease = Signal(reset_less=True)
930 m.d.comb += decrease.eq(in_z.m_msbzero)
931 # decrease exponent
932 with m.If(decrease):
933 # *sigh* not entirely obvious: count leading zeros (clz)
934 # with a PriorityEncoder: to find from the MSB
935 # we reverse the order of the bits.
936 temp_m = Signal(mwid, reset_less=True)
937 temp_s = Signal(mwid+1, reset_less=True)
938 clz = Signal((len(in_z.e), True), reset_less=True)
939 m.d.comb += [
940 # cat round and guard bits back into the mantissa
941 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
942 pe.i.eq(temp_m[::-1]), # inverted
943 clz.eq(pe.o), # count zeros from MSB down
944 temp_s.eq(temp_m << clz), # shift mantissa UP
945 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
946 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
947 ]
948
949 return m
950
951
952 class FPNorm1ModSingle:
953
954 def __init__(self, width):
955 self.width = width
956 self.out_norm = Signal(reset_less=True)
957 self.in_z = FPNumBase(width, False)
958 self.in_of = Overflow()
959 self.out_z = FPNumBase(width, False)
960 self.out_of = Overflow()
961
962 def setup(self, m, in_z, in_of, out_z):
963 """ links module to inputs and outputs
964 """
965 m.submodules.normalise_1 = self
966
967 m.d.comb += self.in_z.eq(in_z)
968 m.d.comb += self.in_of.eq(in_of)
969
970 m.d.comb += out_z.eq(self.out_z)
971
972 def elaborate(self, platform):
973 m = Module()
974
975 mwid = self.out_z.m_width+2
976 pe = PriorityEncoder(mwid)
977 m.submodules.norm_pe = pe
978
979 m.submodules.norm1_out_z = self.out_z
980 m.submodules.norm1_out_overflow = self.out_of
981 m.submodules.norm1_in_z = self.in_z
982 m.submodules.norm1_in_overflow = self.in_of
983
984 in_z = FPNumBase(self.width, False)
985 in_of = Overflow()
986 m.submodules.norm1_insel_z = in_z
987 m.submodules.norm1_insel_overflow = in_of
988
989 espec = (len(in_z.e), True)
990 ediff_n126 = Signal(espec, reset_less=True)
991 msr = MultiShiftRMerge(mwid, espec)
992 m.submodules.multishift_r = msr
993
994 m.d.comb += in_z.eq(self.in_z)
995 m.d.comb += in_of.eq(self.in_of)
996 # initialise out from in (overridden below)
997 m.d.comb += self.out_z.eq(in_z)
998 m.d.comb += self.out_of.eq(in_of)
999 # normalisation increase/decrease conditions
1000 decrease = Signal(reset_less=True)
1001 increase = Signal(reset_less=True)
1002 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1003 m.d.comb += increase.eq(in_z.exp_lt_n126)
1004 # decrease exponent
1005 with m.If(decrease):
1006 # *sigh* not entirely obvious: count leading zeros (clz)
1007 # with a PriorityEncoder: to find from the MSB
1008 # we reverse the order of the bits.
1009 temp_m = Signal(mwid, reset_less=True)
1010 temp_s = Signal(mwid+1, reset_less=True)
1011 clz = Signal((len(in_z.e), True), reset_less=True)
1012 # make sure that the amount to decrease by does NOT
1013 # go below the minimum non-INF/NaN exponent
1014 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
1015 in_z.exp_sub_n126)
1016 m.d.comb += [
1017 # cat round and guard bits back into the mantissa
1018 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1019 pe.i.eq(temp_m[::-1]), # inverted
1020 clz.eq(limclz), # count zeros from MSB down
1021 temp_s.eq(temp_m << clz), # shift mantissa UP
1022 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
1023 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
1024 self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
1025 # overflow in bits 0..1: got shifted too (leave sticky)
1026 self.out_of.guard.eq(temp_s[1]), # guard
1027 self.out_of.round_bit.eq(temp_s[0]), # round
1028 ]
1029 # increase exponent
1030 with m.Elif(increase):
1031 temp_m = Signal(mwid+1, reset_less=True)
1032 m.d.comb += [
1033 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
1034 in_z.m)),
1035 ediff_n126.eq(in_z.N126 - in_z.e),
1036 # connect multi-shifter to inp/out mantissa (and ediff)
1037 msr.inp.eq(temp_m),
1038 msr.diff.eq(ediff_n126),
1039 self.out_z.m.eq(msr.m[3:]),
1040 self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
1041 # overflow in bits 0..1: got shifted too (leave sticky)
1042 self.out_of.guard.eq(temp_s[2]), # guard
1043 self.out_of.round_bit.eq(temp_s[1]), # round
1044 self.out_of.sticky.eq(temp_s[0]), # sticky
1045 self.out_z.e.eq(in_z.e + ediff_n126),
1046 ]
1047
1048 return m
1049
1050
1051 class FPNorm1ModMulti:
1052
1053 def __init__(self, width, single_cycle=True):
1054 self.width = width
1055 self.in_select = Signal(reset_less=True)
1056 self.out_norm = Signal(reset_less=True)
1057 self.in_z = FPNumBase(width, False)
1058 self.in_of = Overflow()
1059 self.temp_z = FPNumBase(width, False)
1060 self.temp_of = Overflow()
1061 self.out_z = FPNumBase(width, False)
1062 self.out_of = Overflow()
1063
1064 def elaborate(self, platform):
1065 m = Module()
1066
1067 m.submodules.norm1_out_z = self.out_z
1068 m.submodules.norm1_out_overflow = self.out_of
1069 m.submodules.norm1_temp_z = self.temp_z
1070 m.submodules.norm1_temp_of = self.temp_of
1071 m.submodules.norm1_in_z = self.in_z
1072 m.submodules.norm1_in_overflow = self.in_of
1073
1074 in_z = FPNumBase(self.width, False)
1075 in_of = Overflow()
1076 m.submodules.norm1_insel_z = in_z
1077 m.submodules.norm1_insel_overflow = in_of
1078
1079 # select which of temp or in z/of to use
1080 with m.If(self.in_select):
1081 m.d.comb += in_z.eq(self.in_z)
1082 m.d.comb += in_of.eq(self.in_of)
1083 with m.Else():
1084 m.d.comb += in_z.eq(self.temp_z)
1085 m.d.comb += in_of.eq(self.temp_of)
1086 # initialise out from in (overridden below)
1087 m.d.comb += self.out_z.eq(in_z)
1088 m.d.comb += self.out_of.eq(in_of)
1089 # normalisation increase/decrease conditions
1090 decrease = Signal(reset_less=True)
1091 increase = Signal(reset_less=True)
1092 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1093 m.d.comb += increase.eq(in_z.exp_lt_n126)
1094 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1095 # decrease exponent
1096 with m.If(decrease):
1097 m.d.comb += [
1098 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
1099 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1100 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1101 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1102 self.out_of.round_bit.eq(0), # reset round bit
1103 self.out_of.m0.eq(in_of.guard),
1104 ]
1105 # increase exponent
1106 with m.Elif(increase):
1107 m.d.comb += [
1108 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
1109 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1110 self.out_of.guard.eq(in_z.m[0]),
1111 self.out_of.m0.eq(in_z.m[1]),
1112 self.out_of.round_bit.eq(in_of.guard),
1113 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1114 ]
1115
1116 return m
1117
1118
1119 class FPNorm1Single(FPState, FPID):
1120
1121 def __init__(self, width, id_wid, single_cycle=True):
1122 FPID.__init__(self, id_wid)
1123 FPState.__init__(self, "normalise_1")
1124 self.mod = FPNorm1ModSingle(width)
1125 self.out_norm = Signal(reset_less=True)
1126 self.out_z = FPNumBase(width)
1127 self.out_roundz = Signal(reset_less=True)
1128
1129 def setup(self, m, in_z, in_of, in_mid):
1130 """ links module to inputs and outputs
1131 """
1132 self.mod.setup(m, in_z, in_of, self.out_z)
1133
1134 if self.in_mid is not None:
1135 m.d.comb += self.in_mid.eq(in_mid)
1136
1137 def action(self, m):
1138 self.idsync(m)
1139 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1140 m.next = "round"
1141
1142
1143 class FPNorm1Multi(FPState, FPID):
1144
1145 def __init__(self, width, id_wid):
1146 FPID.__init__(self, id_wid)
1147 FPState.__init__(self, "normalise_1")
1148 self.mod = FPNorm1ModMulti(width)
1149 self.stb = Signal(reset_less=True)
1150 self.ack = Signal(reset=0, reset_less=True)
1151 self.out_norm = Signal(reset_less=True)
1152 self.in_accept = Signal(reset_less=True)
1153 self.temp_z = FPNumBase(width)
1154 self.temp_of = Overflow()
1155 self.out_z = FPNumBase(width)
1156 self.out_roundz = Signal(reset_less=True)
1157
1158 def setup(self, m, in_z, in_of, norm_stb, in_mid):
1159 """ links module to inputs and outputs
1160 """
1161 self.mod.setup(m, in_z, in_of, norm_stb,
1162 self.in_accept, self.temp_z, self.temp_of,
1163 self.out_z, self.out_norm)
1164
1165 m.d.comb += self.stb.eq(norm_stb)
1166 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1167
1168 if self.in_mid is not None:
1169 m.d.comb += self.in_mid.eq(in_mid)
1170
1171 def action(self, m):
1172 self.idsync(m)
1173 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1174 m.d.sync += self.temp_of.eq(self.mod.out_of)
1175 m.d.sync += self.temp_z.eq(self.out_z)
1176 with m.If(self.out_norm):
1177 with m.If(self.in_accept):
1178 m.d.sync += [
1179 self.ack.eq(1),
1180 ]
1181 with m.Else():
1182 m.d.sync += self.ack.eq(0)
1183 with m.Else():
1184 # normalisation not required (or done).
1185 m.next = "round"
1186 m.d.sync += self.ack.eq(1)
1187 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1188
1189
1190 class FPNormToPack(FPState, FPID):
1191
1192 def __init__(self, width, id_wid):
1193 FPID.__init__(self, id_wid)
1194 FPState.__init__(self, "normalise_1")
1195 self.width = width
1196
1197 def setup(self, m, in_z, in_of, in_mid):
1198 """ links module to inputs and outputs
1199 """
1200
1201 # Normalisation (chained to input in_z+in_of)
1202 nmod = FPNorm1ModSingle(self.width)
1203 n_out_z = FPNumBase(self.width)
1204 n_out_roundz = Signal(reset_less=True)
1205 nmod.setup(m, in_z, in_of, n_out_z)
1206
1207 # Rounding (chained to normalisation)
1208 rmod = FPRoundMod(self.width)
1209 r_out_z = FPNumBase(self.width)
1210 rmod.setup(m, n_out_z, n_out_roundz)
1211 m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
1212 m.d.comb += r_out_z.eq(rmod.out_z)
1213
1214 # Corrections (chained to rounding)
1215 cmod = FPCorrectionsMod(self.width)
1216 c_out_z = FPNumBase(self.width)
1217 cmod.setup(m, r_out_z)
1218 m.d.comb += c_out_z.eq(cmod.out_z)
1219
1220 # Pack (chained to corrections)
1221 self.pmod = FPPackMod(self.width)
1222 self.out_z = FPNumBase(self.width)
1223 self.pmod.setup(m, c_out_z)
1224
1225 # Multiplex ID
1226 if self.in_mid is not None:
1227 m.d.comb += self.in_mid.eq(in_mid)
1228
1229 def action(self, m):
1230 self.idsync(m) # copies incoming ID to outgoing
1231 m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
1232 m.next = "pack_put_z"
1233
1234
1235 class FPRoundMod:
1236
1237 def __init__(self, width):
1238 self.in_roundz = Signal(reset_less=True)
1239 self.in_z = FPNumBase(width, False)
1240 self.out_z = FPNumBase(width, False)
1241
1242 def setup(self, m, in_z, roundz):
1243 m.submodules.roundz = self
1244
1245 m.d.comb += self.in_z.eq(in_z)
1246 m.d.comb += self.in_roundz.eq(roundz)
1247
1248 def elaborate(self, platform):
1249 m = Module()
1250 m.d.comb += self.out_z.eq(self.in_z)
1251 with m.If(self.in_roundz):
1252 m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
1253 with m.If(self.in_z.m == self.in_z.m1s): # all 1s
1254 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
1255 return m
1256
1257
1258 class FPRound(FPState, FPID):
1259
1260 def __init__(self, width, id_wid):
1261 FPState.__init__(self, "round")
1262 FPID.__init__(self, id_wid)
1263 self.mod = FPRoundMod(width)
1264 self.out_z = FPNumBase(width)
1265
1266 def setup(self, m, in_z, roundz, in_mid):
1267 """ links module to inputs and outputs
1268 """
1269 self.mod.setup(m, in_z, roundz)
1270
1271 if self.in_mid is not None:
1272 m.d.comb += self.in_mid.eq(in_mid)
1273
1274 def action(self, m):
1275 self.idsync(m)
1276 m.d.sync += self.out_z.eq(self.mod.out_z)
1277 m.next = "corrections"
1278
1279
1280 class FPCorrectionsMod:
1281
1282 def __init__(self, width):
1283 self.in_z = FPNumOut(width, False)
1284 self.out_z = FPNumOut(width, False)
1285
1286 def setup(self, m, in_z):
1287 """ links module to inputs and outputs
1288 """
1289 m.submodules.corrections = self
1290 m.d.comb += self.in_z.eq(in_z)
1291
1292 def elaborate(self, platform):
1293 m = Module()
1294 m.submodules.corr_in_z = self.in_z
1295 m.submodules.corr_out_z = self.out_z
1296 m.d.comb += self.out_z.eq(self.in_z)
1297 with m.If(self.in_z.is_denormalised):
1298 m.d.comb += self.out_z.e.eq(self.in_z.N127)
1299 return m
1300
1301
1302 class FPCorrections(FPState, FPID):
1303
1304 def __init__(self, width, id_wid):
1305 FPState.__init__(self, "corrections")
1306 FPID.__init__(self, id_wid)
1307 self.mod = FPCorrectionsMod(width)
1308 self.out_z = FPNumBase(width)
1309
1310 def setup(self, m, in_z, in_mid):
1311 """ links module to inputs and outputs
1312 """
1313 self.mod.setup(m, in_z)
1314 if self.in_mid is not None:
1315 m.d.comb += self.in_mid.eq(in_mid)
1316
1317 def action(self, m):
1318 self.idsync(m)
1319 m.d.sync += self.out_z.eq(self.mod.out_z)
1320 m.next = "pack"
1321
1322
1323 class FPPackMod:
1324
1325 def __init__(self, width):
1326 self.in_z = FPNumOut(width, False)
1327 self.out_z = FPNumOut(width, False)
1328
1329 def setup(self, m, in_z):
1330 """ links module to inputs and outputs
1331 """
1332 m.submodules.pack = self
1333 m.d.comb += self.in_z.eq(in_z)
1334
1335 def elaborate(self, platform):
1336 m = Module()
1337 m.submodules.pack_in_z = self.in_z
1338 with m.If(self.in_z.is_overflowed):
1339 m.d.comb += self.out_z.inf(self.in_z.s)
1340 with m.Else():
1341 m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
1342 return m
1343
1344
1345 class FPPack(FPState, FPID):
1346
1347 def __init__(self, width, id_wid):
1348 FPState.__init__(self, "pack")
1349 FPID.__init__(self, id_wid)
1350 self.mod = FPPackMod(width)
1351 self.out_z = FPNumOut(width, False)
1352
1353 def setup(self, m, in_z, in_mid):
1354 """ links module to inputs and outputs
1355 """
1356 self.mod.setup(m, in_z)
1357 if self.in_mid is not None:
1358 m.d.comb += self.in_mid.eq(in_mid)
1359
1360 def action(self, m):
1361 self.idsync(m)
1362 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1363 m.next = "pack_put_z"
1364
1365
1366 class FPPutZ(FPState):
1367
1368 def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1369 FPState.__init__(self, state)
1370 if to_state is None:
1371 to_state = "get_ops"
1372 self.to_state = to_state
1373 self.in_z = in_z
1374 self.out_z = out_z
1375 self.in_mid = in_mid
1376 self.out_mid = out_mid
1377
1378 def action(self, m):
1379 if self.in_mid is not None:
1380 m.d.sync += self.out_mid.eq(self.in_mid)
1381 m.d.sync += [
1382 self.out_z.v.eq(self.in_z.v)
1383 ]
1384 with m.If(self.out_z.stb & self.out_z.ack):
1385 m.d.sync += self.out_z.stb.eq(0)
1386 m.next = self.to_state
1387 with m.Else():
1388 m.d.sync += self.out_z.stb.eq(1)
1389
1390
1391 class FPPutZIdx(FPState):
1392
1393 def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1394 FPState.__init__(self, state)
1395 if to_state is None:
1396 to_state = "get_ops"
1397 self.to_state = to_state
1398 self.in_z = in_z
1399 self.out_zs = out_zs
1400 self.in_mid = in_mid
1401
1402 def action(self, m):
1403 outz_stb = Signal(reset_less=True)
1404 outz_ack = Signal(reset_less=True)
1405 m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1406 outz_ack.eq(self.out_zs[self.in_mid].ack),
1407 ]
1408 m.d.sync += [
1409 self.out_zs[self.in_mid].v.eq(self.in_z.v)
1410 ]
1411 with m.If(outz_stb & outz_ack):
1412 m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1413 m.next = self.to_state
1414 with m.Else():
1415 m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1416
1417
1418 class FPADDBaseMod(FPID):
1419
1420 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1421 """ IEEE754 FP Add
1422
1423 * width: bit-width of IEEE754. supported: 16, 32, 64
1424 * id_wid: an identifier that is sync-connected to the input
1425 * single_cycle: True indicates each stage to complete in 1 clock
1426 * compact: True indicates a reduced number of stages
1427 """
1428 FPID.__init__(self, id_wid)
1429 self.width = width
1430 self.single_cycle = single_cycle
1431 self.compact = compact
1432
1433 self.in_t = Trigger()
1434 self.in_a = Signal(width)
1435 self.in_b = Signal(width)
1436 self.out_z = FPOp(width)
1437
1438 self.states = []
1439
1440 def add_state(self, state):
1441 self.states.append(state)
1442 return state
1443
1444 def get_fragment(self, platform=None):
1445 """ creates the HDL code-fragment for FPAdd
1446 """
1447 m = Module()
1448 m.submodules.out_z = self.out_z
1449 m.submodules.in_t = self.in_t
1450 if self.compact:
1451 self.get_compact_fragment(m, platform)
1452 else:
1453 self.get_longer_fragment(m, platform)
1454
1455 with m.FSM() as fsm:
1456
1457 for state in self.states:
1458 with m.State(state.state_from):
1459 state.action(m)
1460
1461 return m
1462
1463 def get_longer_fragment(self, m, platform=None):
1464
1465 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1466 self.in_a, self.in_b, self.width))
1467 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1468 a = get.out_op1
1469 b = get.out_op2
1470
1471 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1472 sc.setup(m, a, b, self.in_mid)
1473
1474 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1475 dn.setup(m, a, b, sc.in_mid)
1476
1477 if self.single_cycle:
1478 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1479 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1480 else:
1481 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1482 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1483
1484 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1485 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1486
1487 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1488 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1489
1490 if self.single_cycle:
1491 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1492 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1493 else:
1494 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1495 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1496
1497 rn = self.add_state(FPRound(self.width, self.id_wid))
1498 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1499
1500 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1501 cor.setup(m, rn.out_z, rn.in_mid)
1502
1503 pa = self.add_state(FPPack(self.width, self.id_wid))
1504 pa.setup(m, cor.out_z, rn.in_mid)
1505
1506 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1507 pa.in_mid, self.out_mid))
1508
1509 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1510 pa.in_mid, self.out_mid))
1511
1512 def get_compact_fragment(self, m, platform=None):
1513
1514 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1515 self.in_a, self.in_b, self.width))
1516 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1517 a = get.out_op1
1518 b = get.out_op2
1519
1520 sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1521 sc.setup(m, a, b, self.in_mid)
1522
1523 alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1524 alm.setup(m, sc.out_a, sc.out_b, sc.in_mid)
1525
1526 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1527 n1.setup(m, alm.out_z, alm.out_of, alm.in_mid)
1528
1529 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
1530 n1.in_mid, self.out_mid))
1531
1532 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1533 sc.in_mid, self.out_mid))
1534
1535
1536 class FPADDBase(FPState, FPID):
1537
1538 def __init__(self, width, id_wid=None, single_cycle=False):
1539 """ IEEE754 FP Add
1540
1541 * width: bit-width of IEEE754. supported: 16, 32, 64
1542 * id_wid: an identifier that is sync-connected to the input
1543 * single_cycle: True indicates each stage to complete in 1 clock
1544 """
1545 FPID.__init__(self, id_wid)
1546 FPState.__init__(self, "fpadd")
1547 self.width = width
1548 self.single_cycle = single_cycle
1549 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1550
1551 self.in_t = Trigger()
1552 self.in_a = Signal(width)
1553 self.in_b = Signal(width)
1554 #self.out_z = FPOp(width)
1555
1556 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1557 self.in_accept = Signal(reset_less=True)
1558 self.add_stb = Signal(reset_less=True)
1559 self.add_ack = Signal(reset=0, reset_less=True)
1560
1561 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1562 self.out_z = out_z
1563 self.out_mid = out_mid
1564 m.d.comb += [self.in_a.eq(a),
1565 self.in_b.eq(b),
1566 self.mod.in_a.eq(self.in_a),
1567 self.mod.in_b.eq(self.in_b),
1568 self.in_mid.eq(in_mid),
1569 self.mod.in_mid.eq(self.in_mid),
1570 self.z_done.eq(self.mod.out_z.trigger),
1571 #self.add_stb.eq(add_stb),
1572 self.mod.in_t.stb.eq(self.in_t.stb),
1573 self.in_t.ack.eq(self.mod.in_t.ack),
1574 self.out_mid.eq(self.mod.out_mid),
1575 self.out_z.v.eq(self.mod.out_z.v),
1576 self.out_z.stb.eq(self.mod.out_z.stb),
1577 self.mod.out_z.ack.eq(self.out_z.ack),
1578 ]
1579
1580 m.d.sync += self.add_stb.eq(add_stb)
1581 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1582 m.d.sync += self.out_z.ack.eq(0) # likewise
1583 #m.d.sync += self.in_t.stb.eq(0)
1584
1585 m.submodules.fpadd = self.mod
1586
1587 def action(self, m):
1588
1589 # in_accept is set on incoming strobe HIGH and ack LOW.
1590 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1591
1592 #with m.If(self.in_t.ack):
1593 # m.d.sync += self.in_t.stb.eq(0)
1594 with m.If(~self.z_done):
1595 # not done: test for accepting an incoming operand pair
1596 with m.If(self.in_accept):
1597 m.d.sync += [
1598 self.add_ack.eq(1), # acknowledge receipt...
1599 self.in_t.stb.eq(1), # initiate add
1600 ]
1601 with m.Else():
1602 m.d.sync += [self.add_ack.eq(0),
1603 self.in_t.stb.eq(0),
1604 self.out_z.ack.eq(1),
1605 ]
1606 with m.Else():
1607 # done: acknowledge, and write out id and value
1608 m.d.sync += [self.add_ack.eq(1),
1609 self.in_t.stb.eq(0)
1610 ]
1611 m.next = "put_z"
1612
1613 return
1614
1615 if self.in_mid is not None:
1616 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1617
1618 m.d.sync += [
1619 self.out_z.v.eq(self.mod.out_z.v)
1620 ]
1621 # move to output state on detecting z ack
1622 with m.If(self.out_z.trigger):
1623 m.d.sync += self.out_z.stb.eq(0)
1624 m.next = "put_z"
1625 with m.Else():
1626 m.d.sync += self.out_z.stb.eq(1)
1627
1628 class ResArray:
1629 def __init__(self, width, id_wid):
1630 self.width = width
1631 self.id_wid = id_wid
1632 res = []
1633 for i in range(rs_sz):
1634 out_z = FPOp(width)
1635 out_z.name = "out_z_%d" % i
1636 res.append(out_z)
1637 self.res = Array(res)
1638 self.in_z = FPOp(width)
1639 self.in_mid = Signal(self.id_wid, reset_less=True)
1640
1641 def setup(self, m, in_z, in_mid):
1642 m.d.comb += [self.in_z.eq(in_z),
1643 self.in_mid.eq(in_mid)]
1644
1645 def get_fragment(self, platform=None):
1646 """ creates the HDL code-fragment for FPAdd
1647 """
1648 m = Module()
1649 m.submodules.res_in_z = self.in_z
1650 m.submodules += self.res
1651
1652 return m
1653
1654 def ports(self):
1655 res = []
1656 for z in self.res:
1657 res += z.ports()
1658 return res
1659
1660
1661 class FPADD(FPID):
1662 """ FPADD: stages as follows:
1663
1664 FPGetOp (a)
1665 |
1666 FPGetOp (b)
1667 |
1668 FPAddBase---> FPAddBaseMod
1669 | |
1670 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1671
1672 FPAddBase is tricky: it is both a stage and *has* stages.
1673 Connection to FPAddBaseMod therefore requires an in stb/ack
1674 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1675 needs to be the thing that raises the incoming stb.
1676 """
1677
1678 def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1679 """ IEEE754 FP Add
1680
1681 * width: bit-width of IEEE754. supported: 16, 32, 64
1682 * id_wid: an identifier that is sync-connected to the input
1683 * single_cycle: True indicates each stage to complete in 1 clock
1684 """
1685 self.width = width
1686 self.id_wid = id_wid
1687 self.single_cycle = single_cycle
1688
1689 #self.out_z = FPOp(width)
1690 self.ids = FPID(id_wid)
1691
1692 rs = []
1693 for i in range(rs_sz):
1694 in_a = FPOp(width)
1695 in_b = FPOp(width)
1696 in_a.name = "in_a_%d" % i
1697 in_b.name = "in_b_%d" % i
1698 rs.append((in_a, in_b))
1699 self.rs = Array(rs)
1700
1701 res = []
1702 for i in range(rs_sz):
1703 out_z = FPOp(width)
1704 out_z.name = "out_z_%d" % i
1705 res.append(out_z)
1706 self.res = Array(res)
1707
1708 self.states = []
1709
1710 def add_state(self, state):
1711 self.states.append(state)
1712 return state
1713
1714 def get_fragment(self, platform=None):
1715 """ creates the HDL code-fragment for FPAdd
1716 """
1717 m = Module()
1718 m.submodules += self.rs
1719
1720 in_a = self.rs[0][0]
1721 in_b = self.rs[0][1]
1722
1723 out_z = FPOp(self.width)
1724 out_mid = Signal(self.id_wid, reset_less=True)
1725 m.submodules.out_z = out_z
1726
1727 geta = self.add_state(FPGetOp("get_a", "get_b",
1728 in_a, self.width))
1729 geta.setup(m, in_a)
1730 a = geta.out_op
1731
1732 getb = self.add_state(FPGetOp("get_b", "fpadd",
1733 in_b, self.width))
1734 getb.setup(m, in_b)
1735 b = getb.out_op
1736
1737 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1738 ab = self.add_state(ab)
1739 ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1740 out_z, out_mid)
1741
1742 pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1743 out_mid, "get_a"))
1744
1745 with m.FSM() as fsm:
1746
1747 for state in self.states:
1748 with m.State(state.state_from):
1749 state.action(m)
1750
1751 return m
1752
1753
1754 if __name__ == "__main__":
1755 if True:
1756 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1757 main(alu, ports=alu.rs[0][0].ports() + \
1758 alu.rs[0][1].ports() + \
1759 alu.res[0].ports() + \
1760 [alu.ids.in_mid, alu.ids.out_mid])
1761 else:
1762 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1763 main(alu, ports=[alu.in_a, alu.in_b] + \
1764 alu.in_t.ports() + \
1765 alu.out_z.ports() + \
1766 [alu.in_mid, alu.out_mid])
1767
1768
1769 # works... but don't use, just do "python fname.py convert -t v"
1770 #print (verilog.convert(alu, ports=[
1771 # ports=alu.in_a.ports() + \
1772 # alu.in_b.ports() + \
1773 # alu.out_z.ports())