src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux, Array, Const
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8 from math import log
   9
  10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  11 from fpbase import MultiShiftRMerge, Trigger
  12 from example_buf_pipe import StageChain
  13 #from fpbase import FPNumShiftMultiRight
  14
  15
  16 class FPState(FPBase):
  17     def __init__(self, state_from):
  18         self.state_from = state_from
  19
  20     def set_inputs(self, inputs):
  21         self.inputs = inputs
  22         for k,v in inputs.items():
  23             setattr(self, k, v)
  24
  25     def set_outputs(self, outputs):
  26         self.outputs = outputs
  27         for k,v in outputs.items():
  28             setattr(self, k, v)
  29
  30
  31 class FPGetSyncOpsMod:
  32     def __init__(self, width, num_ops=2):
  33         self.width = width
  34         self.num_ops = num_ops
  35         inops = []
  36         outops = []
  37         for i in range(num_ops):
  38             inops.append(Signal(width, reset_less=True))
  39             outops.append(Signal(width, reset_less=True))
  40         self.in_op = inops
  41         self.out_op = outops
  42         self.stb = Signal(num_ops)
  43         self.ack = Signal()
  44         self.ready = Signal(reset_less=True)
  45         self.out_decode = Signal(reset_less=True)
  46
  47     def elaborate(self, platform):
  48         m = Module()
  49         m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
  50         m.d.comb += self.out_decode.eq(self.ack & self.ready)
  51         with m.If(self.out_decode):
  52             for i in range(self.num_ops):
  53                 m.d.comb += [
  54                         self.out_op[i].eq(self.in_op[i]),
  55                 ]
  56         return m
  57
  58     def ports(self):
  59         return self.in_op + self.out_op + [self.stb, self.ack]
  60
  61
  62 class FPOps(Trigger):
  63     def __init__(self, width, num_ops):
  64         Trigger.__init__(self)
  65         self.width = width
  66         self.num_ops = num_ops
  67
  68         res = []
  69         for i in range(num_ops):
  70             res.append(Signal(width))
  71         self.v  = Array(res)
  72
  73     def ports(self):
  74         res = []
  75         for i in range(self.num_ops):
  76             res.append(self.v[i])
  77         res.append(self.ack)
  78         res.append(self.stb)
  79         return res
  80
  81
  82 class InputGroup:
  83     def __init__(self, width, num_ops=2, num_rows=4):
  84         self.width = width
  85         self.num_ops = num_ops
  86         self.num_rows = num_rows
  87         self.mmax = int(log(self.num_rows) / log(2))
  88         self.rs = []
  89         self.mid = Signal(self.mmax, reset_less=True) # multiplex id
  90         for i in range(num_rows):
  91             self.rs.append(FPGetSyncOpsMod(width, num_ops))
  92         self.rs = Array(self.rs)
  93
  94         self.out_op = FPOps(width, num_ops)
  95
  96     def elaborate(self, platform):
  97         m = Module()
  98
  99         pe = PriorityEncoder(self.num_rows)
 100         m.submodules.selector = pe
 101         m.submodules.out_op = self.out_op
 102         m.submodules += self.rs
 103
 104         # connect priority encoder
 105         in_ready = []
 106         for i in range(self.num_rows):
 107             in_ready.append(self.rs[i].ready)
 108         m.d.comb += pe.i.eq(Cat(*in_ready))
 109
 110         active = Signal(reset_less=True)
 111         out_en = Signal(reset_less=True)
 112         m.d.comb += active.eq(~pe.n) # encoder active
 113         m.d.comb += out_en.eq(active & self.out_op.trigger)
 114
 115         # encoder active: ack relevant input, record MID, pass output
 116         with m.If(out_en):
 117             rs = self.rs[pe.o]
 118             m.d.sync += self.mid.eq(pe.o)
 119             m.d.sync += rs.ack.eq(0)
 120             m.d.sync += self.out_op.stb.eq(0)
 121             for j in range(self.num_ops):
 122                 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
 123         with m.Else():
 124             m.d.sync += self.out_op.stb.eq(1)
 125             # acks all default to zero
 126             for i in range(self.num_rows):
 127                 m.d.sync += self.rs[i].ack.eq(1)
 128
 129         return m
 130
 131     def ports(self):
 132         res = []
 133         for i in range(self.num_rows):
 134             inop = self.rs[i]
 135             res += inop.in_op + [inop.stb]
 136         return self.out_op.ports() + res + [self.mid]
 137
 138
 139 class FPGetOpMod:
 140     def __init__(self, width):
 141         self.in_op = FPOp(width)
 142         self.out_op = Signal(width)
 143         self.out_decode = Signal(reset_less=True)
 144
 145     def elaborate(self, platform):
 146         m = Module()
 147         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
 148         m.submodules.get_op_in = self.in_op
 149         #m.submodules.get_op_out = self.out_op
 150         with m.If(self.out_decode):
 151             m.d.comb += [
 152                 self.out_op.eq(self.in_op.v),
 153             ]
 154         return m
 155
 156
 157 class FPGetOp(FPState):
 158     """ gets operand
 159     """
 160
 161     def __init__(self, in_state, out_state, in_op, width):
 162         FPState.__init__(self, in_state)
 163         self.out_state = out_state
 164         self.mod = FPGetOpMod(width)
 165         self.in_op = in_op
 166         self.out_op = Signal(width)
 167         self.out_decode = Signal(reset_less=True)
 168
 169     def setup(self, m, in_op):
 170         """ links module to inputs and outputs
 171         """
 172         setattr(m.submodules, self.state_from, self.mod)
 173         m.d.comb += self.mod.in_op.eq(in_op)
 174         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 175
 176     def action(self, m):
 177         with m.If(self.out_decode):
 178             m.next = self.out_state
 179             m.d.sync += [
 180                 self.in_op.ack.eq(0),
 181                 self.out_op.eq(self.mod.out_op)
 182             ]
 183         with m.Else():
 184             m.d.sync += self.in_op.ack.eq(1)
 185
 186
 187 class FPGet2OpMod(Trigger):
 188     def __init__(self, width, id_wid):
 189         Trigger.__init__(self)
 190         self.width = width
 191         self.id_wid = id_wid
 192         self.i = self.ispec()
 193         self.o = self.ospec()
 194
 195     def ispec(self):
 196         return FPADDBaseData(self.width, self.id_wid)
 197
 198     def ospec(self):
 199         return FPNumBase2Ops(self.width, self.id_wid)
 200
 201     def elaborate(self, platform):
 202         m = Trigger.elaborate(self, platform)
 203         m.submodules.get_op1_out = self.o.a
 204         m.submodules.get_op2_out = self.o.b
 205         out_op1 = FPNumIn(None, self.width)
 206         out_op2 = FPNumIn(None, self.width)
 207         with m.If(self.trigger):
 208             m.d.comb += [
 209                 out_op1.decode(self.i.a),
 210                 out_op2.decode(self.i.b),
 211                 self.o.a.eq(out_op1),
 212                 self.o.b.eq(out_op2),
 213                 self.o.mid.eq(self.i.mid)
 214             ]
 215         return m
 216
 217
 218 class FPGet2Op(FPState):
 219     """ gets operands
 220     """
 221
 222     def __init__(self, in_state, out_state, width, id_wid):
 223         FPState.__init__(self, in_state)
 224         self.out_state = out_state
 225         self.mod = FPGet2OpMod(width, id_wid)
 226         self.o = self.mod.ospec()
 227         self.in_stb = Signal(reset_less=True)
 228         self.out_ack = Signal(reset_less=True)
 229         self.out_decode = Signal(reset_less=True)
 230
 231     def setup(self, m, i, in_stb, in_ack):
 232         """ links module to inputs and outputs
 233         """
 234         m.submodules.get_ops = self.mod
 235         m.d.comb += self.mod.i.eq(i)
 236         m.d.comb += self.mod.stb.eq(in_stb)
 237         m.d.comb += self.out_ack.eq(self.mod.ack)
 238         m.d.comb += self.out_decode.eq(self.mod.trigger)
 239         m.d.comb += in_ack.eq(self.mod.ack)
 240
 241     def action(self, m):
 242         with m.If(self.out_decode):
 243             m.next = self.out_state
 244             m.d.sync += [
 245                 self.mod.ack.eq(0),
 246                 self.o.eq(self.mod.o),
 247             ]
 248         with m.Else():
 249             m.d.sync += self.mod.ack.eq(1)
 250
 251
 252 class FPNumBase2Ops:
 253
 254     def __init__(self, width, id_wid, m_extra=True):
 255         self.a = FPNumBase(width, m_extra)
 256         self.b = FPNumBase(width, m_extra)
 257         self.mid = Signal(id_wid, reset_less=True)
 258
 259     def eq(self, i):
 260         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 261
 262
 263 class FPAddSpecialCasesMod:
 264     """ special cases: NaNs, infs, zeros, denormalised
 265         NOTE: some of these are unique to add.  see "Special Operations"
 266         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 267     """
 268
 269     def __init__(self, width, id_wid):
 270         self.width = width
 271         self.id_wid = id_wid
 272         self.i = self.ispec()
 273         self.o = self.ospec()
 274         self.out_do_z = Signal(reset_less=True)
 275
 276     def ispec(self):
 277         return FPNumBase2Ops(self.width, self.id_wid)
 278
 279     def ospec(self):
 280         return FPPackData(self.width, self.id_wid)
 281
 282     def setup(self, m, i, out_do_z):
 283         """ links module to inputs and outputs
 284         """
 285         m.submodules.specialcases = self
 286         m.d.comb += self.i.eq(i)
 287         m.d.comb += out_do_z.eq(self.out_do_z)
 288
 289     def elaborate(self, platform):
 290         m = Module()
 291
 292         m.submodules.sc_in_a = self.i.a
 293         m.submodules.sc_in_b = self.i.b
 294         m.submodules.sc_out_z = self.o.z
 295
 296         s_nomatch = Signal()
 297         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
 298
 299         m_match = Signal()
 300         m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
 301
 302         # if a is NaN or b is NaN return NaN
 303         with m.If(self.i.a.is_nan | self.i.b.is_nan):
 304             m.d.comb += self.out_do_z.eq(1)
 305             m.d.comb += self.o.z.nan(0)
 306
 307         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 308         # under review
 309
 310         ## if a is zero and b is NaN return -b
 311         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 312         #    m.d.comb += self.out_do_z.eq(1)
 313         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 314
 315         ## if b is zero and a is NaN return -a
 316         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 317         #    m.d.comb += self.out_do_z.eq(1)
 318         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 319
 320         ## if a is -zero and b is NaN return -b
 321         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 322         #    m.d.comb += self.out_do_z.eq(1)
 323         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 324
 325         ## if b is -zero and a is NaN return -a
 326         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 327         #    m.d.comb += self.out_do_z.eq(1)
 328         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 329
 330         # if a is inf return inf (or NaN)
 331         with m.Elif(self.i.a.is_inf):
 332             m.d.comb += self.out_do_z.eq(1)
 333             m.d.comb += self.o.z.inf(self.i.a.s)
 334             # if a is inf and signs don't match return NaN
 335             with m.If(self.i.b.exp_128 & s_nomatch):
 336                 m.d.comb += self.o.z.nan(0)
 337
 338         # if b is inf return inf
 339         with m.Elif(self.i.b.is_inf):
 340             m.d.comb += self.out_do_z.eq(1)
 341             m.d.comb += self.o.z.inf(self.i.b.s)
 342
 343         # if a is zero and b zero return signed-a/b
 344         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
 345             m.d.comb += self.out_do_z.eq(1)
 346             m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
 347                                           self.i.b.e,
 348                                           self.i.b.m[3:-1])
 349
 350         # if a is zero return b
 351         with m.Elif(self.i.a.is_zero):
 352             m.d.comb += self.out_do_z.eq(1)
 353             m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
 354                                       self.i.b.m[3:-1])
 355
 356         # if b is zero return a
 357         with m.Elif(self.i.b.is_zero):
 358             m.d.comb += self.out_do_z.eq(1)
 359             m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
 360                                       self.i.a.m[3:-1])
 361
 362         # if a equal to -b return zero (+ve zero)
 363         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
 364             m.d.comb += self.out_do_z.eq(1)
 365             m.d.comb += self.o.z.zero(0)
 366
 367         # Denormalised Number checks
 368         with m.Else():
 369             m.d.comb += self.out_do_z.eq(0)
 370
 371         m.d.comb += self.o.mid.eq(self.i.mid)
 372
 373         return m
 374
 375
 376 class FPID:
 377     def __init__(self, id_wid):
 378         self.id_wid = id_wid
 379         if self.id_wid:
 380             self.in_mid = Signal(id_wid, reset_less=True)
 381             self.out_mid = Signal(id_wid, reset_less=True)
 382         else:
 383             self.in_mid = None
 384             self.out_mid = None
 385
 386     def idsync(self, m):
 387         if self.id_wid is not None:
 388             m.d.sync += self.out_mid.eq(self.in_mid)
 389
 390
 391 class FPAddSpecialCases(FPState):
 392     """ special cases: NaNs, infs, zeros, denormalised
 393         NOTE: some of these are unique to add.  see "Special Operations"
 394         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 395     """
 396
 397     def __init__(self, width, id_wid):
 398         FPState.__init__(self, "special_cases")
 399         self.mod = FPAddSpecialCasesMod(width)
 400         self.out_z = self.mod.ospec()
 401         self.out_do_z = Signal(reset_less=True)
 402
 403     def setup(self, m, i):
 404         """ links module to inputs and outputs
 405         """
 406         self.mod.setup(m, i, self.out_do_z)
 407         m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 408         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)  # (and mid)
 409
 410     def action(self, m):
 411         self.idsync(m)
 412         with m.If(self.out_do_z):
 413             m.next = "put_z"
 414         with m.Else():
 415             m.next = "denormalise"
 416
 417
 418 class FPAddSpecialCasesDeNorm(FPState):
 419     """ special cases: NaNs, infs, zeros, denormalised
 420         NOTE: some of these are unique to add.  see "Special Operations"
 421         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 422     """
 423
 424     def __init__(self, width, id_wid):
 425         FPState.__init__(self, "special_cases")
 426         self.smod = FPAddSpecialCasesMod(width, id_wid)
 427         self.out_z = self.smod.ospec()
 428         self.out_do_z = Signal(reset_less=True)
 429
 430         self.dmod = FPAddDeNormMod(width, id_wid)
 431         self.o = self.dmod.ospec()
 432
 433     def setup(self, m, i):
 434         """ links module to inputs and outputs
 435         """
 436         self.smod.setup(m, i, self.out_do_z)
 437         self.dmod.setup(m, i)
 438
 439         # out_do_z=True
 440         m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
 441         m.d.sync += self.out_z.mid.eq(self.smod.o.mid)  # (and mid)
 442         # out_do_z=False
 443         m.d.sync += self.o.eq(self.dmod.o)
 444
 445     def action(self, m):
 446         with m.If(self.out_do_z):
 447             m.next = "put_z"
 448         with m.Else():
 449             m.next = "align"
 450
 451
 452 class FPAddDeNormMod(FPState):
 453
 454     def __init__(self, width, id_wid):
 455         self.width = width
 456         self.id_wid = id_wid
 457         self.i = self.ispec()
 458         self.o = self.ospec()
 459
 460     def ispec(self):
 461         return FPNumBase2Ops(self.width, self.id_wid)
 462
 463     def ospec(self):
 464         return FPNumBase2Ops(self.width, self.id_wid)
 465
 466     def setup(self, m, i):
 467         """ links module to inputs and outputs
 468         """
 469         m.submodules.denormalise = self
 470         m.d.comb += self.i.eq(i)
 471
 472     def elaborate(self, platform):
 473         m = Module()
 474         m.submodules.denorm_in_a = self.i.a
 475         m.submodules.denorm_in_b = self.i.b
 476         m.submodules.denorm_out_a = self.o.a
 477         m.submodules.denorm_out_b = self.o.b
 478         # hmmm, don't like repeating identical code
 479         m.d.comb += self.o.a.eq(self.i.a)
 480         with m.If(self.i.a.exp_n127):
 481             m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
 482         with m.Else():
 483             m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 484
 485         m.d.comb += self.o.b.eq(self.i.b)
 486         with m.If(self.i.b.exp_n127):
 487             m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
 488         with m.Else():
 489             m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 490
 491         m.d.comb += self.o.mid.eq(self.i.mid)
 492
 493         return m
 494
 495
 496 class FPAddDeNorm(FPState):
 497
 498     def __init__(self, width, id_wid):
 499         FPState.__init__(self, "denormalise")
 500         self.mod = FPAddDeNormMod(width)
 501         self.out_a = FPNumBase(width)
 502         self.out_b = FPNumBase(width)
 503
 504     def setup(self, m, i):
 505         """ links module to inputs and outputs
 506         """
 507         self.mod.setup(m, i)
 508
 509         m.d.sync += self.out_a.eq(self.mod.out_a)
 510         m.d.sync += self.out_b.eq(self.mod.out_b)
 511
 512     def action(self, m):
 513         # Denormalised Number checks
 514         m.next = "align"
 515
 516
 517 class FPAddAlignMultiMod(FPState):
 518
 519     def __init__(self, width):
 520         self.in_a = FPNumBase(width)
 521         self.in_b = FPNumBase(width)
 522         self.out_a = FPNumIn(None, width)
 523         self.out_b = FPNumIn(None, width)
 524         self.exp_eq = Signal(reset_less=True)
 525
 526     def elaborate(self, platform):
 527         # This one however (single-cycle) will do the shift
 528         # in one go.
 529
 530         m = Module()
 531
 532         m.submodules.align_in_a = self.in_a
 533         m.submodules.align_in_b = self.in_b
 534         m.submodules.align_out_a = self.out_a
 535         m.submodules.align_out_b = self.out_b
 536
 537         # NOTE: this does *not* do single-cycle multi-shifting,
 538         #       it *STAYS* in the align state until exponents match
 539
 540         # exponent of a greater than b: shift b down
 541         m.d.comb += self.exp_eq.eq(0)
 542         m.d.comb += self.out_a.eq(self.in_a)
 543         m.d.comb += self.out_b.eq(self.in_b)
 544         agtb = Signal(reset_less=True)
 545         altb = Signal(reset_less=True)
 546         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 547         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 548         with m.If(agtb):
 549             m.d.comb += self.out_b.shift_down(self.in_b)
 550         # exponent of b greater than a: shift a down
 551         with m.Elif(altb):
 552             m.d.comb += self.out_a.shift_down(self.in_a)
 553         # exponents equal: move to next stage.
 554         with m.Else():
 555             m.d.comb += self.exp_eq.eq(1)
 556         return m
 557
 558
 559 class FPAddAlignMulti(FPState):
 560
 561     def __init__(self, width, id_wid):
 562         FPState.__init__(self, "align")
 563         self.mod = FPAddAlignMultiMod(width)
 564         self.out_a = FPNumIn(None, width)
 565         self.out_b = FPNumIn(None, width)
 566         self.exp_eq = Signal(reset_less=True)
 567
 568     def setup(self, m, in_a, in_b):
 569         """ links module to inputs and outputs
 570         """
 571         m.submodules.align = self.mod
 572         m.d.comb += self.mod.in_a.eq(in_a)
 573         m.d.comb += self.mod.in_b.eq(in_b)
 574         #m.d.comb += self.out_a.eq(self.mod.out_a)
 575         #m.d.comb += self.out_b.eq(self.mod.out_b)
 576         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 577         m.d.sync += self.out_a.eq(self.mod.out_a)
 578         m.d.sync += self.out_b.eq(self.mod.out_b)
 579
 580     def action(self, m):
 581         with m.If(self.exp_eq):
 582             m.next = "add_0"
 583
 584
 585 class FPNumIn2Ops:
 586
 587     def __init__(self, width, id_wid):
 588         self.a = FPNumIn(None, width)
 589         self.b = FPNumIn(None, width)
 590         self.mid = Signal(id_wid, reset_less=True)
 591
 592     def eq(self, i):
 593         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 594
 595
 596 class FPAddAlignSingleMod:
 597
 598     def __init__(self, width, id_wid):
 599         self.width = width
 600         self.id_wid = id_wid
 601         self.i = self.ispec()
 602         self.o = self.ospec()
 603
 604     def ispec(self):
 605         return FPNumBase2Ops(self.width, self.id_wid)
 606
 607     def ospec(self):
 608         return FPNumIn2Ops(self.width, self.id_wid)
 609
 610     def setup(self, m, i):
 611         """ links module to inputs and outputs
 612         """
 613         m.submodules.align = self
 614         m.d.comb += self.i.eq(i)
 615
 616     def elaborate(self, platform):
 617         """ Aligns A against B or B against A, depending on which has the
 618             greater exponent.  This is done in a *single* cycle using
 619             variable-width bit-shift
 620
 621             the shifter used here is quite expensive in terms of gates.
 622             Mux A or B in (and out) into temporaries, as only one of them
 623             needs to be aligned against the other
 624         """
 625         m = Module()
 626
 627         m.submodules.align_in_a = self.i.a
 628         m.submodules.align_in_b = self.i.b
 629         m.submodules.align_out_a = self.o.a
 630         m.submodules.align_out_b = self.o.b
 631
 632         # temporary (muxed) input and output to be shifted
 633         t_inp = FPNumBase(self.width)
 634         t_out = FPNumIn(None, self.width)
 635         espec = (len(self.i.a.e), True)
 636         msr = MultiShiftRMerge(self.i.a.m_width, espec)
 637         m.submodules.align_t_in = t_inp
 638         m.submodules.align_t_out = t_out
 639         m.submodules.multishift_r = msr
 640
 641         ediff = Signal(espec, reset_less=True)
 642         ediffr = Signal(espec, reset_less=True)
 643         tdiff = Signal(espec, reset_less=True)
 644         elz = Signal(reset_less=True)
 645         egz = Signal(reset_less=True)
 646
 647         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 648         m.d.comb += msr.inp.eq(t_inp.m)
 649         m.d.comb += msr.diff.eq(tdiff)
 650         m.d.comb += t_out.m.eq(msr.m)
 651         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 652         m.d.comb += t_out.s.eq(t_inp.s)
 653
 654         m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
 655         m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
 656         m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
 657         m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
 658
 659         # default: A-exp == B-exp, A and B untouched (fall through)
 660         m.d.comb += self.o.a.eq(self.i.a)
 661         m.d.comb += self.o.b.eq(self.i.b)
 662         # only one shifter (muxed)
 663         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 664         # exponent of a greater than b: shift b down
 665         with m.If(egz):
 666             m.d.comb += [t_inp.eq(self.i.b),
 667                          tdiff.eq(ediff),
 668                          self.o.b.eq(t_out),
 669                          self.o.b.s.eq(self.i.b.s), # whoops forgot sign
 670                         ]
 671         # exponent of b greater than a: shift a down
 672         with m.Elif(elz):
 673             m.d.comb += [t_inp.eq(self.i.a),
 674                          tdiff.eq(ediffr),
 675                          self.o.a.eq(t_out),
 676                          self.o.a.s.eq(self.i.a.s), # whoops forgot sign
 677                         ]
 678
 679         m.d.comb += self.o.mid.eq(self.i.mid)
 680
 681         return m
 682
 683
 684 class FPAddAlignSingle(FPState):
 685
 686     def __init__(self, width, id_wid):
 687         FPState.__init__(self, "align")
 688         self.mod = FPAddAlignSingleMod(width, id_wid)
 689         self.out_a = FPNumIn(None, width)
 690         self.out_b = FPNumIn(None, width)
 691
 692     def setup(self, m, i):
 693         """ links module to inputs and outputs
 694         """
 695         self.mod.setup(m, i)
 696
 697         # NOTE: could be done as comb
 698         m.d.sync += self.out_a.eq(self.mod.out_a)
 699         m.d.sync += self.out_b.eq(self.mod.out_b)
 700
 701     def action(self, m):
 702         m.next = "add_0"
 703
 704
 705 class FPAddAlignSingleAdd(FPState):
 706
 707     def __init__(self, width, id_wid):
 708         FPState.__init__(self, "align")
 709         self.width = width
 710         self.id_wid = id_wid
 711         self.a1o = self.ospec()
 712
 713     def ispec(self):
 714         return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
 715
 716     def ospec(self):
 717         return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
 718
 719     def setup(self, m, i):
 720         """ links module to inputs and outputs
 721         """
 722         mod = FPAddAlignSingleMod(self.width, self.id_wid)
 723         mod.setup(m, i)
 724         o = mod.ospec()
 725         m.d.comb += o.eq(mod.o)
 726
 727         a0mod = FPAddStage0Mod(self.width, self.id_wid)
 728         a0mod.setup(m, o)
 729         a0o = a0mod.ospec()
 730         m.d.comb += a0o.eq(a0mod.o)
 731
 732         a1mod = FPAddStage1Mod(self.width, self.id_wid)
 733         a1mod.setup(m, a0o)
 734         self.a1modo = a1mod.o
 735
 736         m.d.sync += self.a1o.eq(self.a1modo)
 737
 738     def action(self, m):
 739         m.next = "normalise_1"
 740
 741
 742 class FPAddStage0Data:
 743
 744     def __init__(self, width, id_wid):
 745         self.z = FPNumBase(width, False)
 746         self.tot = Signal(self.z.m_width + 4, reset_less=True)
 747         self.mid = Signal(id_wid, reset_less=True)
 748
 749     def eq(self, i):
 750         return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
 751
 752
 753 class FPAddStage0Mod:
 754
 755     def __init__(self, width, id_wid):
 756         self.width = width
 757         self.id_wid = id_wid
 758         self.i = self.ispec()
 759         self.o = self.ospec()
 760
 761     def ispec(self):
 762         return FPNumBase2Ops(self.width, self.id_wid)
 763
 764     def ospec(self):
 765         return FPAddStage0Data(self.width, self.id_wid)
 766
 767     def setup(self, m, i):
 768         """ links module to inputs and outputs
 769         """
 770         m.submodules.add0 = self
 771         m.d.comb += self.i.eq(i)
 772
 773     def elaborate(self, platform):
 774         m = Module()
 775         m.submodules.add0_in_a = self.i.a
 776         m.submodules.add0_in_b = self.i.b
 777         m.submodules.add0_out_z = self.o.z
 778
 779         m.d.comb += self.o.mid.eq(self.i.mid)
 780         m.d.comb += self.o.z.e.eq(self.i.a.e)
 781
 782         # store intermediate tests (and zero-extended mantissas)
 783         seq = Signal(reset_less=True)
 784         mge = Signal(reset_less=True)
 785         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
 786         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
 787         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
 788                      mge.eq(self.i.a.m >= self.i.b.m),
 789                      am0.eq(Cat(self.i.a.m, 0)),
 790                      bm0.eq(Cat(self.i.b.m, 0))
 791                     ]
 792         # same-sign (both negative or both positive) add mantissas
 793         with m.If(seq):
 794             m.d.comb += [
 795                 self.o.tot.eq(am0 + bm0),
 796                 self.o.z.s.eq(self.i.a.s)
 797             ]
 798         # a mantissa greater than b, use a
 799         with m.Elif(mge):
 800             m.d.comb += [
 801                 self.o.tot.eq(am0 - bm0),
 802                 self.o.z.s.eq(self.i.a.s)
 803             ]
 804         # b mantissa greater than a, use b
 805         with m.Else():
 806             m.d.comb += [
 807                 self.o.tot.eq(bm0 - am0),
 808                 self.o.z.s.eq(self.i.b.s)
 809         ]
 810         return m
 811
 812
 813 class FPAddStage0(FPState):
 814     """ First stage of add.  covers same-sign (add) and subtract
 815         special-casing when mantissas are greater or equal, to
 816         give greatest accuracy.
 817     """
 818
 819     def __init__(self, width, id_wid):
 820         FPState.__init__(self, "add_0")
 821         self.mod = FPAddStage0Mod(width)
 822         self.o = self.mod.ospec()
 823
 824     def setup(self, m, i):
 825         """ links module to inputs and outputs
 826         """
 827         self.mod.setup(m, i)
 828
 829         # NOTE: these could be done as combinatorial (merge add0+add1)
 830         m.d.sync += self.o.eq(self.mod.o)
 831
 832     def action(self, m):
 833         m.next = "add_1"
 834
 835
 836 class FPAddStage1Data:
 837
 838     def __init__(self, width, id_wid):
 839         self.z = FPNumBase(width, False)
 840         self.of = Overflow()
 841         self.mid = Signal(id_wid, reset_less=True)
 842
 843     def eq(self, i):
 844         return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
 845
 846
 847
 848 class FPAddStage1Mod(FPState):
 849     """ Second stage of add: preparation for normalisation.
 850         detects when tot sum is too big (tot[27] is kinda a carry bit)
 851     """
 852
 853     def __init__(self, width, id_wid):
 854         self.width = width
 855         self.id_wid = id_wid
 856         self.i = self.ispec()
 857         self.o = self.ospec()
 858
 859     def ispec(self):
 860         return FPAddStage0Data(self.width, self.id_wid)
 861
 862     def ospec(self):
 863         return FPAddStage1Data(self.width, self.id_wid)
 864
 865     def setup(self, m, i):
 866         """ links module to inputs and outputs
 867         """
 868         m.submodules.add1 = self
 869         m.submodules.add1_out_overflow = self.o.of
 870
 871         m.d.comb += self.i.eq(i)
 872
 873     def elaborate(self, platform):
 874         m = Module()
 875         #m.submodules.norm1_in_overflow = self.in_of
 876         #m.submodules.norm1_out_overflow = self.out_of
 877         #m.submodules.norm1_in_z = self.in_z
 878         #m.submodules.norm1_out_z = self.out_z
 879         m.d.comb += self.o.z.eq(self.i.z)
 880         m.d.comb += self.o.mid.eq(self.i.mid)
 881         # tot[-1] (MSB) gets set when the sum overflows. shift result down
 882         with m.If(self.i.tot[-1]):
 883             m.d.comb += [
 884                 self.o.z.m.eq(self.i.tot[4:]),
 885                 self.o.of.m0.eq(self.i.tot[4]),
 886                 self.o.of.guard.eq(self.i.tot[3]),
 887                 self.o.of.round_bit.eq(self.i.tot[2]),
 888                 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
 889                 self.o.z.e.eq(self.i.z.e + 1)
 890         ]
 891         # tot[-1] (MSB) zero case
 892         with m.Else():
 893             m.d.comb += [
 894                 self.o.z.m.eq(self.i.tot[3:]),
 895                 self.o.of.m0.eq(self.i.tot[3]),
 896                 self.o.of.guard.eq(self.i.tot[2]),
 897                 self.o.of.round_bit.eq(self.i.tot[1]),
 898                 self.o.of.sticky.eq(self.i.tot[0])
 899         ]
 900         return m
 901
 902
 903 class FPAddStage1(FPState):
 904
 905     def __init__(self, width, id_wid):
 906         FPState.__init__(self, "add_1")
 907         self.mod = FPAddStage1Mod(width)
 908         self.out_z = FPNumBase(width, False)
 909         self.out_of = Overflow()
 910         self.norm_stb = Signal()
 911
 912     def setup(self, m, i):
 913         """ links module to inputs and outputs
 914         """
 915         self.mod.setup(m, i)
 916
 917         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 918
 919         m.d.sync += self.out_of.eq(self.mod.out_of)
 920         m.d.sync += self.out_z.eq(self.mod.out_z)
 921         m.d.sync += self.norm_stb.eq(1)
 922
 923     def action(self, m):
 924         m.next = "normalise_1"
 925
 926
 927 class FPNormaliseModSingle:
 928
 929     def __init__(self, width):
 930         self.width = width
 931         self.in_z = self.ispec()
 932         self.out_z = self.ospec()
 933
 934     def ispec(self):
 935         return FPNumBase(self.width, False)
 936
 937     def ospec(self):
 938         return FPNumBase(self.width, False)
 939
 940     def setup(self, m, i):
 941         """ links module to inputs and outputs
 942         """
 943         m.submodules.normalise = self
 944         m.d.comb += self.i.eq(i)
 945
 946     def elaborate(self, platform):
 947         m = Module()
 948
 949         mwid = self.out_z.m_width+2
 950         pe = PriorityEncoder(mwid)
 951         m.submodules.norm_pe = pe
 952
 953         m.submodules.norm1_out_z = self.out_z
 954         m.submodules.norm1_in_z = self.in_z
 955
 956         in_z = FPNumBase(self.width, False)
 957         in_of = Overflow()
 958         m.submodules.norm1_insel_z = in_z
 959         m.submodules.norm1_insel_overflow = in_of
 960
 961         espec = (len(in_z.e), True)
 962         ediff_n126 = Signal(espec, reset_less=True)
 963         msr = MultiShiftRMerge(mwid, espec)
 964         m.submodules.multishift_r = msr
 965
 966         m.d.comb += in_z.eq(self.in_z)
 967         m.d.comb += in_of.eq(self.in_of)
 968         # initialise out from in (overridden below)
 969         m.d.comb += self.out_z.eq(in_z)
 970         m.d.comb += self.out_of.eq(in_of)
 971         # normalisation decrease condition
 972         decrease = Signal(reset_less=True)
 973         m.d.comb += decrease.eq(in_z.m_msbzero)
 974         # decrease exponent
 975         with m.If(decrease):
 976             # *sigh* not entirely obvious: count leading zeros (clz)
 977             # with a PriorityEncoder: to find from the MSB
 978             # we reverse the order of the bits.
 979             temp_m = Signal(mwid, reset_less=True)
 980             temp_s = Signal(mwid+1, reset_less=True)
 981             clz = Signal((len(in_z.e), True), reset_less=True)
 982             m.d.comb += [
 983                 # cat round and guard bits back into the mantissa
 984                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
 985                 pe.i.eq(temp_m[::-1]),          # inverted
 986                 clz.eq(pe.o),                   # count zeros from MSB down
 987                 temp_s.eq(temp_m << clz),       # shift mantissa UP
 988                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
 989                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
 990             ]
 991
 992         return m
 993
 994 class FPNorm1Data:
 995
 996     def __init__(self, width, id_wid):
 997         self.roundz = Signal(reset_less=True)
 998         self.z = FPNumBase(width, False)
 999         self.mid = Signal(id_wid, reset_less=True)
1000
1001     def eq(self, i):
1002         return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1003
1004
1005 class FPNorm1ModSingle:
1006
1007     def __init__(self, width, id_wid):
1008         self.width = width
1009         self.id_wid = id_wid
1010         self.i = self.ispec()
1011         self.o = self.ospec()
1012
1013     def ispec(self):
1014         return FPAddStage1Data(self.width, self.id_wid)
1015
1016     def ospec(self):
1017         return FPNorm1Data(self.width, self.id_wid)
1018
1019     def setup(self, m, i):
1020         """ links module to inputs and outputs
1021         """
1022         m.submodules.normalise_1 = self
1023         m.d.comb += self.i.eq(i)
1024
1025     def process(self, i):
1026         return self.o
1027
1028     def elaborate(self, platform):
1029         m = Module()
1030
1031         mwid = self.o.z.m_width+2
1032         pe = PriorityEncoder(mwid)
1033         m.submodules.norm_pe = pe
1034
1035         of = Overflow()
1036         m.d.comb += self.o.roundz.eq(of.roundz)
1037
1038         m.submodules.norm1_out_z = self.o.z
1039         m.submodules.norm1_out_overflow = of
1040         m.submodules.norm1_in_z = self.i.z
1041         m.submodules.norm1_in_overflow = self.i.of
1042
1043         i = self.ispec()
1044         m.submodules.norm1_insel_z = i.z
1045         m.submodules.norm1_insel_overflow = i.of
1046
1047         espec = (len(i.z.e), True)
1048         ediff_n126 = Signal(espec, reset_less=True)
1049         msr = MultiShiftRMerge(mwid, espec)
1050         m.submodules.multishift_r = msr
1051
1052         m.d.comb += i.eq(self.i)
1053         # initialise out from in (overridden below)
1054         m.d.comb += self.o.z.eq(i.z)
1055         m.d.comb += self.o.mid.eq(self.i.mid)
1056         m.d.comb += of.eq(i.of)
1057         # normalisation increase/decrease conditions
1058         decrease = Signal(reset_less=True)
1059         increase = Signal(reset_less=True)
1060         m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1061         m.d.comb += increase.eq(i.z.exp_lt_n126)
1062         # decrease exponent
1063         with m.If(decrease):
1064             # *sigh* not entirely obvious: count leading zeros (clz)
1065             # with a PriorityEncoder: to find from the MSB
1066             # we reverse the order of the bits.
1067             temp_m = Signal(mwid, reset_less=True)
1068             temp_s = Signal(mwid+1, reset_less=True)
1069             clz = Signal((len(i.z.e), True), reset_less=True)
1070             # make sure that the amount to decrease by does NOT
1071             # go below the minimum non-INF/NaN exponent
1072             limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1073                          i.z.exp_sub_n126)
1074             m.d.comb += [
1075                 # cat round and guard bits back into the mantissa
1076                 temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1077                 pe.i.eq(temp_m[::-1]),          # inverted
1078                 clz.eq(limclz),                 # count zeros from MSB down
1079                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1080                 self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
1081                 self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
1082                 of.m0.eq(temp_s[2]),          # copy of mantissa[0]
1083                 # overflow in bits 0..1: got shifted too (leave sticky)
1084                 of.guard.eq(temp_s[1]),       # guard
1085                 of.round_bit.eq(temp_s[0]),   # round
1086             ]
1087         # increase exponent
1088         with m.Elif(increase):
1089             temp_m = Signal(mwid+1, reset_less=True)
1090             m.d.comb += [
1091                 temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1092                               i.z.m)),
1093                 ediff_n126.eq(i.z.N126 - i.z.e),
1094                 # connect multi-shifter to inp/out mantissa (and ediff)
1095                 msr.inp.eq(temp_m),
1096                 msr.diff.eq(ediff_n126),
1097                 self.o.z.m.eq(msr.m[3:]),
1098                 of.m0.eq(temp_s[3]),   # copy of mantissa[0]
1099                 # overflow in bits 0..1: got shifted too (leave sticky)
1100                 of.guard.eq(temp_s[2]),     # guard
1101                 of.round_bit.eq(temp_s[1]), # round
1102                 of.sticky.eq(temp_s[0]),    # sticky
1103                 self.o.z.e.eq(i.z.e + ediff_n126),
1104             ]
1105
1106         return m
1107
1108
1109 class FPNorm1ModMulti:
1110
1111     def __init__(self, width, single_cycle=True):
1112         self.width = width
1113         self.in_select = Signal(reset_less=True)
1114         self.in_z = FPNumBase(width, False)
1115         self.in_of = Overflow()
1116         self.temp_z = FPNumBase(width, False)
1117         self.temp_of = Overflow()
1118         self.out_z = FPNumBase(width, False)
1119         self.out_of = Overflow()
1120
1121     def elaborate(self, platform):
1122         m = Module()
1123
1124         m.submodules.norm1_out_z = self.out_z
1125         m.submodules.norm1_out_overflow = self.out_of
1126         m.submodules.norm1_temp_z = self.temp_z
1127         m.submodules.norm1_temp_of = self.temp_of
1128         m.submodules.norm1_in_z = self.in_z
1129         m.submodules.norm1_in_overflow = self.in_of
1130
1131         in_z = FPNumBase(self.width, False)
1132         in_of = Overflow()
1133         m.submodules.norm1_insel_z = in_z
1134         m.submodules.norm1_insel_overflow = in_of
1135
1136         # select which of temp or in z/of to use
1137         with m.If(self.in_select):
1138             m.d.comb += in_z.eq(self.in_z)
1139             m.d.comb += in_of.eq(self.in_of)
1140         with m.Else():
1141             m.d.comb += in_z.eq(self.temp_z)
1142             m.d.comb += in_of.eq(self.temp_of)
1143         # initialise out from in (overridden below)
1144         m.d.comb += self.out_z.eq(in_z)
1145         m.d.comb += self.out_of.eq(in_of)
1146         # normalisation increase/decrease conditions
1147         decrease = Signal(reset_less=True)
1148         increase = Signal(reset_less=True)
1149         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1150         m.d.comb += increase.eq(in_z.exp_lt_n126)
1151         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1152         # decrease exponent
1153         with m.If(decrease):
1154             m.d.comb += [
1155                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
1156                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1157                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1158                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1159                 self.out_of.round_bit.eq(0),        # reset round bit
1160                 self.out_of.m0.eq(in_of.guard),
1161             ]
1162         # increase exponent
1163         with m.Elif(increase):
1164             m.d.comb += [
1165                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
1166                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1167                 self.out_of.guard.eq(in_z.m[0]),
1168                 self.out_of.m0.eq(in_z.m[1]),
1169                 self.out_of.round_bit.eq(in_of.guard),
1170                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1171             ]
1172
1173         return m
1174
1175
1176 class FPNorm1Single(FPState):
1177
1178     def __init__(self, width, id_wid, single_cycle=True):
1179         FPState.__init__(self, "normalise_1")
1180         self.mod = FPNorm1ModSingle(width)
1181         self.o = self.ospec()
1182         self.out_z = FPNumBase(width, False)
1183         self.out_roundz = Signal(reset_less=True)
1184
1185     def ispec(self):
1186         return self.mod.ispec()
1187
1188     def ospec(self):
1189         return self.mod.ospec()
1190
1191     def setup(self, m, i):
1192         """ links module to inputs and outputs
1193         """
1194         self.mod.setup(m, i)
1195
1196     def action(self, m):
1197         m.next = "round"
1198
1199
1200 class FPNorm1Multi(FPState):
1201
1202     def __init__(self, width, id_wid):
1203         FPState.__init__(self, "normalise_1")
1204         self.mod = FPNorm1ModMulti(width)
1205         self.stb = Signal(reset_less=True)
1206         self.ack = Signal(reset=0, reset_less=True)
1207         self.out_norm = Signal(reset_less=True)
1208         self.in_accept = Signal(reset_less=True)
1209         self.temp_z = FPNumBase(width)
1210         self.temp_of = Overflow()
1211         self.out_z = FPNumBase(width)
1212         self.out_roundz = Signal(reset_less=True)
1213
1214     def setup(self, m, in_z, in_of, norm_stb):
1215         """ links module to inputs and outputs
1216         """
1217         self.mod.setup(m, in_z, in_of, norm_stb,
1218                        self.in_accept, self.temp_z, self.temp_of,
1219                        self.out_z, self.out_norm)
1220
1221         m.d.comb += self.stb.eq(norm_stb)
1222         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1223
1224     def action(self, m):
1225         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1226         m.d.sync += self.temp_of.eq(self.mod.out_of)
1227         m.d.sync += self.temp_z.eq(self.out_z)
1228         with m.If(self.out_norm):
1229             with m.If(self.in_accept):
1230                 m.d.sync += [
1231                     self.ack.eq(1),
1232                 ]
1233             with m.Else():
1234                 m.d.sync += self.ack.eq(0)
1235         with m.Else():
1236             # normalisation not required (or done).
1237             m.next = "round"
1238             m.d.sync += self.ack.eq(1)
1239             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1240
1241
1242 class FPNormToPack(FPState):
1243
1244     def __init__(self, width, id_wid):
1245         FPState.__init__(self, "normalise_1")
1246         self.id_wid = id_wid
1247         self.width = width
1248
1249     def ispec(self):
1250         return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
1251
1252     def ospec(self):
1253         return FPPackData(self.width, self.id_wid) # FPPackMod ospec
1254
1255     def setup(self, m, i):
1256         """ links module to inputs and outputs
1257         """
1258
1259         # Normalisation, Rounding Corrections, Pack - in a chain
1260         nmod = FPNorm1ModSingle(self.width, self.id_wid)
1261         rmod = FPRoundMod(self.width, self.id_wid)
1262         cmod = FPCorrectionsMod(self.width, self.id_wid)
1263         pmod = FPPackMod(self.width, self.id_wid)
1264         chain = StageChain([nmod, rmod, cmod, pmod])
1265         chain.setup(m, i)
1266         self.out_z = pmod.ospec()
1267
1268         m.d.sync += self.out_z.mid.eq(pmod.o.mid)
1269         m.d.sync += self.out_z.z.v.eq(pmod.o.z.v) # outputs packed result
1270
1271     def action(self, m):
1272         m.next = "pack_put_z"
1273
1274
1275 class FPRoundData:
1276
1277     def __init__(self, width, id_wid):
1278         self.z = FPNumBase(width, False)
1279         self.mid = Signal(id_wid, reset_less=True)
1280
1281     def eq(self, i):
1282         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1283
1284
1285 class FPRoundMod:
1286
1287     def __init__(self, width, id_wid):
1288         self.width = width
1289         self.id_wid = id_wid
1290         self.i = self.ispec()
1291         self.out_z = self.ospec()
1292
1293     def ispec(self):
1294         return FPNorm1Data(self.width, self.id_wid)
1295
1296     def ospec(self):
1297         return FPRoundData(self.width, self.id_wid)
1298
1299     def process(self, i):
1300         return self.out_z
1301
1302     def setup(self, m, i):
1303         m.submodules.roundz = self
1304         m.d.comb += self.i.eq(i)
1305
1306     def elaborate(self, platform):
1307         m = Module()
1308         m.d.comb += self.out_z.eq(self.i)
1309         with m.If(self.i.roundz):
1310             m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
1311             with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1312                 m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1313         return m
1314
1315
1316 class FPRound(FPState):
1317
1318     def __init__(self, width, id_wid):
1319         FPState.__init__(self, "round")
1320         self.mod = FPRoundMod(width)
1321         self.out_z = self.ospec()
1322
1323     def ispec(self):
1324         return self.mod.ispec()
1325
1326     def ospec(self):
1327         return self.mod.ospec()
1328
1329     def setup(self, m, i):
1330         """ links module to inputs and outputs
1331         """
1332         self.mod.setup(m, i)
1333
1334         self.idsync(m)
1335         m.d.sync += self.out_z.eq(self.mod.out_z)
1336         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1337
1338     def action(self, m):
1339         m.next = "corrections"
1340
1341
1342 class FPCorrectionsMod:
1343
1344     def __init__(self, width, id_wid):
1345         self.width = width
1346         self.id_wid = id_wid
1347         self.i = self.ispec()
1348         self.out_z = self.ospec()
1349
1350     def ispec(self):
1351         return FPRoundData(self.width, self.id_wid)
1352
1353     def ospec(self):
1354         return FPRoundData(self.width, self.id_wid)
1355
1356     def process(self, i):
1357         return self.out_z
1358
1359     def setup(self, m, i):
1360         """ links module to inputs and outputs
1361         """
1362         m.submodules.corrections = self
1363         m.d.comb += self.i.eq(i)
1364
1365     def elaborate(self, platform):
1366         m = Module()
1367         m.submodules.corr_in_z = self.i.z
1368         m.submodules.corr_out_z = self.out_z.z
1369         m.d.comb += self.out_z.eq(self.i)
1370         with m.If(self.i.z.is_denormalised):
1371             m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
1372         return m
1373
1374
1375 class FPCorrections(FPState):
1376
1377     def __init__(self, width, id_wid):
1378         FPState.__init__(self, "corrections")
1379         self.mod = FPCorrectionsMod(width)
1380         self.out_z = self.ospec()
1381
1382     def ispec(self):
1383         return self.mod.ispec()
1384
1385     def ospec(self):
1386         return self.mod.ospec()
1387
1388     def setup(self, m, in_z):
1389         """ links module to inputs and outputs
1390         """
1391         self.mod.setup(m, in_z)
1392
1393         m.d.sync += self.out_z.eq(self.mod.out_z)
1394         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1395
1396     def action(self, m):
1397         m.next = "pack"
1398
1399
1400 class FPPackData:
1401
1402     def __init__(self, width, id_wid):
1403         self.z = FPNumOut(width, False)
1404         self.mid = Signal(id_wid, reset_less=True)
1405
1406     def eq(self, i):
1407         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1408
1409
1410 class FPPackMod:
1411
1412     def __init__(self, width, id_wid):
1413         self.width = width
1414         self.id_wid = id_wid
1415         self.i = self.ispec()
1416         self.o = self.ospec()
1417
1418     def ispec(self):
1419         return FPRoundData(self.width, self.id_wid)
1420
1421     def ospec(self):
1422         return FPPackData(self.width, self.id_wid)
1423
1424     def process(self, i):
1425         return self.o
1426
1427     def setup(self, m, in_z):
1428         """ links module to inputs and outputs
1429         """
1430         m.submodules.pack = self
1431         m.d.comb += self.i.eq(in_z)
1432
1433     def elaborate(self, platform):
1434         m = Module()
1435         m.submodules.pack_in_z = self.i.z
1436         m.d.comb += self.o.mid.eq(self.i.mid)
1437         with m.If(self.i.z.is_overflowed):
1438             m.d.comb += self.o.z.inf(self.i.z.s)
1439         with m.Else():
1440             m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1441         return m
1442
1443
1444 class FPPackData:
1445     def __init__(self, width, id_wid):
1446         self.z = FPNumOut(width, False)
1447         self.mid = Signal(id_wid, reset_less=True)
1448
1449     def eq(self, i):
1450         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1451
1452
1453 class FPPack(FPState):
1454
1455     def __init__(self, width, id_wid):
1456         FPState.__init__(self, "pack")
1457         self.mod = FPPackMod(width)
1458         self.out_z = self.ospec()
1459
1460     def ispec(self):
1461         return self.mod.ispec()
1462
1463     def ospec(self):
1464         return self.mod.ospec()
1465
1466     def setup(self, m, in_z):
1467         """ links module to inputs and outputs
1468         """
1469         self.mod.setup(m, in_z)
1470
1471         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1472         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1473
1474     def action(self, m):
1475         m.next = "pack_put_z"
1476
1477
1478 class FPPutZ(FPState):
1479
1480     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1481         FPState.__init__(self, state)
1482         if to_state is None:
1483             to_state = "get_ops"
1484         self.to_state = to_state
1485         self.in_z = in_z
1486         self.out_z = out_z
1487         self.in_mid = in_mid
1488         self.out_mid = out_mid
1489
1490     def action(self, m):
1491         if self.in_mid is not None:
1492             m.d.sync += self.out_mid.eq(self.in_mid)
1493         m.d.sync += [
1494           self.out_z.z.v.eq(self.in_z.v)
1495         ]
1496         with m.If(self.out_z.z.stb & self.out_z.z.ack):
1497             m.d.sync += self.out_z.z.stb.eq(0)
1498             m.next = self.to_state
1499         with m.Else():
1500             m.d.sync += self.out_z.z.stb.eq(1)
1501
1502
1503 class FPPutZIdx(FPState):
1504
1505     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1506         FPState.__init__(self, state)
1507         if to_state is None:
1508             to_state = "get_ops"
1509         self.to_state = to_state
1510         self.in_z = in_z
1511         self.out_zs = out_zs
1512         self.in_mid = in_mid
1513
1514     def action(self, m):
1515         outz_stb = Signal(reset_less=True)
1516         outz_ack = Signal(reset_less=True)
1517         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1518                      outz_ack.eq(self.out_zs[self.in_mid].ack),
1519                     ]
1520         m.d.sync += [
1521           self.out_zs[self.in_mid].v.eq(self.in_z.v)
1522         ]
1523         with m.If(outz_stb & outz_ack):
1524             m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1525             m.next = self.to_state
1526         with m.Else():
1527             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1528
1529 class FPADDBaseData:
1530
1531     def __init__(self, width, id_wid):
1532         self.width = width
1533         self.id_wid = id_wid
1534         self.a  = Signal(width)
1535         self.b  = Signal(width)
1536         self.mid = Signal(id_wid, reset_less=True)
1537
1538     def eq(self, i):
1539         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1540
1541
1542 class FPOpData:
1543     def __init__(self, width, id_wid):
1544         self.z = FPOp(width)
1545         self.mid = Signal(id_wid, reset_less=True)
1546
1547     def eq(self, i):
1548         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1549
1550
1551 class FPADDBaseMod:
1552
1553     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1554         """ IEEE754 FP Add
1555
1556             * width: bit-width of IEEE754.  supported: 16, 32, 64
1557             * id_wid: an identifier that is sync-connected to the input
1558             * single_cycle: True indicates each stage to complete in 1 clock
1559             * compact: True indicates a reduced number of stages
1560         """
1561         self.width = width
1562         self.id_wid = id_wid
1563         self.single_cycle = single_cycle
1564         self.compact = compact
1565
1566         self.in_t = Trigger()
1567         self.i = self.ispec()
1568         self.o = self.ospec()
1569
1570         self.states = []
1571
1572     def ispec(self):
1573         return FPADDBaseData(self.width, self.id_wid)
1574
1575     def ospec(self):
1576         return FPOpData(self.width, self.id_wid)
1577
1578     def add_state(self, state):
1579         self.states.append(state)
1580         return state
1581
1582     def get_fragment(self, platform=None):
1583         """ creates the HDL code-fragment for FPAdd
1584         """
1585         m = Module()
1586         m.submodules.out_z = self.o.z
1587         m.submodules.in_t = self.in_t
1588         if self.compact:
1589             self.get_compact_fragment(m, platform)
1590         else:
1591             self.get_longer_fragment(m, platform)
1592
1593         with m.FSM() as fsm:
1594
1595             for state in self.states:
1596                 with m.State(state.state_from):
1597                     state.action(m)
1598
1599         return m
1600
1601     def get_longer_fragment(self, m, platform=None):
1602
1603         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1604                                       self.width))
1605         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1606         a = get.out_op1
1607         b = get.out_op2
1608
1609         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1610         sc.setup(m, a, b, self.in_mid)
1611
1612         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1613         dn.setup(m, a, b, sc.in_mid)
1614
1615         if self.single_cycle:
1616             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1617             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1618         else:
1619             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1620             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1621
1622         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1623         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1624
1625         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1626         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1627
1628         if self.single_cycle:
1629             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1630             n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1631         else:
1632             n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1633             n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1634
1635         rn = self.add_state(FPRound(self.width, self.id_wid))
1636         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1637
1638         cor = self.add_state(FPCorrections(self.width, self.id_wid))
1639         cor.setup(m, rn.out_z, rn.in_mid)
1640
1641         pa = self.add_state(FPPack(self.width, self.id_wid))
1642         pa.setup(m, cor.out_z, rn.in_mid)
1643
1644         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1645                                     pa.in_mid, self.out_mid))
1646
1647         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1648                                     pa.in_mid, self.out_mid))
1649
1650     def get_compact_fragment(self, m, platform=None):
1651
1652         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1653                                       self.width, self.id_wid))
1654         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1655
1656         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1657         sc.setup(m, get.o)
1658
1659         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1660         alm.setup(m, sc.o)
1661
1662         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1663         n1.setup(m, alm.a1o)
1664
1665         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
1666                                     n1.out_z.mid, self.o.mid))
1667
1668         pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
1669                                     sc.o.mid, self.o.mid))
1670
1671
1672 class FPADDBase(FPState):
1673
1674     def __init__(self, width, id_wid=None, single_cycle=False):
1675         """ IEEE754 FP Add
1676
1677             * width: bit-width of IEEE754.  supported: 16, 32, 64
1678             * id_wid: an identifier that is sync-connected to the input
1679             * single_cycle: True indicates each stage to complete in 1 clock
1680         """
1681         FPState.__init__(self, "fpadd")
1682         self.width = width
1683         self.single_cycle = single_cycle
1684         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1685         self.o = self.ospec()
1686
1687         self.in_t = Trigger()
1688         self.i = self.ispec()
1689
1690         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1691         self.in_accept = Signal(reset_less=True)
1692         self.add_stb = Signal(reset_less=True)
1693         self.add_ack = Signal(reset=0, reset_less=True)
1694
1695     def ispec(self):
1696         return self.mod.ispec()
1697
1698     def ospec(self):
1699         return self.mod.ospec()
1700
1701     def setup(self, m, i, add_stb, in_mid):
1702         m.d.comb += [self.i.eq(i),
1703                      self.mod.i.eq(self.i),
1704                      self.z_done.eq(self.mod.o.z.trigger),
1705                      #self.add_stb.eq(add_stb),
1706                      self.mod.in_t.stb.eq(self.in_t.stb),
1707                      self.in_t.ack.eq(self.mod.in_t.ack),
1708                      self.o.mid.eq(self.mod.o.mid),
1709                      self.o.z.v.eq(self.mod.o.z.v),
1710                      self.o.z.stb.eq(self.mod.o.z.stb),
1711                      self.mod.o.z.ack.eq(self.o.z.ack),
1712                     ]
1713
1714         m.d.sync += self.add_stb.eq(add_stb)
1715         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1716         m.d.sync += self.o.z.ack.eq(0) # likewise
1717         #m.d.sync += self.in_t.stb.eq(0)
1718
1719         m.submodules.fpadd = self.mod
1720
1721     def action(self, m):
1722
1723         # in_accept is set on incoming strobe HIGH and ack LOW.
1724         m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1725
1726         #with m.If(self.in_t.ack):
1727         #    m.d.sync += self.in_t.stb.eq(0)
1728         with m.If(~self.z_done):
1729             # not done: test for accepting an incoming operand pair
1730             with m.If(self.in_accept):
1731                 m.d.sync += [
1732                     self.add_ack.eq(1), # acknowledge receipt...
1733                     self.in_t.stb.eq(1), # initiate add
1734                 ]
1735             with m.Else():
1736                 m.d.sync += [self.add_ack.eq(0),
1737                              self.in_t.stb.eq(0),
1738                              self.o.z.ack.eq(1),
1739                             ]
1740         with m.Else():
1741             # done: acknowledge, and write out id and value
1742             m.d.sync += [self.add_ack.eq(1),
1743                          self.in_t.stb.eq(0)
1744                         ]
1745             m.next = "put_z"
1746
1747             return
1748
1749             if self.in_mid is not None:
1750                 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1751
1752             m.d.sync += [
1753               self.out_z.v.eq(self.mod.out_z.v)
1754             ]
1755             # move to output state on detecting z ack
1756             with m.If(self.out_z.trigger):
1757                 m.d.sync += self.out_z.stb.eq(0)
1758                 m.next = "put_z"
1759             with m.Else():
1760                 m.d.sync += self.out_z.stb.eq(1)
1761
1762
1763 class ResArray:
1764     def __init__(self, width, id_wid):
1765         self.width = width
1766         self.id_wid = id_wid
1767         res = []
1768         for i in range(rs_sz):
1769             out_z = FPOp(width)
1770             out_z.name = "out_z_%d" % i
1771             res.append(out_z)
1772         self.res = Array(res)
1773         self.in_z = FPOp(width)
1774         self.in_mid = Signal(self.id_wid, reset_less=True)
1775
1776     def setup(self, m, in_z, in_mid):
1777         m.d.comb += [self.in_z.eq(in_z),
1778                      self.in_mid.eq(in_mid)]
1779
1780     def get_fragment(self, platform=None):
1781         """ creates the HDL code-fragment for FPAdd
1782         """
1783         m = Module()
1784         m.submodules.res_in_z = self.in_z
1785         m.submodules += self.res
1786
1787         return m
1788
1789     def ports(self):
1790         res = []
1791         for z in self.res:
1792             res += z.ports()
1793         return res
1794
1795
1796 class FPADD(FPID):
1797     """ FPADD: stages as follows:
1798
1799         FPGetOp (a)
1800            |
1801         FPGetOp (b)
1802            |
1803         FPAddBase---> FPAddBaseMod
1804            |            |
1805         PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1806
1807         FPAddBase is tricky: it is both a stage and *has* stages.
1808         Connection to FPAddBaseMod therefore requires an in stb/ack
1809         and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
1810         needs to be the thing that raises the incoming stb.
1811     """
1812
1813     def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1814         """ IEEE754 FP Add
1815
1816             * width: bit-width of IEEE754.  supported: 16, 32, 64
1817             * id_wid: an identifier that is sync-connected to the input
1818             * single_cycle: True indicates each stage to complete in 1 clock
1819         """
1820         self.width = width
1821         self.id_wid = id_wid
1822         self.single_cycle = single_cycle
1823
1824         #self.out_z = FPOp(width)
1825         self.ids = FPID(id_wid)
1826
1827         rs = []
1828         for i in range(rs_sz):
1829             in_a  = FPOp(width)
1830             in_b  = FPOp(width)
1831             in_a.name = "in_a_%d" % i
1832             in_b.name = "in_b_%d" % i
1833             rs.append((in_a, in_b))
1834         self.rs = Array(rs)
1835
1836         res = []
1837         for i in range(rs_sz):
1838             out_z = FPOp(width)
1839             out_z.name = "out_z_%d" % i
1840             res.append(out_z)
1841         self.res = Array(res)
1842
1843         self.states = []
1844
1845     def add_state(self, state):
1846         self.states.append(state)
1847         return state
1848
1849     def get_fragment(self, platform=None):
1850         """ creates the HDL code-fragment for FPAdd
1851         """
1852         m = Module()
1853         m.submodules += self.rs
1854
1855         in_a = self.rs[0][0]
1856         in_b = self.rs[0][1]
1857
1858         geta = self.add_state(FPGetOp("get_a", "get_b",
1859                                       in_a, self.width))
1860         geta.setup(m, in_a)
1861         a = geta.out_op
1862
1863         getb = self.add_state(FPGetOp("get_b", "fpadd",
1864                                       in_b, self.width))
1865         getb.setup(m, in_b)
1866         b = getb.out_op
1867
1868         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1869         ab = self.add_state(ab)
1870         abd = ab.ispec() # create an input spec object for FPADDBase
1871         m.d.sync += [abd.a.eq(a), abd.b.eq(b), abd.mid.eq(self.ids.in_mid)]
1872         ab.setup(m, abd, getb.out_decode, self.ids.in_mid)
1873         o = ab.o
1874
1875         pz = self.add_state(FPPutZIdx("put_z", o.z, self.res,
1876                                     o.mid, "get_a"))
1877
1878         with m.FSM() as fsm:
1879
1880             for state in self.states:
1881                 with m.State(state.state_from):
1882                     state.action(m)
1883
1884         return m
1885
1886
1887 if __name__ == "__main__":
1888     if True:
1889         alu = FPADD(width=32, id_wid=5, single_cycle=True)
1890         main(alu, ports=alu.rs[0][0].ports() + \
1891                         alu.rs[0][1].ports() + \
1892                         alu.res[0].ports() + \
1893                         [alu.ids.in_mid, alu.ids.out_mid])
1894     else:
1895         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1896         main(alu, ports=[alu.in_a, alu.in_b] + \
1897                         alu.in_t.ports() + \
1898                         alu.out_z.ports() + \
1899                         [alu.in_mid, alu.out_mid])
1900
1901
1902     # works... but don't use, just do "python fname.py convert -t v"
1903     #print (verilog.convert(alu, ports=[
1904     #                        ports=alu.in_a.ports() + \
1905     #                              alu.in_b.ports() + \
1906     #                              alu.out_z.ports())