src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
   9
  10
  11 class FPState(FPBase):
  12     def __init__(self, state_from):
  13         self.state_from = state_from
  14
  15     def set_inputs(self, inputs):
  16         self.inputs = inputs
  17         for k,v in inputs.items():
  18             setattr(self, k, v)
  19
  20     def set_outputs(self, outputs):
  21         self.outputs = outputs
  22         for k,v in outputs.items():
  23             setattr(self, k, v)
  24
  25
  26 class FPGetOpMod:
  27     def __init__(self, width):
  28         self.in_op = FPOp(width)
  29         self.out_op = FPNumIn(self.in_op, width)
  30         self.out_decode = Signal(reset_less=True)
  31
  32     def setup(self, m, in_op, out_op, out_decode):
  33         """ links module to inputs and outputs
  34         """
  35         m.d.comb += self.in_op.copy(in_op)
  36         m.d.comb += out_op.v.eq(self.out_op.v)
  37         m.d.comb += out_decode.eq(self.out_decode)
  38
  39     def elaborate(self, platform):
  40         m = Module()
  41         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
  42         #m.submodules.get_op_in = self.in_op
  43         m.submodules.get_op_out = self.out_op
  44         with m.If(self.out_decode):
  45             m.d.comb += [
  46                 self.out_op.decode(self.in_op.v),
  47             ]
  48         return m
  49
  50
  51 class FPGetOp(FPState):
  52     """ gets operand
  53     """
  54
  55     def __init__(self, in_state, out_state, in_op, width):
  56         FPState.__init__(self, in_state)
  57         self.out_state = out_state
  58         self.mod = FPGetOpMod(width)
  59         self.in_op = in_op
  60         self.out_op = FPNumIn(in_op, width)
  61         self.out_decode = Signal(reset_less=True)
  62
  63     def action(self, m):
  64         with m.If(self.out_decode):
  65             m.next = self.out_state
  66             m.d.sync += [
  67                 self.in_op.ack.eq(0),
  68                 self.out_op.copy(self.mod.out_op)
  69             ]
  70         with m.Else():
  71             m.d.sync += self.in_op.ack.eq(1)
  72
  73
  74 class FPGetOpB(FPState):
  75     """ gets operand b
  76     """
  77
  78     def __init__(self, in_b, width):
  79         FPState.__init__(self, "get_b")
  80         self.in_b = in_b
  81         self.b = FPNumIn(self.in_b, width)
  82
  83     def action(self, m):
  84         self.get_op(m, self.in_b, self.b, "special_cases")
  85
  86
  87 class FPAddSpecialCasesMod:
  88     """ special cases: NaNs, infs, zeros, denormalised
  89         NOTE: some of these are unique to add.  see "Special Operations"
  90         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  91     """
  92
  93     def __init__(self, width):
  94         self.in_a = FPNumBase(width)
  95         self.in_b = FPNumBase(width)
  96         self.out_z = FPNumOut(width, False)
  97         self.out_do_z = Signal(reset_less=True)
  98
  99     def setup(self, m, in_a, in_b, out_z, out_do_z):
 100         """ links module to inputs and outputs
 101         """
 102         m.d.comb += self.in_a.copy(in_a)
 103         m.d.comb += self.in_b.copy(in_b)
 104         m.d.comb += out_z.v.eq(self.out_z.v)
 105         m.d.comb += out_do_z.eq(self.out_do_z)
 106
 107     def elaborate(self, platform):
 108         m = Module()
 109
 110         m.submodules.sc_in_a = self.in_a
 111         m.submodules.sc_in_b = self.in_b
 112         m.submodules.sc_out_z = self.out_z
 113
 114         s_nomatch = Signal()
 115         m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
 116
 117         m_match = Signal()
 118         m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
 119
 120         # if a is NaN or b is NaN return NaN
 121         with m.If(self.in_a.is_nan | self.in_b.is_nan):
 122             m.d.comb += self.out_do_z.eq(1)
 123             m.d.comb += self.out_z.nan(0)
 124
 125         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 126         # under review
 127
 128         ## if a is zero and b is NaN return -b
 129         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 130         #    m.d.comb += self.out_do_z.eq(1)
 131         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 132
 133         ## if b is zero and a is NaN return -a
 134         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 135         #    m.d.comb += self.out_do_z.eq(1)
 136         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 137
 138         ## if a is -zero and b is NaN return -b
 139         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 140         #    m.d.comb += self.out_do_z.eq(1)
 141         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 142
 143         ## if b is -zero and a is NaN return -a
 144         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 145         #    m.d.comb += self.out_do_z.eq(1)
 146         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 147
 148         # if a is inf return inf (or NaN)
 149         with m.Elif(self.in_a.is_inf):
 150             m.d.comb += self.out_do_z.eq(1)
 151             m.d.comb += self.out_z.inf(self.in_a.s)
 152             # if a is inf and signs don't match return NaN
 153             with m.If(self.in_b.exp_128 & s_nomatch):
 154                 m.d.comb += self.out_z.nan(0)
 155
 156         # if b is inf return inf
 157         with m.Elif(self.in_b.is_inf):
 158             m.d.comb += self.out_do_z.eq(1)
 159             m.d.comb += self.out_z.inf(self.in_b.s)
 160
 161         # if a is zero and b zero return signed-a/b
 162         with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
 163             m.d.comb += self.out_do_z.eq(1)
 164             m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
 165                                           self.in_b.e,
 166                                           self.in_b.m[3:-1])
 167
 168         # if a is zero return b
 169         with m.Elif(self.in_a.is_zero):
 170             m.d.comb += self.out_do_z.eq(1)
 171             m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
 172                                       self.in_b.m[3:-1])
 173
 174         # if b is zero return a
 175         with m.Elif(self.in_b.is_zero):
 176             m.d.comb += self.out_do_z.eq(1)
 177             m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
 178                                       self.in_a.m[3:-1])
 179
 180         # if a equal to -b return zero (+ve zero)
 181         with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
 182             m.d.comb += self.out_do_z.eq(1)
 183             m.d.comb += self.out_z.zero(0)
 184
 185         # Denormalised Number checks
 186         with m.Else():
 187             m.d.comb += self.out_do_z.eq(0)
 188
 189         return m
 190
 191
 192 class FPAddSpecialCases(FPState):
 193     """ special cases: NaNs, infs, zeros, denormalised
 194         NOTE: some of these are unique to add.  see "Special Operations"
 195         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 196     """
 197
 198     def __init__(self, width):
 199         FPState.__init__(self, "special_cases")
 200         self.mod = FPAddSpecialCasesMod(width)
 201         self.out_z = FPNumOut(width, False)
 202         self.out_do_z = Signal(reset_less=True)
 203
 204     def action(self, m):
 205         with m.If(self.out_do_z):
 206             m.d.sync += self.z.v.eq(self.out_z.v) # only take the output
 207             m.next = "put_z"
 208         with m.Else():
 209             m.next = "denormalise"
 210
 211
 212 class FPAddDeNormMod(FPState):
 213
 214     def __init__(self, width):
 215         self.in_a = FPNumBase(width)
 216         self.in_b = FPNumBase(width)
 217         self.out_a = FPNumBase(width)
 218         self.out_b = FPNumBase(width)
 219
 220     def setup(self, m, in_a, in_b, out_a, out_b):
 221         """ links module to inputs and outputs
 222         """
 223         m.d.comb += self.in_a.copy(in_a)
 224         m.d.comb += self.in_b.copy(in_b)
 225         m.d.comb += out_a.copy(self.out_a)
 226         m.d.comb += out_b.copy(self.out_b)
 227
 228     def elaborate(self, platform):
 229         m = Module()
 230         m.submodules.denorm_in_a = self.in_a
 231         m.submodules.denorm_in_b = self.in_b
 232         m.submodules.denorm_out_a = self.out_a
 233         m.submodules.denorm_out_b = self.out_b
 234         # hmmm, don't like repeating identical code
 235         m.d.comb += self.out_a.copy(self.in_a)
 236         with m.If(self.in_a.exp_n127):
 237             m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
 238         with m.Else():
 239             m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
 240
 241         m.d.comb += self.out_b.copy(self.in_b)
 242         with m.If(self.in_b.exp_n127):
 243             m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
 244         with m.Else():
 245             m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
 246
 247         return m
 248
 249
 250 class FPAddDeNorm(FPState):
 251
 252     def __init__(self, width):
 253         FPState.__init__(self, "denormalise")
 254         self.mod = FPAddDeNormMod(width)
 255         self.out_a = FPNumBase(width)
 256         self.out_b = FPNumBase(width)
 257
 258     def action(self, m):
 259         # Denormalised Number checks
 260         m.next = "align"
 261         m.d.sync += self.a.copy(self.out_a)
 262         m.d.sync += self.b.copy(self.out_b)
 263
 264
 265 class FPAddAlignMultiMod(FPState):
 266
 267     def __init__(self, width):
 268         self.in_a = FPNumBase(width)
 269         self.in_b = FPNumBase(width)
 270         self.out_a = FPNumIn(None, width)
 271         self.out_b = FPNumIn(None, width)
 272         self.exp_eq = Signal(reset_less=True)
 273
 274     def setup(self, m, in_a, in_b, out_a, out_b, exp_eq):
 275         """ links module to inputs and outputs
 276         """
 277         m.d.comb += self.in_a.copy(in_a)
 278         m.d.comb += self.in_b.copy(in_b)
 279         m.d.comb += out_a.copy(self.out_a)
 280         m.d.comb += out_b.copy(self.out_b)
 281         m.d.comb += exp_eq.eq(self.exp_eq)
 282
 283     def elaborate(self, platform):
 284         # This one however (single-cycle) will do the shift
 285         # in one go.
 286
 287         m = Module()
 288
 289         #m.submodules.align_in_a = self.in_a
 290         #m.submodules.align_in_b = self.in_b
 291         m.submodules.align_out_a = self.out_a
 292         m.submodules.align_out_b = self.out_b
 293
 294         # NOTE: this does *not* do single-cycle multi-shifting,
 295         #       it *STAYS* in the align state until exponents match
 296
 297         # exponent of a greater than b: shift b down
 298         m.d.comb += self.exp_eq.eq(0)
 299         m.d.comb += self.out_a.copy(self.in_a)
 300         m.d.comb += self.out_b.copy(self.in_b)
 301         agtb = Signal(reset_less=True)
 302         altb = Signal(reset_less=True)
 303         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 304         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 305         with m.If(agtb):
 306             m.d.comb += self.out_b.shift_down(self.in_b)
 307         # exponent of b greater than a: shift a down
 308         with m.Elif(altb):
 309             m.d.comb += self.out_a.shift_down(self.in_a)
 310         # exponents equal: move to next stage.
 311         with m.Else():
 312             m.d.comb += self.exp_eq.eq(1)
 313         return m
 314
 315
 316 class FPAddAlignMulti(FPState):
 317
 318     def __init__(self, width):
 319         FPState.__init__(self, "align")
 320         self.mod = FPAddAlignMultiMod(width)
 321         self.out_a = FPNumIn(None, width)
 322         self.out_b = FPNumIn(None, width)
 323         self.exp_eq = Signal(reset_less=True)
 324
 325     def action(self, m):
 326         m.d.sync += self.a.copy(self.out_a)
 327         m.d.sync += self.b.copy(self.out_b)
 328         with m.If(self.exp_eq):
 329             m.next = "add_0"
 330
 331
 332 class FPAddAlignSingleMod:
 333
 334     def __init__(self, width):
 335         self.in_a = FPNumBase(width)
 336         self.in_b = FPNumBase(width)
 337         self.out_a = FPNumIn(None, width)
 338         self.out_b = FPNumIn(None, width)
 339         #self.out_a = FPNumBase(width)
 340         #self.out_b = FPNumBase(width)
 341
 342     def setup(self, m, in_a, in_b, out_a, out_b):
 343         """ links module to inputs and outputs
 344         """
 345         m.d.comb += self.in_a.copy(in_a)
 346         m.d.comb += self.in_b.copy(in_b)
 347         m.d.comb += out_a.copy(self.out_a)
 348         m.d.comb += out_b.copy(self.out_b)
 349
 350     def elaborate(self, platform):
 351         # This one however (single-cycle) will do the shift
 352         # in one go.
 353
 354         m = Module()
 355
 356         #m.submodules.align_in_a = self.in_a
 357         #m.submodules.align_in_b = self.in_b
 358         m.submodules.align_out_a = self.out_a
 359         m.submodules.align_out_b = self.out_b
 360
 361         # XXX TODO: the shifter used here is quite expensive
 362         # having only one would be better
 363
 364         ediff = Signal((len(self.in_a.e), True), reset_less=True)
 365         ediffr = Signal((len(self.in_a.e), True), reset_less=True)
 366         m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
 367         m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
 368         m.d.comb += self.out_a.copy(self.in_a)
 369         m.d.comb += self.out_b.copy(self.in_b)
 370         with m.If(ediff > 0):
 371             m.d.comb += self.out_b.shift_down_multi(ediff)
 372         # exponent of b greater than a: shift a down
 373         with m.Elif(ediff < 0):
 374             m.d.comb += self.out_a.shift_down_multi(ediffr)
 375         return m
 376
 377
 378 class FPAddAlignSingle(FPState):
 379
 380     def __init__(self, width):
 381         FPState.__init__(self, "align")
 382         self.mod = FPAddAlignSingleMod(width)
 383         self.out_a = FPNumIn(None, width)
 384         self.out_b = FPNumIn(None, width)
 385
 386     def action(self, m):
 387         m.d.sync += self.a.copy(self.out_a)
 388         m.d.sync += self.b.copy(self.out_b)
 389         m.next = "add_0"
 390
 391
 392 class FPAddStage0Mod:
 393
 394     def __init__(self, width):
 395         self.in_a = FPNumBase(width)
 396         self.in_b = FPNumBase(width)
 397         self.in_z = FPNumBase(width, False)
 398         self.out_z = FPNumBase(width, False)
 399         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 400
 401     def elaborate(self, platform):
 402         m = Module()
 403         m.submodules.add0_in_a = self.in_a
 404         m.submodules.add0_in_b = self.in_b
 405         #m.submodules.add0_in_z = self.in_z
 406         #m.submodules.add0_out_z = self.out_z
 407
 408         m.d.comb += self.out_z.e.eq(self.in_a.e)
 409
 410         # store intermediate tests (and zero-extended mantissas)
 411         seq = Signal(reset_less=True)
 412         mge = Signal(reset_less=True)
 413         am0 = Signal(len(self.in_a.m)+1, reset_less=True)
 414         bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
 415         m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
 416                      mge.eq(self.in_a.m >= self.in_b.m),
 417                      am0.eq(Cat(self.in_a.m, 0)),
 418                      bm0.eq(Cat(self.in_b.m, 0))
 419                     ]
 420         # same-sign (both negative or both positive) add mantissas
 421         with m.If(seq):
 422             m.d.comb += [
 423                 self.out_tot.eq(am0 + bm0),
 424                 self.out_z.s.eq(self.in_a.s)
 425             ]
 426         # a mantissa greater than b, use a
 427         with m.Elif(mge):
 428             m.d.comb += [
 429                 self.out_tot.eq(am0 - bm0),
 430                 self.out_z.s.eq(self.in_a.s)
 431             ]
 432         # b mantissa greater than a, use b
 433         with m.Else():
 434             m.d.comb += [
 435                 self.out_tot.eq(bm0 - am0),
 436                 self.out_z.s.eq(self.in_b.s)
 437         ]
 438         return m
 439
 440
 441 class FPAddStage0(FPState):
 442     """ First stage of add.  covers same-sign (add) and subtract
 443         special-casing when mantissas are greater or equal, to
 444         give greatest accuracy.
 445     """
 446
 447     def __init__(self, width):
 448         FPState.__init__(self, "add_0")
 449         self.mod = FPAddStage0Mod(width)
 450         self.out_z = FPNumBase(width, False)
 451         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 452
 453     def setup(self, m, in_a, in_b, in_z):
 454         """ links module to inputs and outputs
 455         """
 456         m.submodules.add0 = self.mod
 457
 458         m.d.comb += self.mod.in_a.copy(in_a)
 459         m.d.comb += self.mod.in_b.copy(in_b)
 460         m.d.comb += self.mod.in_z.copy(in_z)
 461
 462         m.d.comb += self.out_z.copy(self.mod.out_z)
 463         m.d.comb += self.out_tot.eq(self.mod.out_tot)
 464
 465     def action(self, m):
 466         m.next = "add_1"
 467         m.d.sync += self.z.copy(self.out_z)
 468
 469
 470 class FPAddStage1Mod(FPState):
 471     """ Second stage of add: preparation for normalisation.
 472         detects when tot sum is too big (tot[27] is kinda a carry bit)
 473     """
 474
 475     def __init__(self, width):
 476         self.out_norm = Signal(reset_less=True)
 477         self.in_z = FPNumBase(width, False)
 478         self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
 479         self.out_z = FPNumBase(width, False)
 480         self.out_of = Overflow()
 481
 482     def setup(self, m, in_tot, in_z, out_z, out_of):
 483         """ links module to inputs and outputs
 484         """
 485         m.d.comb += self.in_z.copy(in_z)
 486         m.d.comb += self.in_tot.eq(in_tot)
 487         #m.d.comb += out_z.copy(self.out_z)
 488         #m.d.comb += out_of.copy(self.out_of)
 489
 490     def elaborate(self, platform):
 491         m = Module()
 492         #m.submodules.norm1_in_overflow = self.in_of
 493         #m.submodules.norm1_out_overflow = self.out_of
 494         #m.submodules.norm1_in_z = self.in_z
 495         #m.submodules.norm1_out_z = self.out_z
 496         m.d.comb += self.out_z.copy(self.in_z)
 497         # tot[27] gets set when the sum overflows. shift result down
 498         with m.If(self.in_tot[-1]):
 499             m.d.comb += [
 500                 self.out_z.m.eq(self.in_tot[4:]),
 501                 self.out_of.m0.eq(self.in_tot[4]),
 502                 self.out_of.guard.eq(self.in_tot[3]),
 503                 self.out_of.round_bit.eq(self.in_tot[2]),
 504                 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
 505                 self.out_z.e.eq(self.in_z.e + 1)
 506         ]
 507         # tot[27] zero case
 508         with m.Else():
 509             m.d.comb += [
 510                 self.out_z.m.eq(self.in_tot[3:]),
 511                 self.out_of.m0.eq(self.in_tot[3]),
 512                 self.out_of.guard.eq(self.in_tot[2]),
 513                 self.out_of.round_bit.eq(self.in_tot[1]),
 514                 self.out_of.sticky.eq(self.in_tot[0])
 515         ]
 516         return m
 517
 518
 519 class FPAddStage1(FPState):
 520
 521     def __init__(self, width):
 522         FPState.__init__(self, "add_1")
 523         self.mod = FPAddStage1Mod(width)
 524         self.out_z = FPNumBase(width, False)
 525         self.out_of = Overflow()
 526         self.norm_stb = Signal()
 527
 528     def action(self, m):
 529         m.submodules.add1_out_overflow = self.out_of
 530         m.d.sync += self.out_of.copy(self.mod.out_of)
 531         m.d.sync += self.out_z.copy(self.mod.out_z)
 532         m.d.sync += self.norm_stb.eq(1)
 533         m.next = "normalise_1"
 534
 535
 536 class FPNorm1Mod:
 537
 538     def __init__(self, width):
 539         self.width = width
 540         self.in_select = Signal(reset_less=True)
 541         self.out_norm = Signal(reset_less=True)
 542         self.in_z = FPNumBase(width, False)
 543         self.in_of = Overflow()
 544         self.temp_z = FPNumBase(width, False)
 545         self.temp_of = Overflow()
 546         self.out_z = FPNumBase(width, False)
 547         self.out_of = Overflow()
 548
 549     def elaborate(self, platform):
 550         m = Module()
 551         m.submodules.norm1_out_z = self.out_z
 552         m.submodules.norm1_out_overflow = self.out_of
 553         m.submodules.norm1_temp_z = self.temp_z
 554         m.submodules.norm1_temp_of = self.temp_of
 555         m.submodules.norm1_in_z = self.in_z
 556         m.submodules.norm1_in_overflow = self.in_of
 557         in_z = FPNumBase(self.width, False)
 558         in_of = Overflow()
 559         m.submodules.norm1_insel_z = in_z
 560         m.submodules.norm1_insel_overflow = in_of
 561         # select which of temp or in z/of to use
 562         with m.If(self.in_select):
 563             m.d.comb += in_z.copy(self.in_z)
 564             m.d.comb += in_of.copy(self.in_of)
 565         with m.Else():
 566             m.d.comb += in_z.copy(self.temp_z)
 567             m.d.comb += in_of.copy(self.temp_of)
 568         # initialise out from in (overridden below)
 569         m.d.comb += self.out_z.copy(in_z)
 570         m.d.comb += self.out_of.copy(in_of)
 571         # normalisation increase/decrease conditions
 572         decrease = Signal(reset_less=True)
 573         increase = Signal(reset_less=True)
 574         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 575         m.d.comb += increase.eq(in_z.exp_lt_n126)
 576         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end condition
 577         # decrease exponent
 578         with m.If(decrease):
 579             m.d.comb += [
 580                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
 581                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
 582                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
 583                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
 584                 self.out_of.round_bit.eq(0),        # reset round bit
 585                 self.out_of.m0.eq(in_of.guard),
 586             ]
 587         # increase exponent
 588         with m.If(increase):
 589             m.d.comb += [
 590                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
 591                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
 592                 self.out_of.guard.eq(in_z.m[0]),
 593                 self.out_of.m0.eq(in_z.m[1]),
 594                 self.out_of.round_bit.eq(in_of.guard),
 595                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
 596             ]
 597
 598         return m
 599
 600
 601 class FPNorm1(FPState):
 602
 603     def __init__(self, width):
 604         FPState.__init__(self, "normalise_1")
 605         self.mod = FPNorm1Mod(width)
 606         self.stb = Signal(reset_less=True)
 607         self.ack = Signal(reset=0, reset_less=True)
 608         self.out_norm = Signal(reset_less=True)
 609         self.in_accept = Signal(reset_less=True)
 610         self.temp_z = FPNumBase(width)
 611         self.temp_of = Overflow()
 612         self.out_z = FPNumBase(width)
 613         self.out_of = Overflow()
 614
 615     def setup(self, m, in_z, in_of, norm_stb):
 616         """ links module to inputs and outputs
 617         """
 618         m.submodules.normalise_1 = self.mod
 619
 620         m.d.comb += self.mod.in_z.copy(in_z)
 621         m.d.comb += self.mod.in_of.copy(in_of)
 622
 623         m.d.comb += self.mod.in_select.eq(self.in_accept)
 624         m.d.comb += self.mod.temp_z.copy(self.temp_z)
 625         m.d.comb += self.mod.temp_of.copy(self.temp_of)
 626
 627         m.d.comb += self.out_z.copy(self.mod.out_z)
 628         m.d.comb += self.out_of.copy(self.mod.out_of)
 629         m.d.comb += self.out_norm.eq(self.mod.out_norm)
 630
 631         m.d.comb += self.stb.eq(norm_stb)
 632         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
 633
 634     def action(self, m):
 635         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
 636         m.d.sync += self.of.copy(self.out_of)
 637         m.d.sync += self.z.copy(self.out_z)
 638         m.d.sync += self.temp_of.copy(self.out_of)
 639         m.d.sync += self.temp_z.copy(self.out_z)
 640         with m.If(self.out_norm):
 641             with m.If(self.in_accept):
 642                 m.d.sync += [
 643                     self.ack.eq(1),
 644                 ]
 645             with m.Else():
 646                 m.d.sync += self.ack.eq(0)
 647         with m.Else():
 648             # normalisation not required (or done).
 649             m.next = "round"
 650             m.d.sync += self.ack.eq(1)
 651
 652
 653 class FPRoundMod:
 654
 655     def __init__(self, width):
 656         self.in_roundz = Signal(reset_less=True)
 657         self.in_z = FPNumBase(width, False)
 658         self.out_z = FPNumBase(width, False)
 659
 660     def setup(self, m, in_z, out_z, in_of):
 661         """ links module to inputs and outputs
 662         """
 663         m.d.comb += self.in_z.copy(in_z)
 664         m.d.comb += out_z.copy(self.out_z)
 665         m.d.comb += self.in_roundz.eq(in_of.roundz)
 666
 667     def elaborate(self, platform):
 668         m = Module()
 669         m.d.comb += self.out_z.copy(self.in_z)
 670         with m.If(self.in_roundz):
 671             m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
 672             with m.If(self.in_z.m == self.in_z.m1s): # all 1s
 673                 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
 674         return m
 675
 676
 677 class FPRound(FPState):
 678
 679     def __init__(self, width):
 680         FPState.__init__(self, "round")
 681         self.mod = FPRoundMod(width)
 682         self.out_z = FPNumBase(width)
 683
 684     def action(self, m):
 685         m.d.sync += self.z.copy(self.out_z)
 686         m.next = "corrections"
 687
 688
 689 class FPCorrectionsMod:
 690
 691     def __init__(self, width):
 692         self.in_z = FPNumOut(width, False)
 693         self.out_z = FPNumOut(width, False)
 694
 695     def setup(self, m, in_z, out_z):
 696         """ links module to inputs and outputs
 697         """
 698         m.d.comb += self.in_z.copy(in_z)
 699         m.d.comb += out_z.copy(self.out_z)
 700
 701     def elaborate(self, platform):
 702         m = Module()
 703         m.submodules.corr_in_z = self.in_z
 704         m.submodules.corr_out_z = self.out_z
 705         m.d.comb += self.out_z.copy(self.in_z)
 706         with m.If(self.in_z.is_denormalised):
 707             m.d.comb += self.out_z.e.eq(self.in_z.N127)
 708
 709         #        with m.If(self.in_z.is_overflowed):
 710         #            m.d.comb += self.out_z.inf(self.in_z.s)
 711         #        with m.Else():
 712         #            m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 713         return m
 714
 715
 716 class FPCorrections(FPState):
 717
 718     def __init__(self, width):
 719         FPState.__init__(self, "corrections")
 720         self.mod = FPCorrectionsMod(width)
 721         self.out_z = FPNumBase(width)
 722
 723     def action(self, m):
 724         m.d.sync += self.z.copy(self.out_z)
 725         m.next = "pack"
 726
 727
 728 class FPPackMod:
 729
 730     def __init__(self, width):
 731         self.in_z = FPNumOut(width, False)
 732         self.out_z = FPNumOut(width, False)
 733
 734     def setup(self, m, in_z, out_z):
 735         """ links module to inputs and outputs
 736         """
 737         m.d.comb += self.in_z.copy(in_z)
 738         m.d.comb += out_z.v.eq(self.out_z.v)
 739
 740     def elaborate(self, platform):
 741         m = Module()
 742         m.submodules.pack_in_z = self.in_z
 743         with m.If(self.in_z.is_overflowed):
 744             m.d.comb += self.out_z.inf(self.in_z.s)
 745         with m.Else():
 746             m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 747         return m
 748
 749
 750 class FPPack(FPState):
 751
 752     def __init__(self, width):
 753         FPState.__init__(self, "pack")
 754         self.mod = FPPackMod(width)
 755         self.out_z = FPNumOut(width, False)
 756
 757     def action(self, m):
 758         m.d.sync += self.z.v.eq(self.out_z.v)
 759         m.next = "pack_put_z"
 760
 761
 762 class FPPutZ(FPState):
 763
 764     def action(self, m):
 765         self.put_z(m, self.z, self.out_z, "get_a")
 766
 767
 768 class FPADD:
 769
 770     def __init__(self, width, single_cycle=False):
 771         self.width = width
 772         self.single_cycle = single_cycle
 773
 774         self.in_a  = FPOp(width)
 775         self.in_b  = FPOp(width)
 776         self.out_z = FPOp(width)
 777
 778         self.states = []
 779
 780     def add_state(self, state):
 781         self.states.append(state)
 782         return state
 783
 784     def get_fragment(self, platform=None):
 785         """ creates the HDL code-fragment for FPAdd
 786         """
 787         m = Module()
 788
 789         # Latches
 790         z = FPNumOut(self.width, False)
 791         m.submodules.fpnum_z = z
 792
 793         w = z.m_width + 4
 794
 795         geta = self.add_state(FPGetOp("get_a", "get_b",
 796                                       self.in_a, self.width))
 797         a = geta.out_op
 798         geta.mod.setup(m, self.in_a, geta.out_op, geta.out_decode)
 799         m.submodules.get_a = geta.mod
 800
 801         getb = self.add_state(FPGetOp("get_b", "special_cases",
 802                                       self.in_b, self.width))
 803         b = getb.out_op
 804         getb.mod.setup(m, self.in_b, getb.out_op, getb.out_decode)
 805         m.submodules.get_b = getb.mod
 806
 807         sc = self.add_state(FPAddSpecialCases(self.width))
 808         sc.set_inputs({"a": a, "b": b})
 809         sc.set_outputs({"z": z})
 810         sc.mod.setup(m, a, b, sc.out_z, sc.out_do_z)
 811         m.submodules.specialcases = sc.mod
 812
 813         dn = self.add_state(FPAddDeNorm(self.width))
 814         dn.set_inputs({"a": a, "b": b})
 815         #dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 816         dn.mod.setup(m, a, b, dn.out_a, dn.out_b)
 817         m.submodules.denormalise = dn.mod
 818
 819         if self.single_cycle:
 820             alm = self.add_state(FPAddAlignSingle(self.width))
 821             alm.set_inputs({"a": a, "b": b})
 822             alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 823             alm.mod.setup(m, a, b, alm.out_a, alm.out_b)
 824         else:
 825             alm = self.add_state(FPAddAlignMulti(self.width))
 826             alm.set_inputs({"a": a, "b": b})
 827             #alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 828             alm.mod.setup(m, a, b, alm.out_a, alm.out_b, alm.exp_eq)
 829         m.submodules.align = alm.mod
 830
 831         az1 = FPNumOut(self.width, False)
 832         m.submodules.fpnum_az1 = az1
 833
 834         add0 = self.add_state(FPAddStage0(self.width))
 835         add0.set_inputs({"a": alm.out_a, "b": alm.out_b})
 836         add0.set_outputs({"z": az1})
 837         add0.setup(m, alm.out_a, alm.out_b, az1)
 838
 839         add1 = self.add_state(FPAddStage1(self.width))
 840         #add1.set_outputs({"z": az})  # XXX Z as output
 841         add1.mod.setup(m, add0.out_tot, az1, None, add1.out_of)
 842         m.submodules.add1 = add1.mod
 843         m.d.sync += add1.norm_stb.eq(0) # sets to zero when not in add1 state
 844
 845         az = add1.out_z
 846
 847         n1 = self.add_state(FPNorm1(self.width))
 848         n1.set_inputs({"z": az, "of": add1.out_of})  # XXX Z as output
 849         n1.set_outputs({"z": az})  # XXX Z as output
 850         n1.setup(m, az, add1.out_of, add1.norm_stb)
 851
 852         rnz = FPNumOut(self.width, False)
 853         m.submodules.fpnum_rnz = rnz
 854
 855         rn = self.add_state(FPRound(self.width))
 856         rn.set_inputs({"of": n1.out_of})
 857         rn.set_outputs({"z": rnz})
 858         rn.mod.setup(m, n1.out_z, rn.out_z, add1.out_of)
 859         m.submodules.roundz = rn.mod
 860
 861         cor = self.add_state(FPCorrections(self.width))
 862         cor.set_inputs({"z": rnz})  # XXX Z as output
 863         cor.mod.setup(m, rnz, cor.out_z)
 864         m.submodules.corrections = cor.mod
 865
 866         pa = self.add_state(FPPack(self.width))
 867         pa.set_inputs({"z": cor.out_z})  # XXX Z as output
 868         pa.mod.setup(m, cor.out_z, pa.out_z)
 869         m.submodules.pack = pa.mod
 870
 871         ppz = self.add_state(FPPutZ("pack_put_z"))
 872         ppz.set_inputs({"z": pa.out_z})
 873         ppz.set_outputs({"out_z": self.out_z})
 874
 875         pz = self.add_state(FPPutZ("put_z"))
 876         pz.set_inputs({"z": z})
 877         pz.set_outputs({"out_z": self.out_z})
 878
 879         with m.FSM() as fsm:
 880
 881             for state in self.states:
 882                 with m.State(state.state_from):
 883                     state.action(m)
 884
 885         return m
 886
 887
 888 if __name__ == "__main__":
 889     alu = FPADD(width=32)
 890     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 891
 892
 893     # works... but don't use, just do "python fname.py convert -t v"
 894     #print (verilog.convert(alu, ports=[
 895     #                        ports=alu.in_a.ports() + \
 896     #                              alu.in_b.ports() + \
 897     #                              alu.out_z.ports())