src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8
   9 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  10 from fpbase import MultiShiftRMerge
  11 #from fpbase import FPNumShiftMultiRight
  12
  13 class FPState(FPBase):
  14     def __init__(self, state_from):
  15         self.state_from = state_from
  16
  17     def set_inputs(self, inputs):
  18         self.inputs = inputs
  19         for k,v in inputs.items():
  20             setattr(self, k, v)
  21
  22     def set_outputs(self, outputs):
  23         self.outputs = outputs
  24         for k,v in outputs.items():
  25             setattr(self, k, v)
  26
  27
  28 class FPGetOpMod:
  29     def __init__(self, width):
  30         self.in_op = FPOp(width)
  31         self.out_op = FPNumIn(self.in_op, width)
  32         self.out_decode = Signal(reset_less=True)
  33
  34     def elaborate(self, platform):
  35         m = Module()
  36         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
  37         #m.submodules.get_op_in = self.in_op
  38         m.submodules.get_op_out = self.out_op
  39         with m.If(self.out_decode):
  40             m.d.comb += [
  41                 self.out_op.decode(self.in_op.v),
  42             ]
  43         return m
  44
  45
  46 class FPGetOp(FPState):
  47     """ gets operand
  48     """
  49
  50     def __init__(self, in_state, out_state, in_op, width):
  51         FPState.__init__(self, in_state)
  52         self.out_state = out_state
  53         self.mod = FPGetOpMod(width)
  54         self.in_op = in_op
  55         self.out_op = FPNumIn(in_op, width)
  56         self.out_decode = Signal(reset_less=True)
  57
  58     def setup(self, m, in_op):
  59         """ links module to inputs and outputs
  60         """
  61         setattr(m.submodules, self.state_from, self.mod)
  62         m.d.comb += self.mod.in_op.copy(in_op)
  63         m.d.comb += self.out_op.v.eq(self.mod.out_op.v)
  64         m.d.comb += self.out_decode.eq(self.mod.out_decode)
  65
  66     def action(self, m):
  67         with m.If(self.out_decode):
  68             m.next = self.out_state
  69             m.d.sync += [
  70                 self.in_op.ack.eq(0),
  71                 self.out_op.copy(self.mod.out_op)
  72             ]
  73         with m.Else():
  74             m.d.sync += self.in_op.ack.eq(1)
  75
  76
  77 class FPAddSpecialCasesMod:
  78     """ special cases: NaNs, infs, zeros, denormalised
  79         NOTE: some of these are unique to add.  see "Special Operations"
  80         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  81     """
  82
  83     def __init__(self, width):
  84         self.in_a = FPNumBase(width)
  85         self.in_b = FPNumBase(width)
  86         self.out_z = FPNumOut(width, False)
  87         self.out_do_z = Signal(reset_less=True)
  88
  89     def elaborate(self, platform):
  90         m = Module()
  91
  92         m.submodules.sc_in_a = self.in_a
  93         m.submodules.sc_in_b = self.in_b
  94         m.submodules.sc_out_z = self.out_z
  95
  96         s_nomatch = Signal()
  97         m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
  98
  99         m_match = Signal()
 100         m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
 101
 102         # if a is NaN or b is NaN return NaN
 103         with m.If(self.in_a.is_nan | self.in_b.is_nan):
 104             m.d.comb += self.out_do_z.eq(1)
 105             m.d.comb += self.out_z.nan(0)
 106
 107         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 108         # under review
 109
 110         ## if a is zero and b is NaN return -b
 111         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 112         #    m.d.comb += self.out_do_z.eq(1)
 113         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 114
 115         ## if b is zero and a is NaN return -a
 116         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 117         #    m.d.comb += self.out_do_z.eq(1)
 118         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 119
 120         ## if a is -zero and b is NaN return -b
 121         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 122         #    m.d.comb += self.out_do_z.eq(1)
 123         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 124
 125         ## if b is -zero and a is NaN return -a
 126         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 127         #    m.d.comb += self.out_do_z.eq(1)
 128         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 129
 130         # if a is inf return inf (or NaN)
 131         with m.Elif(self.in_a.is_inf):
 132             m.d.comb += self.out_do_z.eq(1)
 133             m.d.comb += self.out_z.inf(self.in_a.s)
 134             # if a is inf and signs don't match return NaN
 135             with m.If(self.in_b.exp_128 & s_nomatch):
 136                 m.d.comb += self.out_z.nan(0)
 137
 138         # if b is inf return inf
 139         with m.Elif(self.in_b.is_inf):
 140             m.d.comb += self.out_do_z.eq(1)
 141             m.d.comb += self.out_z.inf(self.in_b.s)
 142
 143         # if a is zero and b zero return signed-a/b
 144         with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
 145             m.d.comb += self.out_do_z.eq(1)
 146             m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
 147                                           self.in_b.e,
 148                                           self.in_b.m[3:-1])
 149
 150         # if a is zero return b
 151         with m.Elif(self.in_a.is_zero):
 152             m.d.comb += self.out_do_z.eq(1)
 153             m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
 154                                       self.in_b.m[3:-1])
 155
 156         # if b is zero return a
 157         with m.Elif(self.in_b.is_zero):
 158             m.d.comb += self.out_do_z.eq(1)
 159             m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
 160                                       self.in_a.m[3:-1])
 161
 162         # if a equal to -b return zero (+ve zero)
 163         with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
 164             m.d.comb += self.out_do_z.eq(1)
 165             m.d.comb += self.out_z.zero(0)
 166
 167         # Denormalised Number checks
 168         with m.Else():
 169             m.d.comb += self.out_do_z.eq(0)
 170
 171         return m
 172
 173
 174 class FPID:
 175     def __init__(self, id_wid):
 176         self.id_wid = id_wid
 177         if self.id_wid:
 178             self.in_mid = Signal(width, reset_less)
 179             self.out_mid = Signal(width, reset_less)
 180         else:
 181             self.in_mid = None
 182             self.out_mid = None
 183
 184     def idsync(self, m):
 185         if self.id_wid:
 186             m.d.sync += self.out_mid.eq(self.in_mid)
 187
 188
 189 class FPAddSpecialCases(FPState, FPID):
 190     """ special cases: NaNs, infs, zeros, denormalised
 191         NOTE: some of these are unique to add.  see "Special Operations"
 192         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 193     """
 194
 195     def __init__(self, width, id_wid):
 196         FPState.__init__(self, "special_cases")
 197         FPID.__init__(self, id_wid)
 198         self.mod = FPAddSpecialCasesMod(width)
 199         self.out_z = FPNumOut(width, False)
 200         self.out_do_z = Signal(reset_less=True)
 201
 202     def setup(self, m, in_a, in_b, in_mid):
 203         """ links module to inputs and outputs
 204         """
 205         m.submodules.specialcases = self.mod
 206         m.d.comb += self.mod.in_a.copy(in_a)
 207         m.d.comb += self.mod.in_b.copy(in_b)
 208         #m.d.comb += self.out_z.v.eq(self.mod.out_z.v)
 209         m.d.comb += self.out_do_z.eq(self.mod.out_do_z)
 210         if self.in_mid:
 211             m.d.comb += self.in_mid.eq(in_mid)
 212
 213     def action(self, m):
 214         self.idsync(m)
 215         with m.If(self.out_do_z):
 216             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 217             m.next = "put_z"
 218         with m.Else():
 219             m.next = "denormalise"
 220
 221
 222 class FPAddDeNormMod(FPState):
 223
 224     def __init__(self, width):
 225         self.in_a = FPNumBase(width)
 226         self.in_b = FPNumBase(width)
 227         self.out_a = FPNumBase(width)
 228         self.out_b = FPNumBase(width)
 229
 230     def elaborate(self, platform):
 231         m = Module()
 232         m.submodules.denorm_in_a = self.in_a
 233         m.submodules.denorm_in_b = self.in_b
 234         m.submodules.denorm_out_a = self.out_a
 235         m.submodules.denorm_out_b = self.out_b
 236         # hmmm, don't like repeating identical code
 237         m.d.comb += self.out_a.copy(self.in_a)
 238         with m.If(self.in_a.exp_n127):
 239             m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
 240         with m.Else():
 241             m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
 242
 243         m.d.comb += self.out_b.copy(self.in_b)
 244         with m.If(self.in_b.exp_n127):
 245             m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
 246         with m.Else():
 247             m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
 248
 249         return m
 250
 251
 252 class FPAddDeNorm(FPState, FPID):
 253
 254     def __init__(self, width, id_wid):
 255         FPState.__init__(self, "denormalise")
 256         FPID.__init__(self, id_wid)
 257         self.mod = FPAddDeNormMod(width)
 258         self.out_a = FPNumBase(width)
 259         self.out_b = FPNumBase(width)
 260
 261     def setup(self, m, in_a, in_b, in_mid):
 262         """ links module to inputs and outputs
 263         """
 264         m.submodules.denormalise = self.mod
 265         m.d.comb += self.mod.in_a.copy(in_a)
 266         m.d.comb += self.mod.in_b.copy(in_b)
 267         if self.in_mid:
 268             m.d.comb += self.in_mid.eq(in_mid)
 269
 270     def action(self, m):
 271         self.idsync(m)
 272         # Denormalised Number checks
 273         m.next = "align"
 274         m.d.sync += self.out_a.copy(self.mod.out_a)
 275         m.d.sync += self.out_b.copy(self.mod.out_b)
 276
 277
 278 class FPAddAlignMultiMod(FPState):
 279
 280     def __init__(self, width):
 281         self.in_a = FPNumBase(width)
 282         self.in_b = FPNumBase(width)
 283         self.out_a = FPNumIn(None, width)
 284         self.out_b = FPNumIn(None, width)
 285         self.exp_eq = Signal(reset_less=True)
 286
 287     def elaborate(self, platform):
 288         # This one however (single-cycle) will do the shift
 289         # in one go.
 290
 291         m = Module()
 292
 293         m.submodules.align_in_a = self.in_a
 294         m.submodules.align_in_b = self.in_b
 295         m.submodules.align_out_a = self.out_a
 296         m.submodules.align_out_b = self.out_b
 297
 298         # NOTE: this does *not* do single-cycle multi-shifting,
 299         #       it *STAYS* in the align state until exponents match
 300
 301         # exponent of a greater than b: shift b down
 302         m.d.comb += self.exp_eq.eq(0)
 303         m.d.comb += self.out_a.copy(self.in_a)
 304         m.d.comb += self.out_b.copy(self.in_b)
 305         agtb = Signal(reset_less=True)
 306         altb = Signal(reset_less=True)
 307         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 308         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 309         with m.If(agtb):
 310             m.d.comb += self.out_b.shift_down(self.in_b)
 311         # exponent of b greater than a: shift a down
 312         with m.Elif(altb):
 313             m.d.comb += self.out_a.shift_down(self.in_a)
 314         # exponents equal: move to next stage.
 315         with m.Else():
 316             m.d.comb += self.exp_eq.eq(1)
 317         return m
 318
 319
 320 class FPAddAlignMulti(FPState):
 321
 322     def __init__(self, width):
 323         FPState.__init__(self, "align")
 324         self.mod = FPAddAlignMultiMod(width)
 325         self.out_a = FPNumIn(None, width)
 326         self.out_b = FPNumIn(None, width)
 327         self.exp_eq = Signal(reset_less=True)
 328
 329     def setup(self, m, in_a, in_b):
 330         """ links module to inputs and outputs
 331         """
 332         m.submodules.align = self.mod
 333         m.d.comb += self.mod.in_a.copy(in_a)
 334         m.d.comb += self.mod.in_b.copy(in_b)
 335         #m.d.comb += self.out_a.copy(self.mod.out_a)
 336         #m.d.comb += self.out_b.copy(self.mod.out_b)
 337         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 338
 339     def action(self, m):
 340         m.d.sync += self.out_a.copy(self.mod.out_a)
 341         m.d.sync += self.out_b.copy(self.mod.out_b)
 342         with m.If(self.exp_eq):
 343             m.next = "add_0"
 344
 345
 346 class FPAddAlignSingleMod:
 347
 348     def __init__(self, width):
 349         self.width = width
 350         self.in_a = FPNumBase(width)
 351         self.in_b = FPNumBase(width)
 352         self.out_a = FPNumIn(None, width)
 353         self.out_b = FPNumIn(None, width)
 354
 355     def elaborate(self, platform):
 356         """ Aligns A against B or B against A, depending on which has the
 357             greater exponent.  This is done in a *single* cycle using
 358             variable-width bit-shift
 359
 360             the shifter used here is quite expensive in terms of gates.
 361             Mux A or B in (and out) into temporaries, as only one of them
 362             needs to be aligned against the other
 363         """
 364         m = Module()
 365
 366         m.submodules.align_in_a = self.in_a
 367         m.submodules.align_in_b = self.in_b
 368         m.submodules.align_out_a = self.out_a
 369         m.submodules.align_out_b = self.out_b
 370
 371         # temporary (muxed) input and output to be shifted
 372         t_inp = FPNumBase(self.width)
 373         t_out = FPNumIn(None, self.width)
 374         espec = (len(self.in_a.e), True)
 375         msr = MultiShiftRMerge(self.in_a.m_width, espec)
 376         m.submodules.align_t_in = t_inp
 377         m.submodules.align_t_out = t_out
 378         m.submodules.multishift_r = msr
 379
 380         ediff = Signal(espec, reset_less=True)
 381         ediffr = Signal(espec, reset_less=True)
 382         tdiff = Signal(espec, reset_less=True)
 383         elz = Signal(reset_less=True)
 384         egz = Signal(reset_less=True)
 385
 386         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 387         m.d.comb += msr.inp.eq(t_inp.m)
 388         m.d.comb += msr.diff.eq(tdiff)
 389         m.d.comb += t_out.m.eq(msr.m)
 390         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 391         m.d.comb += t_out.s.eq(t_inp.s)
 392
 393         m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
 394         m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
 395         m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
 396         m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
 397
 398         # default: A-exp == B-exp, A and B untouched (fall through)
 399         m.d.comb += self.out_a.copy(self.in_a)
 400         m.d.comb += self.out_b.copy(self.in_b)
 401         # only one shifter (muxed)
 402         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 403         # exponent of a greater than b: shift b down
 404         with m.If(egz):
 405             m.d.comb += [t_inp.copy(self.in_b),
 406                          tdiff.eq(ediff),
 407                          self.out_b.copy(t_out),
 408                          self.out_b.s.eq(self.in_b.s), # whoops forgot sign
 409                         ]
 410         # exponent of b greater than a: shift a down
 411         with m.Elif(elz):
 412             m.d.comb += [t_inp.copy(self.in_a),
 413                          tdiff.eq(ediffr),
 414                          self.out_a.copy(t_out),
 415                          self.out_a.s.eq(self.in_a.s), # whoops forgot sign
 416                         ]
 417         return m
 418
 419
 420 class FPAddAlignSingle(FPState):
 421
 422     def __init__(self, width):
 423         FPState.__init__(self, "align")
 424         self.mod = FPAddAlignSingleMod(width)
 425         self.out_a = FPNumIn(None, width)
 426         self.out_b = FPNumIn(None, width)
 427
 428     def setup(self, m, in_a, in_b):
 429         """ links module to inputs and outputs
 430         """
 431         m.submodules.align = self.mod
 432         m.d.comb += self.mod.in_a.copy(in_a)
 433         m.d.comb += self.mod.in_b.copy(in_b)
 434
 435     def action(self, m):
 436         # NOTE: could be done as comb
 437         m.d.sync += self.out_a.copy(self.mod.out_a)
 438         m.d.sync += self.out_b.copy(self.mod.out_b)
 439         m.next = "add_0"
 440
 441
 442 class FPAddStage0Mod:
 443
 444     def __init__(self, width):
 445         self.in_a = FPNumBase(width)
 446         self.in_b = FPNumBase(width)
 447         self.in_z = FPNumBase(width, False)
 448         self.out_z = FPNumBase(width, False)
 449         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 450
 451     def elaborate(self, platform):
 452         m = Module()
 453         m.submodules.add0_in_a = self.in_a
 454         m.submodules.add0_in_b = self.in_b
 455         m.submodules.add0_out_z = self.out_z
 456
 457         m.d.comb += self.out_z.e.eq(self.in_a.e)
 458
 459         # store intermediate tests (and zero-extended mantissas)
 460         seq = Signal(reset_less=True)
 461         mge = Signal(reset_less=True)
 462         am0 = Signal(len(self.in_a.m)+1, reset_less=True)
 463         bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
 464         m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
 465                      mge.eq(self.in_a.m >= self.in_b.m),
 466                      am0.eq(Cat(self.in_a.m, 0)),
 467                      bm0.eq(Cat(self.in_b.m, 0))
 468                     ]
 469         # same-sign (both negative or both positive) add mantissas
 470         with m.If(seq):
 471             m.d.comb += [
 472                 self.out_tot.eq(am0 + bm0),
 473                 self.out_z.s.eq(self.in_a.s)
 474             ]
 475         # a mantissa greater than b, use a
 476         with m.Elif(mge):
 477             m.d.comb += [
 478                 self.out_tot.eq(am0 - bm0),
 479                 self.out_z.s.eq(self.in_a.s)
 480             ]
 481         # b mantissa greater than a, use b
 482         with m.Else():
 483             m.d.comb += [
 484                 self.out_tot.eq(bm0 - am0),
 485                 self.out_z.s.eq(self.in_b.s)
 486         ]
 487         return m
 488
 489
 490 class FPAddStage0(FPState):
 491     """ First stage of add.  covers same-sign (add) and subtract
 492         special-casing when mantissas are greater or equal, to
 493         give greatest accuracy.
 494     """
 495
 496     def __init__(self, width):
 497         FPState.__init__(self, "add_0")
 498         self.mod = FPAddStage0Mod(width)
 499         self.out_z = FPNumBase(width, False)
 500         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 501
 502     def setup(self, m, in_a, in_b):
 503         """ links module to inputs and outputs
 504         """
 505         m.submodules.add0 = self.mod
 506
 507         m.d.comb += self.mod.in_a.copy(in_a)
 508         m.d.comb += self.mod.in_b.copy(in_b)
 509
 510     def action(self, m):
 511         m.next = "add_1"
 512         # NOTE: these could be done as combinatorial (merge add0+add1)
 513         m.d.sync += self.out_z.copy(self.mod.out_z)
 514         m.d.sync += self.out_tot.eq(self.mod.out_tot)
 515
 516
 517 class FPAddStage1Mod(FPState):
 518     """ Second stage of add: preparation for normalisation.
 519         detects when tot sum is too big (tot[27] is kinda a carry bit)
 520     """
 521
 522     def __init__(self, width):
 523         self.out_norm = Signal(reset_less=True)
 524         self.in_z = FPNumBase(width, False)
 525         self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
 526         self.out_z = FPNumBase(width, False)
 527         self.out_of = Overflow()
 528
 529     def elaborate(self, platform):
 530         m = Module()
 531         #m.submodules.norm1_in_overflow = self.in_of
 532         #m.submodules.norm1_out_overflow = self.out_of
 533         #m.submodules.norm1_in_z = self.in_z
 534         #m.submodules.norm1_out_z = self.out_z
 535         m.d.comb += self.out_z.copy(self.in_z)
 536         # tot[27] gets set when the sum overflows. shift result down
 537         with m.If(self.in_tot[-1]):
 538             m.d.comb += [
 539                 self.out_z.m.eq(self.in_tot[4:]),
 540                 self.out_of.m0.eq(self.in_tot[4]),
 541                 self.out_of.guard.eq(self.in_tot[3]),
 542                 self.out_of.round_bit.eq(self.in_tot[2]),
 543                 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
 544                 self.out_z.e.eq(self.in_z.e + 1)
 545         ]
 546         # tot[27] zero case
 547         with m.Else():
 548             m.d.comb += [
 549                 self.out_z.m.eq(self.in_tot[3:]),
 550                 self.out_of.m0.eq(self.in_tot[3]),
 551                 self.out_of.guard.eq(self.in_tot[2]),
 552                 self.out_of.round_bit.eq(self.in_tot[1]),
 553                 self.out_of.sticky.eq(self.in_tot[0])
 554         ]
 555         return m
 556
 557
 558 class FPAddStage1(FPState):
 559
 560     def __init__(self, width):
 561         FPState.__init__(self, "add_1")
 562         self.mod = FPAddStage1Mod(width)
 563         self.out_z = FPNumBase(width, False)
 564         self.out_of = Overflow()
 565         self.norm_stb = Signal()
 566
 567     def setup(self, m, in_tot, in_z):
 568         """ links module to inputs and outputs
 569         """
 570         m.submodules.add1 = self.mod
 571
 572         m.d.comb += self.mod.in_z.copy(in_z)
 573         m.d.comb += self.mod.in_tot.eq(in_tot)
 574
 575         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 576
 577     def action(self, m):
 578         m.submodules.add1_out_overflow = self.out_of
 579         m.d.sync += self.out_of.copy(self.mod.out_of)
 580         m.d.sync += self.out_z.copy(self.mod.out_z)
 581         m.d.sync += self.norm_stb.eq(1)
 582         m.next = "normalise_1"
 583
 584
 585 class FPNorm1ModSingle:
 586
 587     def __init__(self, width):
 588         self.width = width
 589         self.in_select = Signal(reset_less=True)
 590         self.out_norm = Signal(reset_less=True)
 591         self.in_z = FPNumBase(width, False)
 592         self.in_of = Overflow()
 593         self.temp_z = FPNumBase(width, False)
 594         self.temp_of = Overflow()
 595         self.out_z = FPNumBase(width, False)
 596         self.out_of = Overflow()
 597
 598     def elaborate(self, platform):
 599         m = Module()
 600
 601         mwid = self.out_z.m_width+2
 602         pe = PriorityEncoder(mwid)
 603         m.submodules.norm_pe = pe
 604
 605         m.submodules.norm1_out_z = self.out_z
 606         m.submodules.norm1_out_overflow = self.out_of
 607         m.submodules.norm1_temp_z = self.temp_z
 608         m.submodules.norm1_temp_of = self.temp_of
 609         m.submodules.norm1_in_z = self.in_z
 610         m.submodules.norm1_in_overflow = self.in_of
 611
 612         in_z = FPNumBase(self.width, False)
 613         in_of = Overflow()
 614         m.submodules.norm1_insel_z = in_z
 615         m.submodules.norm1_insel_overflow = in_of
 616
 617         espec = (len(in_z.e), True)
 618         ediff_n126 = Signal(espec, reset_less=True)
 619         msr = MultiShiftRMerge(mwid, espec)
 620         m.submodules.multishift_r = msr
 621
 622         # select which of temp or in z/of to use
 623         with m.If(self.in_select):
 624             m.d.comb += in_z.copy(self.in_z)
 625             m.d.comb += in_of.copy(self.in_of)
 626         with m.Else():
 627             m.d.comb += in_z.copy(self.temp_z)
 628             m.d.comb += in_of.copy(self.temp_of)
 629         # initialise out from in (overridden below)
 630         m.d.comb += self.out_z.copy(in_z)
 631         m.d.comb += self.out_of.copy(in_of)
 632         # normalisation increase/decrease conditions
 633         decrease = Signal(reset_less=True)
 634         increase = Signal(reset_less=True)
 635         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 636         m.d.comb += increase.eq(in_z.exp_lt_n126)
 637         m.d.comb += self.out_norm.eq(0) # loop-end condition
 638         # decrease exponent
 639         with m.If(decrease):
 640             # *sigh* not entirely obvious: count leading zeros (clz)
 641             # with a PriorityEncoder: to find from the MSB
 642             # we reverse the order of the bits.
 643             temp_m = Signal(mwid, reset_less=True)
 644             temp_s = Signal(mwid+1, reset_less=True)
 645             clz = Signal((len(in_z.e), True), reset_less=True)
 646             # make sure that the amount to decrease by does NOT
 647             # go below the minimum non-INF/NaN exponent
 648             limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
 649                          in_z.exp_sub_n126)
 650             m.d.comb += [
 651                 # cat round and guard bits back into the mantissa
 652                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
 653                 pe.i.eq(temp_m[::-1]),          # inverted
 654                 clz.eq(limclz),                 # count zeros from MSB down
 655                 temp_s.eq(temp_m << clz),       # shift mantissa UP
 656                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
 657                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
 658                 self.out_of.m0.eq(temp_s[2]),   # copy of mantissa[0]
 659                 # overflow in bits 0..1: got shifted too (leave sticky)
 660                 self.out_of.guard.eq(temp_s[1]),     # guard
 661                 self.out_of.round_bit.eq(temp_s[0]), # round
 662             ]
 663         # increase exponent
 664         with m.Elif(increase):
 665             temp_m = Signal(mwid+1, reset_less=True)
 666             m.d.comb += [
 667                 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
 668                               in_z.m)),
 669                 ediff_n126.eq(in_z.N126 - in_z.e),
 670                 # connect multi-shifter to inp/out mantissa (and ediff)
 671                 msr.inp.eq(temp_m),
 672                 msr.diff.eq(ediff_n126),
 673                 self.out_z.m.eq(msr.m[3:]),
 674                 self.out_of.m0.eq(temp_s[3]),   # copy of mantissa[0]
 675                 # overflow in bits 0..1: got shifted too (leave sticky)
 676                 self.out_of.guard.eq(temp_s[2]),     # guard
 677                 self.out_of.round_bit.eq(temp_s[1]), # round
 678                 self.out_of.sticky.eq(temp_s[0]), # sticky
 679                 self.out_z.e.eq(in_z.e + ediff_n126),
 680             ]
 681
 682         return m
 683
 684
 685 class FPNorm1ModMulti:
 686
 687     def __init__(self, width, single_cycle=True):
 688         self.width = width
 689         self.in_select = Signal(reset_less=True)
 690         self.out_norm = Signal(reset_less=True)
 691         self.in_z = FPNumBase(width, False)
 692         self.in_of = Overflow()
 693         self.temp_z = FPNumBase(width, False)
 694         self.temp_of = Overflow()
 695         self.out_z = FPNumBase(width, False)
 696         self.out_of = Overflow()
 697
 698     def elaborate(self, platform):
 699         m = Module()
 700
 701         m.submodules.norm1_out_z = self.out_z
 702         m.submodules.norm1_out_overflow = self.out_of
 703         m.submodules.norm1_temp_z = self.temp_z
 704         m.submodules.norm1_temp_of = self.temp_of
 705         m.submodules.norm1_in_z = self.in_z
 706         m.submodules.norm1_in_overflow = self.in_of
 707
 708         in_z = FPNumBase(self.width, False)
 709         in_of = Overflow()
 710         m.submodules.norm1_insel_z = in_z
 711         m.submodules.norm1_insel_overflow = in_of
 712
 713         # select which of temp or in z/of to use
 714         with m.If(self.in_select):
 715             m.d.comb += in_z.copy(self.in_z)
 716             m.d.comb += in_of.copy(self.in_of)
 717         with m.Else():
 718             m.d.comb += in_z.copy(self.temp_z)
 719             m.d.comb += in_of.copy(self.temp_of)
 720         # initialise out from in (overridden below)
 721         m.d.comb += self.out_z.copy(in_z)
 722         m.d.comb += self.out_of.copy(in_of)
 723         # normalisation increase/decrease conditions
 724         decrease = Signal(reset_less=True)
 725         increase = Signal(reset_less=True)
 726         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 727         m.d.comb += increase.eq(in_z.exp_lt_n126)
 728         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
 729         # decrease exponent
 730         with m.If(decrease):
 731             m.d.comb += [
 732                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
 733                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
 734                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
 735                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
 736                 self.out_of.round_bit.eq(0),        # reset round bit
 737                 self.out_of.m0.eq(in_of.guard),
 738             ]
 739         # increase exponent
 740         with m.Elif(increase):
 741             m.d.comb += [
 742                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
 743                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
 744                 self.out_of.guard.eq(in_z.m[0]),
 745                 self.out_of.m0.eq(in_z.m[1]),
 746                 self.out_of.round_bit.eq(in_of.guard),
 747                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
 748             ]
 749
 750         return m
 751
 752
 753 class FPNorm1(FPState):
 754
 755     def __init__(self, width, single_cycle=True):
 756         FPState.__init__(self, "normalise_1")
 757         if single_cycle:
 758             self.mod = FPNorm1ModSingle(width)
 759         else:
 760             self.mod = FPNorm1ModMulti(width)
 761         self.stb = Signal(reset_less=True)
 762         self.ack = Signal(reset=0, reset_less=True)
 763         self.out_norm = Signal(reset_less=True)
 764         self.in_accept = Signal(reset_less=True)
 765         self.temp_z = FPNumBase(width)
 766         self.temp_of = Overflow()
 767         self.out_z = FPNumBase(width)
 768         self.out_roundz = Signal(reset_less=True)
 769
 770     def setup(self, m, in_z, in_of, norm_stb):
 771         """ links module to inputs and outputs
 772         """
 773         m.submodules.normalise_1 = self.mod
 774
 775         m.d.comb += self.mod.in_z.copy(in_z)
 776         m.d.comb += self.mod.in_of.copy(in_of)
 777
 778         m.d.comb += self.mod.in_select.eq(self.in_accept)
 779         m.d.comb += self.mod.temp_z.copy(self.temp_z)
 780         m.d.comb += self.mod.temp_of.copy(self.temp_of)
 781
 782         m.d.comb += self.out_z.copy(self.mod.out_z)
 783         m.d.comb += self.out_norm.eq(self.mod.out_norm)
 784
 785         m.d.comb += self.stb.eq(norm_stb)
 786         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
 787
 788     def action(self, m):
 789
 790         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
 791         m.d.sync += self.temp_of.copy(self.mod.out_of)
 792         m.d.sync += self.temp_z.copy(self.out_z)
 793         with m.If(self.out_norm):
 794             with m.If(self.in_accept):
 795                 m.d.sync += [
 796                     self.ack.eq(1),
 797                 ]
 798             with m.Else():
 799                 m.d.sync += self.ack.eq(0)
 800         with m.Else():
 801             # normalisation not required (or done).
 802             m.next = "round"
 803             m.d.sync += self.ack.eq(1)
 804             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
 805
 806
 807 class FPRoundMod:
 808
 809     def __init__(self, width):
 810         self.in_roundz = Signal(reset_less=True)
 811         self.in_z = FPNumBase(width, False)
 812         self.out_z = FPNumBase(width, False)
 813
 814     def elaborate(self, platform):
 815         m = Module()
 816         m.d.comb += self.out_z.copy(self.in_z)
 817         with m.If(self.in_roundz):
 818             m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
 819             with m.If(self.in_z.m == self.in_z.m1s): # all 1s
 820                 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
 821         return m
 822
 823
 824 class FPRound(FPState):
 825
 826     def __init__(self, width):
 827         FPState.__init__(self, "round")
 828         self.mod = FPRoundMod(width)
 829         self.out_z = FPNumBase(width)
 830
 831     def setup(self, m, in_z, roundz):
 832         """ links module to inputs and outputs
 833         """
 834         m.submodules.roundz = self.mod
 835
 836         m.d.comb += self.mod.in_z.copy(in_z)
 837         m.d.comb += self.mod.in_roundz.eq(roundz)
 838
 839     def action(self, m):
 840         m.d.sync += self.out_z.copy(self.mod.out_z)
 841         m.next = "corrections"
 842
 843
 844 class FPCorrectionsMod:
 845
 846     def __init__(self, width):
 847         self.in_z = FPNumOut(width, False)
 848         self.out_z = FPNumOut(width, False)
 849
 850     def elaborate(self, platform):
 851         m = Module()
 852         m.submodules.corr_in_z = self.in_z
 853         m.submodules.corr_out_z = self.out_z
 854         m.d.comb += self.out_z.copy(self.in_z)
 855         with m.If(self.in_z.is_denormalised):
 856             m.d.comb += self.out_z.e.eq(self.in_z.N127)
 857         return m
 858
 859
 860 class FPCorrections(FPState):
 861
 862     def __init__(self, width):
 863         FPState.__init__(self, "corrections")
 864         self.mod = FPCorrectionsMod(width)
 865         self.out_z = FPNumBase(width)
 866
 867     def setup(self, m, in_z):
 868         """ links module to inputs and outputs
 869         """
 870         m.submodules.corrections = self.mod
 871         m.d.comb += self.mod.in_z.copy(in_z)
 872
 873     def action(self, m):
 874         m.d.sync += self.out_z.copy(self.mod.out_z)
 875         m.next = "pack"
 876
 877
 878 class FPPackMod:
 879
 880     def __init__(self, width):
 881         self.in_z = FPNumOut(width, False)
 882         self.out_z = FPNumOut(width, False)
 883
 884     def elaborate(self, platform):
 885         m = Module()
 886         m.submodules.pack_in_z = self.in_z
 887         with m.If(self.in_z.is_overflowed):
 888             m.d.comb += self.out_z.inf(self.in_z.s)
 889         with m.Else():
 890             m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 891         return m
 892
 893
 894 class FPPack(FPState):
 895
 896     def __init__(self, width):
 897         FPState.__init__(self, "pack")
 898         self.mod = FPPackMod(width)
 899         self.out_z = FPNumOut(width, False)
 900
 901     def setup(self, m, in_z):
 902         """ links module to inputs and outputs
 903         """
 904         m.submodules.pack = self.mod
 905         m.d.comb += self.mod.in_z.copy(in_z)
 906
 907     def action(self, m):
 908         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
 909         m.next = "pack_put_z"
 910
 911
 912 class FPPutZ(FPState):
 913
 914     def __init__(self, state, in_z, out_z):
 915         FPState.__init__(self, state)
 916         self.in_z = in_z
 917         self.out_z = out_z
 918
 919     def action(self, m):
 920         m.d.sync += [
 921           self.out_z.v.eq(self.in_z.v)
 922         ]
 923         with m.If(self.out_z.stb & self.out_z.ack):
 924             m.d.sync += self.out_z.stb.eq(0)
 925             m.next = "get_a"
 926         with m.Else():
 927             m.d.sync += self.out_z.stb.eq(1)
 928
 929
 930 class FPADD(FPID):
 931
 932     def __init__(self, width, id_wid=None, single_cycle=False):
 933         """ IEEE754 FP Add
 934
 935             * width: bit-width of IEEE754.  supported: 16, 32, 64
 936             * id_wid: an identifier that is sync-connected to the input
 937             * single_cycle: True indicates each stage to complete in 1 clock
 938         """
 939         FPID.__init__(self, id_wid)
 940         self.width = width
 941         self.single_cycle = single_cycle
 942
 943         self.in_a  = FPOp(width)
 944         self.in_b  = FPOp(width)
 945         self.out_z = FPOp(width)
 946
 947         self.states = []
 948
 949     def add_state(self, state):
 950         self.states.append(state)
 951         return state
 952
 953     def get_fragment(self, platform=None):
 954         """ creates the HDL code-fragment for FPAdd
 955         """
 956         m = Module()
 957         m.submodules.in_a = self.in_a
 958         m.submodules.in_b = self.in_b
 959         m.submodules.out_z = self.out_z
 960
 961         geta = self.add_state(FPGetOp("get_a", "get_b",
 962                                       self.in_a, self.width))
 963         geta.setup(m, self.in_a)
 964         a = geta.out_op
 965
 966         getb = self.add_state(FPGetOp("get_b", "special_cases",
 967                                       self.in_b, self.width))
 968         getb.setup(m, self.in_b)
 969         b = getb.out_op
 970
 971         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
 972         sc.setup(m, a, b, self.in_mid)
 973
 974         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
 975         dn.setup(m, a, b, sc.in_mid)
 976
 977         if self.single_cycle:
 978             alm = self.add_state(FPAddAlignSingle(self.width))
 979             alm.setup(m, dn.out_a, dn.out_b)
 980         else:
 981             alm = self.add_state(FPAddAlignMulti(self.width))
 982             alm.setup(m, dn.out_a, dn.out_b)
 983
 984         add0 = self.add_state(FPAddStage0(self.width))
 985         add0.setup(m, alm.out_a, alm.out_b)
 986
 987         add1 = self.add_state(FPAddStage1(self.width))
 988         add1.setup(m, add0.out_tot, add0.out_z)
 989
 990         n1 = self.add_state(FPNorm1(self.width))
 991         n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
 992
 993         rn = self.add_state(FPRound(self.width))
 994         rn.setup(m, n1.out_z, n1.out_roundz)
 995
 996         cor = self.add_state(FPCorrections(self.width))
 997         cor.setup(m, rn.out_z)
 998
 999         pa = self.add_state(FPPack(self.width))
1000         pa.setup(m, cor.out_z)
1001
1002         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
1003
1004         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
1005
1006         with m.FSM() as fsm:
1007
1008             for state in self.states:
1009                 with m.State(state.state_from):
1010                     state.action(m)
1011
1012         return m
1013
1014
1015 if __name__ == "__main__":
1016     alu = FPADD(width=32, single_cycle=True)
1017     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
1018
1019
1020     # works... but don't use, just do "python fname.py convert -t v"
1021     #print (verilog.convert(alu, ports=[
1022     #                        ports=alu.in_a.ports() + \
1023     #                              alu.in_b.ports() + \
1024     #                              alu.out_z.ports())