src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8
   9 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  10 from fpbase import MultiShiftRMerge
  11 #from fpbase import FPNumShiftMultiRight
  12
  13 class FPState(FPBase):
  14     def __init__(self, state_from):
  15         self.state_from = state_from
  16
  17     def set_inputs(self, inputs):
  18         self.inputs = inputs
  19         for k,v in inputs.items():
  20             setattr(self, k, v)
  21
  22     def set_outputs(self, outputs):
  23         self.outputs = outputs
  24         for k,v in outputs.items():
  25             setattr(self, k, v)
  26
  27
  28 class FPGetOpMod:
  29     def __init__(self, width):
  30         self.in_op = FPOp(width)
  31         self.out_op = FPNumIn(self.in_op, width)
  32         self.out_decode = Signal(reset_less=True)
  33
  34     def setup(self, m, in_op, out_op, out_decode):
  35         """ links module to inputs and outputs
  36         """
  37         m.d.comb += self.in_op.copy(in_op)
  38         m.d.comb += out_op.v.eq(self.out_op.v)
  39         m.d.comb += out_decode.eq(self.out_decode)
  40
  41     def elaborate(self, platform):
  42         m = Module()
  43         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
  44         #m.submodules.get_op_in = self.in_op
  45         m.submodules.get_op_out = self.out_op
  46         with m.If(self.out_decode):
  47             m.d.comb += [
  48                 self.out_op.decode(self.in_op.v),
  49             ]
  50         return m
  51
  52
  53 class FPGetOp(FPState):
  54     """ gets operand
  55     """
  56
  57     def __init__(self, in_state, out_state, in_op, width):
  58         FPState.__init__(self, in_state)
  59         self.out_state = out_state
  60         self.mod = FPGetOpMod(width)
  61         self.in_op = in_op
  62         self.out_op = FPNumIn(in_op, width)
  63         self.out_decode = Signal(reset_less=True)
  64
  65     def action(self, m):
  66         with m.If(self.out_decode):
  67             m.next = self.out_state
  68             m.d.sync += [
  69                 self.in_op.ack.eq(0),
  70                 self.out_op.copy(self.mod.out_op)
  71             ]
  72         with m.Else():
  73             m.d.sync += self.in_op.ack.eq(1)
  74
  75
  76 class FPGetOpB(FPState):
  77     """ gets operand b
  78     """
  79
  80     def __init__(self, in_b, width):
  81         FPState.__init__(self, "get_b")
  82         self.in_b = in_b
  83         self.b = FPNumIn(self.in_b, width)
  84
  85     def action(self, m):
  86         self.get_op(m, self.in_b, self.b, "special_cases")
  87
  88
  89 class FPAddSpecialCasesMod:
  90     """ special cases: NaNs, infs, zeros, denormalised
  91         NOTE: some of these are unique to add.  see "Special Operations"
  92         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  93     """
  94
  95     def __init__(self, width):
  96         self.in_a = FPNumBase(width)
  97         self.in_b = FPNumBase(width)
  98         self.out_z = FPNumOut(width, False)
  99         self.out_do_z = Signal(reset_less=True)
 100
 101     def setup(self, m, in_a, in_b, out_z, out_do_z):
 102         """ links module to inputs and outputs
 103         """
 104         m.d.comb += self.in_a.copy(in_a)
 105         m.d.comb += self.in_b.copy(in_b)
 106         #m.d.comb += out_z.v.eq(self.out_z.v)
 107         m.d.comb += out_do_z.eq(self.out_do_z)
 108
 109     def elaborate(self, platform):
 110         m = Module()
 111
 112         m.submodules.sc_in_a = self.in_a
 113         m.submodules.sc_in_b = self.in_b
 114         m.submodules.sc_out_z = self.out_z
 115
 116         s_nomatch = Signal()
 117         m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
 118
 119         m_match = Signal()
 120         m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
 121
 122         # if a is NaN or b is NaN return NaN
 123         with m.If(self.in_a.is_nan | self.in_b.is_nan):
 124             m.d.comb += self.out_do_z.eq(1)
 125             m.d.comb += self.out_z.nan(0)
 126
 127         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 128         # under review
 129
 130         ## if a is zero and b is NaN return -b
 131         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 132         #    m.d.comb += self.out_do_z.eq(1)
 133         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 134
 135         ## if b is zero and a is NaN return -a
 136         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 137         #    m.d.comb += self.out_do_z.eq(1)
 138         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 139
 140         ## if a is -zero and b is NaN return -b
 141         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 142         #    m.d.comb += self.out_do_z.eq(1)
 143         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 144
 145         ## if b is -zero and a is NaN return -a
 146         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 147         #    m.d.comb += self.out_do_z.eq(1)
 148         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 149
 150         # if a is inf return inf (or NaN)
 151         with m.Elif(self.in_a.is_inf):
 152             m.d.comb += self.out_do_z.eq(1)
 153             m.d.comb += self.out_z.inf(self.in_a.s)
 154             # if a is inf and signs don't match return NaN
 155             with m.If(self.in_b.exp_128 & s_nomatch):
 156                 m.d.comb += self.out_z.nan(0)
 157
 158         # if b is inf return inf
 159         with m.Elif(self.in_b.is_inf):
 160             m.d.comb += self.out_do_z.eq(1)
 161             m.d.comb += self.out_z.inf(self.in_b.s)
 162
 163         # if a is zero and b zero return signed-a/b
 164         with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
 165             m.d.comb += self.out_do_z.eq(1)
 166             m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
 167                                           self.in_b.e,
 168                                           self.in_b.m[3:-1])
 169
 170         # if a is zero return b
 171         with m.Elif(self.in_a.is_zero):
 172             m.d.comb += self.out_do_z.eq(1)
 173             m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
 174                                       self.in_b.m[3:-1])
 175
 176         # if b is zero return a
 177         with m.Elif(self.in_b.is_zero):
 178             m.d.comb += self.out_do_z.eq(1)
 179             m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
 180                                       self.in_a.m[3:-1])
 181
 182         # if a equal to -b return zero (+ve zero)
 183         with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
 184             m.d.comb += self.out_do_z.eq(1)
 185             m.d.comb += self.out_z.zero(0)
 186
 187         # Denormalised Number checks
 188         with m.Else():
 189             m.d.comb += self.out_do_z.eq(0)
 190
 191         return m
 192
 193
 194 class FPAddSpecialCases(FPState):
 195     """ special cases: NaNs, infs, zeros, denormalised
 196         NOTE: some of these are unique to add.  see "Special Operations"
 197         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 198     """
 199
 200     def __init__(self, width):
 201         FPState.__init__(self, "special_cases")
 202         self.mod = FPAddSpecialCasesMod(width)
 203         self.out_z = FPNumOut(width, False)
 204         self.out_do_z = Signal(reset_less=True)
 205
 206     def action(self, m):
 207         with m.If(self.out_do_z):
 208             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 209             m.next = "put_z"
 210         with m.Else():
 211             m.next = "denormalise"
 212
 213
 214 class FPAddDeNormMod(FPState):
 215
 216     def __init__(self, width):
 217         self.in_a = FPNumBase(width)
 218         self.in_b = FPNumBase(width)
 219         self.out_a = FPNumBase(width)
 220         self.out_b = FPNumBase(width)
 221
 222     def setup(self, m, in_a, in_b, out_a, out_b):
 223         """ links module to inputs and outputs
 224         """
 225         m.d.comb += self.in_a.copy(in_a)
 226         m.d.comb += self.in_b.copy(in_b)
 227         m.d.comb += out_a.copy(self.out_a)
 228         m.d.comb += out_b.copy(self.out_b)
 229
 230     def elaborate(self, platform):
 231         m = Module()
 232         m.submodules.denorm_in_a = self.in_a
 233         m.submodules.denorm_in_b = self.in_b
 234         m.submodules.denorm_out_a = self.out_a
 235         m.submodules.denorm_out_b = self.out_b
 236         # hmmm, don't like repeating identical code
 237         m.d.comb += self.out_a.copy(self.in_a)
 238         with m.If(self.in_a.exp_n127):
 239             m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
 240         with m.Else():
 241             m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
 242
 243         m.d.comb += self.out_b.copy(self.in_b)
 244         with m.If(self.in_b.exp_n127):
 245             m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
 246         with m.Else():
 247             m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
 248
 249         return m
 250
 251
 252 class FPAddDeNorm(FPState):
 253
 254     def __init__(self, width):
 255         FPState.__init__(self, "denormalise")
 256         self.mod = FPAddDeNormMod(width)
 257         self.out_a = FPNumBase(width)
 258         self.out_b = FPNumBase(width)
 259
 260     def action(self, m):
 261         # Denormalised Number checks
 262         m.next = "align"
 263         m.d.sync += self.a.copy(self.out_a)
 264         m.d.sync += self.b.copy(self.out_b)
 265
 266
 267 class FPAddAlignMultiMod(FPState):
 268
 269     def __init__(self, width):
 270         self.in_a = FPNumBase(width)
 271         self.in_b = FPNumBase(width)
 272         self.out_a = FPNumIn(None, width)
 273         self.out_b = FPNumIn(None, width)
 274         self.exp_eq = Signal(reset_less=True)
 275
 276     def setup(self, m, in_a, in_b, out_a, out_b, exp_eq):
 277         """ links module to inputs and outputs
 278         """
 279         m.d.comb += self.in_a.copy(in_a)
 280         m.d.comb += self.in_b.copy(in_b)
 281         m.d.comb += out_a.copy(self.out_a)
 282         m.d.comb += out_b.copy(self.out_b)
 283         m.d.comb += exp_eq.eq(self.exp_eq)
 284
 285     def elaborate(self, platform):
 286         # This one however (single-cycle) will do the shift
 287         # in one go.
 288
 289         m = Module()
 290
 291         #m.submodules.align_in_a = self.in_a
 292         #m.submodules.align_in_b = self.in_b
 293         m.submodules.align_out_a = self.out_a
 294         m.submodules.align_out_b = self.out_b
 295
 296         # NOTE: this does *not* do single-cycle multi-shifting,
 297         #       it *STAYS* in the align state until exponents match
 298
 299         # exponent of a greater than b: shift b down
 300         m.d.comb += self.exp_eq.eq(0)
 301         m.d.comb += self.out_a.copy(self.in_a)
 302         m.d.comb += self.out_b.copy(self.in_b)
 303         agtb = Signal(reset_less=True)
 304         altb = Signal(reset_less=True)
 305         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 306         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 307         with m.If(agtb):
 308             m.d.comb += self.out_b.shift_down(self.in_b)
 309         # exponent of b greater than a: shift a down
 310         with m.Elif(altb):
 311             m.d.comb += self.out_a.shift_down(self.in_a)
 312         # exponents equal: move to next stage.
 313         with m.Else():
 314             m.d.comb += self.exp_eq.eq(1)
 315         return m
 316
 317
 318 class FPAddAlignMulti(FPState):
 319
 320     def __init__(self, width):
 321         FPState.__init__(self, "align")
 322         self.mod = FPAddAlignMultiMod(width)
 323         self.out_a = FPNumIn(None, width)
 324         self.out_b = FPNumIn(None, width)
 325         self.exp_eq = Signal(reset_less=True)
 326
 327     def action(self, m):
 328         m.d.sync += self.a.copy(self.out_a)
 329         m.d.sync += self.b.copy(self.out_b)
 330         with m.If(self.exp_eq):
 331             m.next = "add_0"
 332
 333
 334 class FPAddAlignSingleMod:
 335
 336     def __init__(self, width):
 337         self.width = width
 338         self.in_a = FPNumBase(width)
 339         self.in_b = FPNumBase(width)
 340         self.out_a = FPNumIn(None, width)
 341         self.out_b = FPNumIn(None, width)
 342
 343     def setup(self, m, in_a, in_b, out_a, out_b):
 344         """ links module to inputs and outputs
 345         """
 346         m.d.comb += self.in_a.copy(in_a)
 347         m.d.comb += self.in_b.copy(in_b)
 348         m.d.comb += out_a.copy(self.out_a)
 349         m.d.comb += out_b.copy(self.out_b)
 350
 351     def elaborate(self, platform):
 352         """ Aligns A against B or B against A, depending on which has the
 353             greater exponent.  This is done in a *single* cycle using
 354             variable-width bit-shift
 355
 356             the shifter used here is quite expensive in terms of gates.
 357             Mux A or B in (and out) into temporaries, as only one of them
 358             needs to be aligned against the other
 359         """
 360         m = Module()
 361
 362         m.submodules.align_in_a = self.in_a
 363         m.submodules.align_in_b = self.in_b
 364         m.submodules.align_out_a = self.out_a
 365         m.submodules.align_out_b = self.out_b
 366
 367         # temporary (muxed) input and output to be shifted
 368         t_inp = FPNumBase(self.width)
 369         t_out = FPNumIn(None, self.width)
 370         espec = (len(self.in_a.e), True)
 371         msr = MultiShiftRMerge(self.in_a.m_width, espec)
 372         m.submodules.align_t_in = t_inp
 373         m.submodules.align_t_out = t_out
 374         m.submodules.multishift_r = msr
 375
 376         ediff = Signal(espec, reset_less=True)
 377         ediffr = Signal(espec, reset_less=True)
 378         tdiff = Signal(espec, reset_less=True)
 379         elz = Signal(reset_less=True)
 380         egz = Signal(reset_less=True)
 381
 382         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 383         m.d.comb += msr.inp.eq(t_inp.m)
 384         m.d.comb += msr.diff.eq(tdiff)
 385         m.d.comb += t_out.m.eq(msr.m)
 386         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 387         m.d.comb += t_out.s.eq(t_inp.s)
 388
 389         m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
 390         m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
 391         m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
 392         m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
 393
 394         # default: A-exp == B-exp, A and B untouched (fall through)
 395         m.d.comb += self.out_a.copy(self.in_a)
 396         m.d.comb += self.out_b.copy(self.in_b)
 397         # only one shifter (muxed)
 398         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 399         # exponent of a greater than b: shift b down
 400         with m.If(egz):
 401             m.d.comb += [t_inp.copy(self.in_b),
 402                          tdiff.eq(ediff),
 403                          self.out_b.copy(t_out),
 404                          self.out_b.s.eq(self.in_b.s), # whoops forgot sign
 405                         ]
 406         # exponent of b greater than a: shift a down
 407         with m.Elif(elz):
 408             m.d.comb += [t_inp.copy(self.in_a),
 409                          tdiff.eq(ediffr),
 410                          self.out_a.copy(t_out),
 411                          self.out_a.s.eq(self.in_a.s), # whoops forgot sign
 412                         ]
 413         return m
 414
 415
 416 class FPAddAlignSingle(FPState):
 417
 418     def __init__(self, width):
 419         FPState.__init__(self, "align")
 420         self.mod = FPAddAlignSingleMod(width)
 421         self.out_a = FPNumIn(None, width)
 422         self.out_b = FPNumIn(None, width)
 423
 424     def action(self, m):
 425         m.d.sync += self.a.copy(self.out_a)
 426         m.d.sync += self.b.copy(self.out_b)
 427         m.next = "add_0"
 428
 429
 430 class FPAddStage0Mod:
 431
 432     def __init__(self, width):
 433         self.in_a = FPNumBase(width)
 434         self.in_b = FPNumBase(width)
 435         self.in_z = FPNumBase(width, False)
 436         self.out_z = FPNumBase(width, False)
 437         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 438
 439     def elaborate(self, platform):
 440         m = Module()
 441         m.submodules.add0_in_a = self.in_a
 442         m.submodules.add0_in_b = self.in_b
 443         m.submodules.add0_out_z = self.out_z
 444
 445         m.d.comb += self.out_z.e.eq(self.in_a.e)
 446
 447         # store intermediate tests (and zero-extended mantissas)
 448         seq = Signal(reset_less=True)
 449         mge = Signal(reset_less=True)
 450         am0 = Signal(len(self.in_a.m)+1, reset_less=True)
 451         bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
 452         m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
 453                      mge.eq(self.in_a.m >= self.in_b.m),
 454                      am0.eq(Cat(self.in_a.m, 0)),
 455                      bm0.eq(Cat(self.in_b.m, 0))
 456                     ]
 457         # same-sign (both negative or both positive) add mantissas
 458         with m.If(seq):
 459             m.d.comb += [
 460                 self.out_tot.eq(am0 + bm0),
 461                 self.out_z.s.eq(self.in_a.s)
 462             ]
 463         # a mantissa greater than b, use a
 464         with m.Elif(mge):
 465             m.d.comb += [
 466                 self.out_tot.eq(am0 - bm0),
 467                 self.out_z.s.eq(self.in_a.s)
 468             ]
 469         # b mantissa greater than a, use b
 470         with m.Else():
 471             m.d.comb += [
 472                 self.out_tot.eq(bm0 - am0),
 473                 self.out_z.s.eq(self.in_b.s)
 474         ]
 475         return m
 476
 477
 478 class FPAddStage0(FPState):
 479     """ First stage of add.  covers same-sign (add) and subtract
 480         special-casing when mantissas are greater or equal, to
 481         give greatest accuracy.
 482     """
 483
 484     def __init__(self, width):
 485         FPState.__init__(self, "add_0")
 486         self.mod = FPAddStage0Mod(width)
 487         self.out_z = FPNumBase(width, False)
 488         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 489
 490     def setup(self, m, in_a, in_b):
 491         """ links module to inputs and outputs
 492         """
 493         m.submodules.add0 = self.mod
 494
 495         m.d.comb += self.mod.in_a.copy(in_a)
 496         m.d.comb += self.mod.in_b.copy(in_b)
 497
 498     def action(self, m):
 499         m.next = "add_1"
 500         # NOTE: these could be done as combinatorial (merge add0+add1)
 501         m.d.sync += self.out_z.copy(self.mod.out_z)
 502         m.d.sync += self.out_tot.eq(self.mod.out_tot)
 503
 504
 505 class FPAddStage1Mod(FPState):
 506     """ Second stage of add: preparation for normalisation.
 507         detects when tot sum is too big (tot[27] is kinda a carry bit)
 508     """
 509
 510     def __init__(self, width):
 511         self.out_norm = Signal(reset_less=True)
 512         self.in_z = FPNumBase(width, False)
 513         self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
 514         self.out_z = FPNumBase(width, False)
 515         self.out_of = Overflow()
 516
 517     def elaborate(self, platform):
 518         m = Module()
 519         #m.submodules.norm1_in_overflow = self.in_of
 520         #m.submodules.norm1_out_overflow = self.out_of
 521         #m.submodules.norm1_in_z = self.in_z
 522         #m.submodules.norm1_out_z = self.out_z
 523         m.d.comb += self.out_z.copy(self.in_z)
 524         # tot[27] gets set when the sum overflows. shift result down
 525         with m.If(self.in_tot[-1]):
 526             m.d.comb += [
 527                 self.out_z.m.eq(self.in_tot[4:]),
 528                 self.out_of.m0.eq(self.in_tot[4]),
 529                 self.out_of.guard.eq(self.in_tot[3]),
 530                 self.out_of.round_bit.eq(self.in_tot[2]),
 531                 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
 532                 self.out_z.e.eq(self.in_z.e + 1)
 533         ]
 534         # tot[27] zero case
 535         with m.Else():
 536             m.d.comb += [
 537                 self.out_z.m.eq(self.in_tot[3:]),
 538                 self.out_of.m0.eq(self.in_tot[3]),
 539                 self.out_of.guard.eq(self.in_tot[2]),
 540                 self.out_of.round_bit.eq(self.in_tot[1]),
 541                 self.out_of.sticky.eq(self.in_tot[0])
 542         ]
 543         return m
 544
 545
 546 class FPAddStage1(FPState):
 547
 548     def __init__(self, width):
 549         FPState.__init__(self, "add_1")
 550         self.mod = FPAddStage1Mod(width)
 551         self.out_z = FPNumBase(width, False)
 552         self.out_of = Overflow()
 553         self.norm_stb = Signal()
 554
 555     def setup(self, m, in_tot, in_z):
 556         """ links module to inputs and outputs
 557         """
 558         m.submodules.add1 = self.mod
 559
 560         m.d.comb += self.mod.in_z.copy(in_z)
 561         m.d.comb += self.mod.in_tot.eq(in_tot)
 562
 563         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 564
 565     def action(self, m):
 566         m.submodules.add1_out_overflow = self.out_of
 567         m.d.sync += self.out_of.copy(self.mod.out_of)
 568         m.d.sync += self.out_z.copy(self.mod.out_z)
 569         m.d.sync += self.norm_stb.eq(1)
 570         m.next = "normalise_1"
 571
 572
 573 class FPNorm1Mod:
 574
 575     def __init__(self, width, single_cycle=True):
 576         self.single_cycle = single_cycle
 577         self.width = width
 578         self.in_select = Signal(reset_less=True)
 579         self.out_norm = Signal(reset_less=True)
 580         self.in_z = FPNumBase(width, False)
 581         self.in_of = Overflow()
 582         self.temp_z = FPNumBase(width, False)
 583         self.temp_of = Overflow()
 584         self.out_z = FPNumBase(width, False)
 585         self.out_of = Overflow()
 586
 587     def elaborate(self, platform):
 588         m = Module()
 589
 590         mwid = self.out_z.m_width+2
 591         pe = PriorityEncoder(mwid)
 592         m.submodules.norm_pe = pe
 593
 594         m.submodules.norm1_out_z = self.out_z
 595         m.submodules.norm1_out_overflow = self.out_of
 596         m.submodules.norm1_temp_z = self.temp_z
 597         m.submodules.norm1_temp_of = self.temp_of
 598         m.submodules.norm1_in_z = self.in_z
 599         m.submodules.norm1_in_overflow = self.in_of
 600
 601         in_z = FPNumBase(self.width, False)
 602         in_of = Overflow()
 603         m.submodules.norm1_insel_z = in_z
 604         m.submodules.norm1_insel_overflow = in_of
 605
 606         if self.single_cycle:
 607             espec = (len(in_z.e), True)
 608             ediff_n126 = Signal(espec, reset_less=True)
 609             msr = MultiShiftRMerge(mwid, espec)
 610             m.submodules.multishift_r = msr
 611
 612         # select which of temp or in z/of to use
 613         with m.If(self.in_select):
 614             m.d.comb += in_z.copy(self.in_z)
 615             m.d.comb += in_of.copy(self.in_of)
 616         with m.Else():
 617             m.d.comb += in_z.copy(self.temp_z)
 618             m.d.comb += in_of.copy(self.temp_of)
 619         # initialise out from in (overridden below)
 620         m.d.comb += self.out_z.copy(in_z)
 621         m.d.comb += self.out_of.copy(in_of)
 622         # normalisation increase/decrease conditions
 623         decrease = Signal(reset_less=True)
 624         increase = Signal(reset_less=True)
 625         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 626         m.d.comb += increase.eq(in_z.exp_lt_n126)
 627         if not self.single_cycle:
 628             m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
 629         else:
 630             m.d.comb += self.out_norm.eq(0) # loop-end condition
 631         # decrease exponent
 632         with m.If(decrease):
 633             if not self.single_cycle:
 634                 m.d.comb += [
 635                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
 636                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
 637                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
 638                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
 639                 self.out_of.round_bit.eq(0),        # reset round bit
 640                 self.out_of.m0.eq(in_of.guard),
 641                 ]
 642             else:
 643                 # *sigh* not entirely obvious: count leading zeros (clz)
 644                 # with a PriorityEncoder: to find from the MSB
 645                 # we reverse the order of the bits.
 646                 temp_m = Signal(mwid, reset_less=True)
 647                 temp_s = Signal(mwid+1, reset_less=True)
 648                 clz = Signal((len(in_z.e), True), reset_less=True)
 649                 # make sure that the amount to decrease by does NOT
 650                 # go below the minimum non-INF/NaN exponent
 651                 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
 652                              in_z.exp_sub_n126)
 653                 m.d.comb += [
 654                     # cat round and guard bits back into the mantissa
 655                     temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
 656                     pe.i.eq(temp_m[::-1]),          # inverted
 657                     clz.eq(limclz),                 # count zeros from MSB down
 658                     temp_s.eq(temp_m << clz),       # shift mantissa UP
 659                     self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
 660                     self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
 661                     self.out_of.m0.eq(temp_s[2]),   # copy of mantissa[0]
 662                     # overflow in bits 0..1: got shifted too (leave sticky)
 663                     self.out_of.guard.eq(temp_s[1]),     # guard
 664                     self.out_of.round_bit.eq(temp_s[0]), # round
 665                 ]
 666         # increase exponent
 667         with m.Elif(increase):
 668             if not self.single_cycle:
 669                 m.d.comb += [
 670                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
 671                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
 672                 self.out_of.guard.eq(in_z.m[0]),
 673                 self.out_of.m0.eq(in_z.m[1]),
 674                 self.out_of.round_bit.eq(in_of.guard),
 675                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
 676                 ]
 677             else:
 678                 m.d.comb += [
 679                     ediff_n126.eq(in_z.N126 - in_z.e),
 680                     # connect multi-shifter to inp/out mantissa (and ediff)
 681                     msr.inp.eq(in_z.m),
 682                     msr.diff.eq(ediff_n126),
 683                     self.out_z.m.eq(msr.m),
 684                     self.out_z.e.eq(in_z.e + ediff_n126),
 685                 ]
 686
 687         return m
 688
 689
 690 class FPNorm1(FPState):
 691
 692     def __init__(self, width):
 693         FPState.__init__(self, "normalise_1")
 694         self.mod = FPNorm1Mod(width)
 695         self.stb = Signal(reset_less=True)
 696         self.ack = Signal(reset=0, reset_less=True)
 697         self.out_norm = Signal(reset_less=True)
 698         self.in_accept = Signal(reset_less=True)
 699         self.temp_z = FPNumBase(width)
 700         self.temp_of = Overflow()
 701         self.out_z = FPNumBase(width)
 702         self.out_roundz = Signal(reset_less=True)
 703
 704     def setup(self, m, in_z, in_of, norm_stb):
 705         """ links module to inputs and outputs
 706         """
 707         m.submodules.normalise_1 = self.mod
 708
 709         m.d.comb += self.mod.in_z.copy(in_z)
 710         m.d.comb += self.mod.in_of.copy(in_of)
 711
 712         m.d.comb += self.mod.in_select.eq(self.in_accept)
 713         m.d.comb += self.mod.temp_z.copy(self.temp_z)
 714         m.d.comb += self.mod.temp_of.copy(self.temp_of)
 715
 716         m.d.comb += self.out_z.copy(self.mod.out_z)
 717         m.d.comb += self.out_norm.eq(self.mod.out_norm)
 718
 719         m.d.comb += self.stb.eq(norm_stb)
 720         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
 721
 722     def action(self, m):
 723
 724         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
 725         m.d.sync += self.temp_of.copy(self.mod.out_of)
 726         m.d.sync += self.temp_z.copy(self.out_z)
 727         with m.If(self.out_norm):
 728             with m.If(self.in_accept):
 729                 m.d.sync += [
 730                     self.ack.eq(1),
 731                 ]
 732             with m.Else():
 733                 m.d.sync += self.ack.eq(0)
 734         with m.Else():
 735             # normalisation not required (or done).
 736             m.next = "round"
 737             m.d.sync += self.ack.eq(1)
 738             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
 739
 740
 741 class FPRoundMod:
 742
 743     def __init__(self, width):
 744         self.in_roundz = Signal(reset_less=True)
 745         self.in_z = FPNumBase(width, False)
 746         self.out_z = FPNumBase(width, False)
 747
 748     def elaborate(self, platform):
 749         m = Module()
 750         m.d.comb += self.out_z.copy(self.in_z)
 751         with m.If(self.in_roundz):
 752             m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
 753             with m.If(self.in_z.m == self.in_z.m1s): # all 1s
 754                 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
 755         return m
 756
 757
 758 class FPRound(FPState):
 759
 760     def __init__(self, width):
 761         FPState.__init__(self, "round")
 762         self.mod = FPRoundMod(width)
 763         self.out_z = FPNumBase(width)
 764
 765     def setup(self, m, in_z, roundz):
 766         """ links module to inputs and outputs
 767         """
 768         m.submodules.roundz = self.mod
 769
 770         m.d.comb += self.mod.in_z.copy(in_z)
 771         m.d.comb += self.mod.in_roundz.eq(roundz)
 772
 773     def action(self, m):
 774         m.d.sync += self.out_z.copy(self.mod.out_z)
 775         m.next = "corrections"
 776
 777
 778 class FPCorrectionsMod:
 779
 780     def __init__(self, width):
 781         self.in_z = FPNumOut(width, False)
 782         self.out_z = FPNumOut(width, False)
 783
 784     def elaborate(self, platform):
 785         m = Module()
 786         m.submodules.corr_in_z = self.in_z
 787         m.submodules.corr_out_z = self.out_z
 788         m.d.comb += self.out_z.copy(self.in_z)
 789         with m.If(self.in_z.is_denormalised):
 790             m.d.comb += self.out_z.e.eq(self.in_z.N127)
 791
 792         #        with m.If(self.in_z.is_overflowed):
 793         #            m.d.comb += self.out_z.inf(self.in_z.s)
 794         #        with m.Else():
 795         #            m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 796         return m
 797
 798
 799 class FPCorrections(FPState):
 800
 801     def __init__(self, width):
 802         FPState.__init__(self, "corrections")
 803         self.mod = FPCorrectionsMod(width)
 804         self.out_z = FPNumBase(width)
 805
 806     def setup(self, m, in_z):
 807         """ links module to inputs and outputs
 808         """
 809         m.submodules.corrections = self.mod
 810         m.d.comb += self.mod.in_z.copy(in_z)
 811
 812     def action(self, m):
 813         m.d.sync += self.out_z.copy(self.mod.out_z)
 814         m.next = "pack"
 815
 816
 817 class FPPackMod:
 818
 819     def __init__(self, width):
 820         self.in_z = FPNumOut(width, False)
 821         self.out_z = FPNumOut(width, False)
 822
 823     def elaborate(self, platform):
 824         m = Module()
 825         m.submodules.pack_in_z = self.in_z
 826         with m.If(self.in_z.is_overflowed):
 827             m.d.comb += self.out_z.inf(self.in_z.s)
 828         with m.Else():
 829             m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 830         return m
 831
 832
 833 class FPPack(FPState):
 834
 835     def __init__(self, width):
 836         FPState.__init__(self, "pack")
 837         self.mod = FPPackMod(width)
 838         self.out_z = FPNumOut(width, False)
 839
 840     def setup(self, m, in_z):
 841         """ links module to inputs and outputs
 842         """
 843         m.submodules.pack = self.mod
 844         m.d.comb += self.mod.in_z.copy(in_z)
 845
 846     def action(self, m):
 847         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
 848         m.next = "pack_put_z"
 849
 850
 851 class FPPutZ(FPState):
 852
 853     def __init__(self, state, in_z, out_z):
 854         FPState.__init__(self, state)
 855         self.in_z = in_z
 856         self.out_z = out_z
 857
 858     def action(self, m):
 859         m.d.sync += [
 860           self.out_z.v.eq(self.in_z.v)
 861         ]
 862         with m.If(self.out_z.stb & self.out_z.ack):
 863             m.d.sync += self.out_z.stb.eq(0)
 864             m.next = "get_a"
 865         with m.Else():
 866             m.d.sync += self.out_z.stb.eq(1)
 867
 868
 869 class FPADD:
 870
 871     def __init__(self, width, single_cycle=False):
 872         self.width = width
 873         self.single_cycle = single_cycle
 874
 875         self.in_a  = FPOp(width)
 876         self.in_b  = FPOp(width)
 877         self.out_z = FPOp(width)
 878
 879         self.states = []
 880
 881     def add_state(self, state):
 882         self.states.append(state)
 883         return state
 884
 885     def get_fragment(self, platform=None):
 886         """ creates the HDL code-fragment for FPAdd
 887         """
 888         m = Module()
 889         m.submodules.in_a = self.in_a
 890         m.submodules.in_b = self.in_b
 891         m.submodules.out_z = self.out_z
 892
 893         geta = self.add_state(FPGetOp("get_a", "get_b",
 894                                       self.in_a, self.width))
 895         a = geta.out_op
 896         geta.mod.setup(m, self.in_a, geta.out_op, geta.out_decode)
 897         m.submodules.get_a = geta.mod
 898
 899         getb = self.add_state(FPGetOp("get_b", "special_cases",
 900                                       self.in_b, self.width))
 901         b = getb.out_op
 902         getb.mod.setup(m, self.in_b, getb.out_op, getb.out_decode)
 903         m.submodules.get_b = getb.mod
 904
 905         sc = self.add_state(FPAddSpecialCases(self.width))
 906         sc.mod.setup(m, a, b, sc.out_z, sc.out_do_z)
 907         m.submodules.specialcases = sc.mod
 908
 909         dn = self.add_state(FPAddDeNorm(self.width))
 910         dn.set_inputs({"a": a, "b": b})
 911         #dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 912         dn.mod.setup(m, a, b, dn.out_a, dn.out_b)
 913         m.submodules.denormalise = dn.mod
 914
 915         if self.single_cycle:
 916             alm = self.add_state(FPAddAlignSingle(self.width))
 917             alm.set_inputs({"a": a, "b": b})
 918             alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 919             alm.mod.setup(m, a, b, alm.out_a, alm.out_b)
 920         else:
 921             alm = self.add_state(FPAddAlignMulti(self.width))
 922             alm.set_inputs({"a": a, "b": b})
 923             #alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 924             alm.mod.setup(m, a, b, alm.out_a, alm.out_b, alm.exp_eq)
 925         m.submodules.align = alm.mod
 926
 927         add0 = self.add_state(FPAddStage0(self.width))
 928         add0.setup(m, alm.out_a, alm.out_b)
 929
 930         add1 = self.add_state(FPAddStage1(self.width))
 931         add1.setup(m, add0.out_tot, add0.out_z)
 932
 933         n1 = self.add_state(FPNorm1(self.width))
 934         n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
 935
 936         rn = self.add_state(FPRound(self.width))
 937         rn.setup(m, n1.out_z, n1.out_roundz)
 938
 939         cor = self.add_state(FPCorrections(self.width))
 940         cor.setup(m, rn.out_z)
 941
 942         pa = self.add_state(FPPack(self.width))
 943         pa.setup(m, cor.out_z)
 944
 945         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z))
 946
 947         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z))
 948
 949         with m.FSM() as fsm:
 950
 951             for state in self.states:
 952                 with m.State(state.state_from):
 953                     state.action(m)
 954
 955         return m
 956
 957
 958 if __name__ == "__main__":
 959     alu = FPADD(width=32, single_cycle=True)
 960     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 961
 962
 963     # works... but don't use, just do "python fname.py convert -t v"
 964     #print (verilog.convert(alu, ports=[
 965     #                        ports=alu.in_a.ports() + \
 966     #                              alu.in_b.ports() + \
 967     #                              alu.out_z.ports())