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remove redundant in_z
[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux, Array, Const
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8 from math import log
9
10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
11 from fpbase import MultiShiftRMerge, Trigger
12 #from fpbase import FPNumShiftMultiRight
13
14
15 class FPState(FPBase):
16 def __init__(self, state_from):
17 self.state_from = state_from
18
19 def set_inputs(self, inputs):
20 self.inputs = inputs
21 for k,v in inputs.items():
22 setattr(self, k, v)
23
24 def set_outputs(self, outputs):
25 self.outputs = outputs
26 for k,v in outputs.items():
27 setattr(self, k, v)
28
29
30 class FPGetSyncOpsMod:
31 def __init__(self, width, num_ops=2):
32 self.width = width
33 self.num_ops = num_ops
34 inops = []
35 outops = []
36 for i in range(num_ops):
37 inops.append(Signal(width, reset_less=True))
38 outops.append(Signal(width, reset_less=True))
39 self.in_op = inops
40 self.out_op = outops
41 self.stb = Signal(num_ops)
42 self.ack = Signal()
43 self.ready = Signal(reset_less=True)
44 self.out_decode = Signal(reset_less=True)
45
46 def elaborate(self, platform):
47 m = Module()
48 m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
49 m.d.comb += self.out_decode.eq(self.ack & self.ready)
50 with m.If(self.out_decode):
51 for i in range(self.num_ops):
52 m.d.comb += [
53 self.out_op[i].eq(self.in_op[i]),
54 ]
55 return m
56
57 def ports(self):
58 return self.in_op + self.out_op + [self.stb, self.ack]
59
60
61 class FPOps(Trigger):
62 def __init__(self, width, num_ops):
63 Trigger.__init__(self)
64 self.width = width
65 self.num_ops = num_ops
66
67 res = []
68 for i in range(num_ops):
69 res.append(Signal(width))
70 self.v = Array(res)
71
72 def ports(self):
73 res = []
74 for i in range(self.num_ops):
75 res.append(self.v[i])
76 res.append(self.ack)
77 res.append(self.stb)
78 return res
79
80
81 class InputGroup:
82 def __init__(self, width, num_ops=2, num_rows=4):
83 self.width = width
84 self.num_ops = num_ops
85 self.num_rows = num_rows
86 self.mmax = int(log(self.num_rows) / log(2))
87 self.rs = []
88 self.mid = Signal(self.mmax, reset_less=True) # multiplex id
89 for i in range(num_rows):
90 self.rs.append(FPGetSyncOpsMod(width, num_ops))
91 self.rs = Array(self.rs)
92
93 self.out_op = FPOps(width, num_ops)
94
95 def elaborate(self, platform):
96 m = Module()
97
98 pe = PriorityEncoder(self.num_rows)
99 m.submodules.selector = pe
100 m.submodules.out_op = self.out_op
101 m.submodules += self.rs
102
103 # connect priority encoder
104 in_ready = []
105 for i in range(self.num_rows):
106 in_ready.append(self.rs[i].ready)
107 m.d.comb += pe.i.eq(Cat(*in_ready))
108
109 active = Signal(reset_less=True)
110 out_en = Signal(reset_less=True)
111 m.d.comb += active.eq(~pe.n) # encoder active
112 m.d.comb += out_en.eq(active & self.out_op.trigger)
113
114 # encoder active: ack relevant input, record MID, pass output
115 with m.If(out_en):
116 rs = self.rs[pe.o]
117 m.d.sync += self.mid.eq(pe.o)
118 m.d.sync += rs.ack.eq(0)
119 m.d.sync += self.out_op.stb.eq(0)
120 for j in range(self.num_ops):
121 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
122 with m.Else():
123 m.d.sync += self.out_op.stb.eq(1)
124 # acks all default to zero
125 for i in range(self.num_rows):
126 m.d.sync += self.rs[i].ack.eq(1)
127
128 return m
129
130 def ports(self):
131 res = []
132 for i in range(self.num_rows):
133 inop = self.rs[i]
134 res += inop.in_op + [inop.stb]
135 return self.out_op.ports() + res + [self.mid]
136
137
138 class FPGetOpMod:
139 def __init__(self, width):
140 self.in_op = FPOp(width)
141 self.out_op = Signal(width)
142 self.out_decode = Signal(reset_less=True)
143
144 def elaborate(self, platform):
145 m = Module()
146 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
147 m.submodules.get_op_in = self.in_op
148 #m.submodules.get_op_out = self.out_op
149 with m.If(self.out_decode):
150 m.d.comb += [
151 self.out_op.eq(self.in_op.v),
152 ]
153 return m
154
155
156 class FPGetOp(FPState):
157 """ gets operand
158 """
159
160 def __init__(self, in_state, out_state, in_op, width):
161 FPState.__init__(self, in_state)
162 self.out_state = out_state
163 self.mod = FPGetOpMod(width)
164 self.in_op = in_op
165 self.out_op = Signal(width)
166 self.out_decode = Signal(reset_less=True)
167
168 def setup(self, m, in_op):
169 """ links module to inputs and outputs
170 """
171 setattr(m.submodules, self.state_from, self.mod)
172 m.d.comb += self.mod.in_op.eq(in_op)
173 #m.d.comb += self.out_op.eq(self.mod.out_op)
174 m.d.comb += self.out_decode.eq(self.mod.out_decode)
175
176 def action(self, m):
177 with m.If(self.out_decode):
178 m.next = self.out_state
179 m.d.sync += [
180 self.in_op.ack.eq(0),
181 self.out_op.eq(self.mod.out_op)
182 ]
183 with m.Else():
184 m.d.sync += self.in_op.ack.eq(1)
185
186
187 class FPGet2OpMod(Trigger):
188 def __init__(self, width):
189 Trigger.__init__(self)
190 self.in_op1 = Signal(width, reset_less=True)
191 self.in_op2 = Signal(width, reset_less=True)
192 self.out_op1 = FPNumIn(None, width)
193 self.out_op2 = FPNumIn(None, width)
194
195 def elaborate(self, platform):
196 m = Trigger.elaborate(self, platform)
197 #m.submodules.get_op_in = self.in_op
198 m.submodules.get_op1_out = self.out_op1
199 m.submodules.get_op2_out = self.out_op2
200 with m.If(self.trigger):
201 m.d.comb += [
202 self.out_op1.decode(self.in_op1),
203 self.out_op2.decode(self.in_op2),
204 ]
205 return m
206
207
208 class FPGet2Op(FPState):
209 """ gets operands
210 """
211
212 def __init__(self, in_state, out_state, in_op1, in_op2, width):
213 FPState.__init__(self, in_state)
214 self.out_state = out_state
215 self.mod = FPGet2OpMod(width)
216 self.in_op1 = in_op1
217 self.in_op2 = in_op2
218 self.out_op1 = FPNumIn(None, width)
219 self.out_op2 = FPNumIn(None, width)
220 self.in_stb = Signal(reset_less=True)
221 self.out_ack = Signal(reset_less=True)
222 self.out_decode = Signal(reset_less=True)
223
224 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
225 """ links module to inputs and outputs
226 """
227 m.submodules.get_ops = self.mod
228 m.d.comb += self.mod.in_op1.eq(in_op1)
229 m.d.comb += self.mod.in_op2.eq(in_op2)
230 m.d.comb += self.mod.stb.eq(in_stb)
231 m.d.comb += self.out_ack.eq(self.mod.ack)
232 m.d.comb += self.out_decode.eq(self.mod.trigger)
233 m.d.comb += in_ack.eq(self.mod.ack)
234
235 def action(self, m):
236 with m.If(self.out_decode):
237 m.next = self.out_state
238 m.d.sync += [
239 self.mod.ack.eq(0),
240 #self.out_op1.v.eq(self.mod.out_op1.v),
241 #self.out_op2.v.eq(self.mod.out_op2.v),
242 self.out_op1.eq(self.mod.out_op1),
243 self.out_op2.eq(self.mod.out_op2)
244 ]
245 with m.Else():
246 m.d.sync += self.mod.ack.eq(1)
247
248 class FPNumBase2Ops:
249
250 def __init__(self, width, m_extra=True):
251 self.a = FPNumBase(width, m_extra)
252 self.b = FPNumBase(width, m_extra)
253
254 def eq(self, i):
255 return [self.a.eq(i.a), self.b.eq(i.b)]
256
257
258 class FPAddSpecialCasesMod:
259 """ special cases: NaNs, infs, zeros, denormalised
260 NOTE: some of these are unique to add. see "Special Operations"
261 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
262 """
263
264 def __init__(self, width):
265 self.width = width
266 self.i = self.ispec()
267 self.out_z = self.ospec()
268 self.out_do_z = Signal(reset_less=True)
269
270 def ispec(self):
271 return FPNumBase2Ops(self.width)
272
273 def ospec(self):
274 return FPNumOut(self.width, False)
275
276 def setup(self, m, in_a, in_b, out_do_z):
277 """ links module to inputs and outputs
278 """
279 m.submodules.specialcases = self
280 m.d.comb += self.i.a.eq(in_a)
281 m.d.comb += self.i.b.eq(in_b)
282 m.d.comb += out_do_z.eq(self.out_do_z)
283
284 def elaborate(self, platform):
285 m = Module()
286
287 m.submodules.sc_in_a = self.i.a
288 m.submodules.sc_in_b = self.i.b
289 m.submodules.sc_out_z = self.out_z
290
291 s_nomatch = Signal()
292 m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
293
294 m_match = Signal()
295 m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
296
297 # if a is NaN or b is NaN return NaN
298 with m.If(self.i.a.is_nan | self.i.b.is_nan):
299 m.d.comb += self.out_do_z.eq(1)
300 m.d.comb += self.out_z.nan(0)
301
302 # XXX WEIRDNESS for FP16 non-canonical NaN handling
303 # under review
304
305 ## if a is zero and b is NaN return -b
306 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
307 # m.d.comb += self.out_do_z.eq(1)
308 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
309
310 ## if b is zero and a is NaN return -a
311 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
312 # m.d.comb += self.out_do_z.eq(1)
313 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
314
315 ## if a is -zero and b is NaN return -b
316 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
317 # m.d.comb += self.out_do_z.eq(1)
318 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
319
320 ## if b is -zero and a is NaN return -a
321 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
322 # m.d.comb += self.out_do_z.eq(1)
323 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
324
325 # if a is inf return inf (or NaN)
326 with m.Elif(self.i.a.is_inf):
327 m.d.comb += self.out_do_z.eq(1)
328 m.d.comb += self.out_z.inf(self.i.a.s)
329 # if a is inf and signs don't match return NaN
330 with m.If(self.i.b.exp_128 & s_nomatch):
331 m.d.comb += self.out_z.nan(0)
332
333 # if b is inf return inf
334 with m.Elif(self.i.b.is_inf):
335 m.d.comb += self.out_do_z.eq(1)
336 m.d.comb += self.out_z.inf(self.i.b.s)
337
338 # if a is zero and b zero return signed-a/b
339 with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
340 m.d.comb += self.out_do_z.eq(1)
341 m.d.comb += self.out_z.create(self.i.a.s & self.i.b.s,
342 self.i.b.e,
343 self.i.b.m[3:-1])
344
345 # if a is zero return b
346 with m.Elif(self.i.a.is_zero):
347 m.d.comb += self.out_do_z.eq(1)
348 m.d.comb += self.out_z.create(self.i.b.s, self.i.b.e,
349 self.i.b.m[3:-1])
350
351 # if b is zero return a
352 with m.Elif(self.i.b.is_zero):
353 m.d.comb += self.out_do_z.eq(1)
354 m.d.comb += self.out_z.create(self.i.a.s, self.i.a.e,
355 self.i.a.m[3:-1])
356
357 # if a equal to -b return zero (+ve zero)
358 with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
359 m.d.comb += self.out_do_z.eq(1)
360 m.d.comb += self.out_z.zero(0)
361
362 # Denormalised Number checks
363 with m.Else():
364 m.d.comb += self.out_do_z.eq(0)
365
366 return m
367
368
369 class FPID:
370 def __init__(self, id_wid):
371 self.id_wid = id_wid
372 if self.id_wid:
373 self.in_mid = Signal(id_wid, reset_less=True)
374 self.out_mid = Signal(id_wid, reset_less=True)
375 else:
376 self.in_mid = None
377 self.out_mid = None
378
379 def idsync(self, m):
380 if self.id_wid is not None:
381 m.d.sync += self.out_mid.eq(self.in_mid)
382
383
384 class FPAddSpecialCases(FPState, FPID):
385 """ special cases: NaNs, infs, zeros, denormalised
386 NOTE: some of these are unique to add. see "Special Operations"
387 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
388 """
389
390 def __init__(self, width, id_wid):
391 FPState.__init__(self, "special_cases")
392 FPID.__init__(self, id_wid)
393 self.mod = FPAddSpecialCasesMod(width)
394 self.out_z = self.mod.ospec()
395 self.out_do_z = Signal(reset_less=True)
396
397 def setup(self, m, in_a, in_b, in_mid):
398 """ links module to inputs and outputs
399 """
400 self.mod.setup(m, in_a, in_b, self.out_do_z)
401 if self.in_mid is not None:
402 m.d.comb += self.in_mid.eq(in_mid)
403
404 def action(self, m):
405 self.idsync(m)
406 with m.If(self.out_do_z):
407 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
408 m.next = "put_z"
409 with m.Else():
410 m.next = "denormalise"
411
412
413 class FPAddSpecialCasesDeNorm(FPState, FPID):
414 """ special cases: NaNs, infs, zeros, denormalised
415 NOTE: some of these are unique to add. see "Special Operations"
416 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
417 """
418
419 def __init__(self, width, id_wid):
420 FPState.__init__(self, "special_cases")
421 FPID.__init__(self, id_wid)
422 self.smod = FPAddSpecialCasesMod(width)
423 self.out_z = self.smod.ospec()
424 self.out_do_z = Signal(reset_less=True)
425
426 self.dmod = FPAddDeNormMod(width)
427 self.o = self.dmod.ospec()
428
429 def setup(self, m, in_a, in_b, in_mid):
430 """ links module to inputs and outputs
431 """
432 self.smod.setup(m, in_a, in_b, self.out_do_z)
433 self.dmod.setup(m, in_a, in_b)
434 if self.in_mid is not None:
435 m.d.comb += self.in_mid.eq(in_mid)
436
437 def action(self, m):
438 self.idsync(m)
439 with m.If(self.out_do_z):
440 m.d.sync += self.out_z.v.eq(self.smod.out_z.v) # only take output
441 m.next = "put_z"
442 with m.Else():
443 m.next = "align"
444 m.d.sync += self.o.a.eq(self.dmod.o.a)
445 m.d.sync += self.o.b.eq(self.dmod.o.b)
446
447
448 class FPAddDeNormMod(FPState):
449
450 def __init__(self, width):
451 self.width = width
452 self.i = self.ispec()
453 self.o = self.ospec()
454
455 def ispec(self):
456 return FPNumBase2Ops(self.width)
457
458 def ospec(self):
459 return FPNumBase2Ops(self.width)
460
461 def setup(self, m, in_a, in_b):
462 """ links module to inputs and outputs
463 """
464 m.submodules.denormalise = self
465 m.d.comb += self.i.a.eq(in_a)
466 m.d.comb += self.i.b.eq(in_b)
467
468 def elaborate(self, platform):
469 m = Module()
470 m.submodules.denorm_in_a = self.i.a
471 m.submodules.denorm_in_b = self.i.b
472 m.submodules.denorm_out_a = self.o.a
473 m.submodules.denorm_out_b = self.o.b
474 # hmmm, don't like repeating identical code
475 m.d.comb += self.o.a.eq(self.i.a)
476 with m.If(self.i.a.exp_n127):
477 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
478 with m.Else():
479 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
480
481 m.d.comb += self.o.b.eq(self.i.b)
482 with m.If(self.i.b.exp_n127):
483 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
484 with m.Else():
485 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
486
487 return m
488
489
490 class FPAddDeNorm(FPState, FPID):
491
492 def __init__(self, width, id_wid):
493 FPState.__init__(self, "denormalise")
494 FPID.__init__(self, id_wid)
495 self.mod = FPAddDeNormMod(width)
496 self.out_a = FPNumBase(width)
497 self.out_b = FPNumBase(width)
498
499 def setup(self, m, in_a, in_b, in_mid):
500 """ links module to inputs and outputs
501 """
502 self.mod.setup(m, in_a, in_b)
503 if self.in_mid is not None:
504 m.d.comb += self.in_mid.eq(in_mid)
505
506 def action(self, m):
507 self.idsync(m)
508 # Denormalised Number checks
509 m.next = "align"
510 m.d.sync += self.out_a.eq(self.mod.out_a)
511 m.d.sync += self.out_b.eq(self.mod.out_b)
512
513
514 class FPAddAlignMultiMod(FPState):
515
516 def __init__(self, width):
517 self.in_a = FPNumBase(width)
518 self.in_b = FPNumBase(width)
519 self.out_a = FPNumIn(None, width)
520 self.out_b = FPNumIn(None, width)
521 self.exp_eq = Signal(reset_less=True)
522
523 def elaborate(self, platform):
524 # This one however (single-cycle) will do the shift
525 # in one go.
526
527 m = Module()
528
529 m.submodules.align_in_a = self.in_a
530 m.submodules.align_in_b = self.in_b
531 m.submodules.align_out_a = self.out_a
532 m.submodules.align_out_b = self.out_b
533
534 # NOTE: this does *not* do single-cycle multi-shifting,
535 # it *STAYS* in the align state until exponents match
536
537 # exponent of a greater than b: shift b down
538 m.d.comb += self.exp_eq.eq(0)
539 m.d.comb += self.out_a.eq(self.in_a)
540 m.d.comb += self.out_b.eq(self.in_b)
541 agtb = Signal(reset_less=True)
542 altb = Signal(reset_less=True)
543 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
544 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
545 with m.If(agtb):
546 m.d.comb += self.out_b.shift_down(self.in_b)
547 # exponent of b greater than a: shift a down
548 with m.Elif(altb):
549 m.d.comb += self.out_a.shift_down(self.in_a)
550 # exponents equal: move to next stage.
551 with m.Else():
552 m.d.comb += self.exp_eq.eq(1)
553 return m
554
555
556 class FPAddAlignMulti(FPState, FPID):
557
558 def __init__(self, width, id_wid):
559 FPID.__init__(self, id_wid)
560 FPState.__init__(self, "align")
561 self.mod = FPAddAlignMultiMod(width)
562 self.out_a = FPNumIn(None, width)
563 self.out_b = FPNumIn(None, width)
564 self.exp_eq = Signal(reset_less=True)
565
566 def setup(self, m, in_a, in_b, in_mid):
567 """ links module to inputs and outputs
568 """
569 m.submodules.align = self.mod
570 m.d.comb += self.mod.in_a.eq(in_a)
571 m.d.comb += self.mod.in_b.eq(in_b)
572 #m.d.comb += self.out_a.eq(self.mod.out_a)
573 #m.d.comb += self.out_b.eq(self.mod.out_b)
574 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
575 if self.in_mid is not None:
576 m.d.comb += self.in_mid.eq(in_mid)
577
578 def action(self, m):
579 self.idsync(m)
580 m.d.sync += self.out_a.eq(self.mod.out_a)
581 m.d.sync += self.out_b.eq(self.mod.out_b)
582 with m.If(self.exp_eq):
583 m.next = "add_0"
584
585
586 class FPNumIn2Ops:
587
588 def __init__(self, width):
589 self.a = FPNumIn(None, width)
590 self.b = FPNumIn(None, width)
591
592 def eq(self, i):
593 return [self.a.eq(i.a), self.b.eq(i.b)]
594
595
596 class FPAddAlignSingleMod:
597
598 def __init__(self, width):
599 self.width = width
600 self.i = self.ispec()
601 self.o = self.ospec()
602
603 def ispec(self):
604 return FPNumBase2Ops(self.width)
605
606 def ospec(self):
607 return FPNumIn2Ops(self.width)
608
609 def setup(self, m, in_a, in_b):
610 """ links module to inputs and outputs
611 """
612 m.submodules.align = self
613 m.d.comb += self.i.a.eq(in_a)
614 m.d.comb += self.i.b.eq(in_b)
615
616 def elaborate(self, platform):
617 """ Aligns A against B or B against A, depending on which has the
618 greater exponent. This is done in a *single* cycle using
619 variable-width bit-shift
620
621 the shifter used here is quite expensive in terms of gates.
622 Mux A or B in (and out) into temporaries, as only one of them
623 needs to be aligned against the other
624 """
625 m = Module()
626
627 m.submodules.align_in_a = self.i.a
628 m.submodules.align_in_b = self.i.b
629 m.submodules.align_out_a = self.o.a
630 m.submodules.align_out_b = self.o.b
631
632 # temporary (muxed) input and output to be shifted
633 t_inp = FPNumBase(self.width)
634 t_out = FPNumIn(None, self.width)
635 espec = (len(self.i.a.e), True)
636 msr = MultiShiftRMerge(self.i.a.m_width, espec)
637 m.submodules.align_t_in = t_inp
638 m.submodules.align_t_out = t_out
639 m.submodules.multishift_r = msr
640
641 ediff = Signal(espec, reset_less=True)
642 ediffr = Signal(espec, reset_less=True)
643 tdiff = Signal(espec, reset_less=True)
644 elz = Signal(reset_less=True)
645 egz = Signal(reset_less=True)
646
647 # connect multi-shifter to t_inp/out mantissa (and tdiff)
648 m.d.comb += msr.inp.eq(t_inp.m)
649 m.d.comb += msr.diff.eq(tdiff)
650 m.d.comb += t_out.m.eq(msr.m)
651 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
652 m.d.comb += t_out.s.eq(t_inp.s)
653
654 m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
655 m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
656 m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
657 m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
658
659 # default: A-exp == B-exp, A and B untouched (fall through)
660 m.d.comb += self.o.a.eq(self.i.a)
661 m.d.comb += self.o.b.eq(self.i.b)
662 # only one shifter (muxed)
663 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
664 # exponent of a greater than b: shift b down
665 with m.If(egz):
666 m.d.comb += [t_inp.eq(self.i.b),
667 tdiff.eq(ediff),
668 self.o.b.eq(t_out),
669 self.o.b.s.eq(self.i.b.s), # whoops forgot sign
670 ]
671 # exponent of b greater than a: shift a down
672 with m.Elif(elz):
673 m.d.comb += [t_inp.eq(self.i.a),
674 tdiff.eq(ediffr),
675 self.o.a.eq(t_out),
676 self.o.a.s.eq(self.i.a.s), # whoops forgot sign
677 ]
678 return m
679
680
681 class FPAddAlignSingle(FPState, FPID):
682
683 def __init__(self, width, id_wid):
684 FPState.__init__(self, "align")
685 FPID.__init__(self, id_wid)
686 self.mod = FPAddAlignSingleMod(width)
687 self.out_a = FPNumIn(None, width)
688 self.out_b = FPNumIn(None, width)
689
690 def setup(self, m, in_a, in_b, in_mid):
691 """ links module to inputs and outputs
692 """
693 self.mod.setup(m, in_a, in_b)
694 if self.in_mid is not None:
695 m.d.comb += self.in_mid.eq(in_mid)
696
697 def action(self, m):
698 self.idsync(m)
699 # NOTE: could be done as comb
700 m.d.sync += self.out_a.eq(self.mod.out_a)
701 m.d.sync += self.out_b.eq(self.mod.out_b)
702 m.next = "add_0"
703
704
705 class FPAddAlignSingleAdd(FPState, FPID):
706
707 def __init__(self, width, id_wid):
708 FPState.__init__(self, "align")
709 FPID.__init__(self, id_wid)
710 self.mod = FPAddAlignSingleMod(width)
711 self.o = self.mod.ospec()
712
713 self.a0mod = FPAddStage0Mod(width)
714 self.a0_out_z = FPNumBase(width, False)
715 self.out_tot = Signal(self.a0_out_z.m_width + 4, reset_less=True)
716 self.a0_out_z = FPNumBase(width, False)
717
718 self.a1mod = FPAddStage1Mod(width)
719 self.out_z = FPNumBase(width, False)
720 self.out_of = Overflow()
721
722 def setup(self, m, in_a, in_b, in_mid):
723 """ links module to inputs and outputs
724 """
725 self.mod.setup(m, in_a, in_b)
726 m.d.comb += self.o.eq(self.mod.o)
727
728 self.a0mod.setup(m, self.o.a, self.o.b)
729 m.d.comb += self.a0_out_z.eq(self.a0mod.out_z)
730 m.d.comb += self.out_tot.eq(self.a0mod.out_tot)
731
732 self.a1mod.setup(m, self.out_tot, self.a0_out_z)
733
734 if self.in_mid is not None:
735 m.d.comb += self.in_mid.eq(in_mid)
736
737 def action(self, m):
738 self.idsync(m)
739 m.d.sync += self.out_of.eq(self.a1mod.out_of)
740 m.d.sync += self.out_z.eq(self.a1mod.out_z)
741 m.next = "normalise_1"
742
743
744 class FPAddStage0Mod:
745
746 def __init__(self, width):
747 self.in_a = FPNumBase(width)
748 self.in_b = FPNumBase(width)
749 self.out_z = FPNumBase(width, False)
750 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
751
752 def setup(self, m, in_a, in_b):
753 """ links module to inputs and outputs
754 """
755 m.submodules.add0 = self
756 m.d.comb += self.in_a.eq(in_a)
757 m.d.comb += self.in_b.eq(in_b)
758
759 def elaborate(self, platform):
760 m = Module()
761 m.submodules.add0_in_a = self.in_a
762 m.submodules.add0_in_b = self.in_b
763 m.submodules.add0_out_z = self.out_z
764
765 m.d.comb += self.out_z.e.eq(self.in_a.e)
766
767 # store intermediate tests (and zero-extended mantissas)
768 seq = Signal(reset_less=True)
769 mge = Signal(reset_less=True)
770 am0 = Signal(len(self.in_a.m)+1, reset_less=True)
771 bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
772 m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
773 mge.eq(self.in_a.m >= self.in_b.m),
774 am0.eq(Cat(self.in_a.m, 0)),
775 bm0.eq(Cat(self.in_b.m, 0))
776 ]
777 # same-sign (both negative or both positive) add mantissas
778 with m.If(seq):
779 m.d.comb += [
780 self.out_tot.eq(am0 + bm0),
781 self.out_z.s.eq(self.in_a.s)
782 ]
783 # a mantissa greater than b, use a
784 with m.Elif(mge):
785 m.d.comb += [
786 self.out_tot.eq(am0 - bm0),
787 self.out_z.s.eq(self.in_a.s)
788 ]
789 # b mantissa greater than a, use b
790 with m.Else():
791 m.d.comb += [
792 self.out_tot.eq(bm0 - am0),
793 self.out_z.s.eq(self.in_b.s)
794 ]
795 return m
796
797
798 class FPAddStage0(FPState, FPID):
799 """ First stage of add. covers same-sign (add) and subtract
800 special-casing when mantissas are greater or equal, to
801 give greatest accuracy.
802 """
803
804 def __init__(self, width, id_wid):
805 FPState.__init__(self, "add_0")
806 FPID.__init__(self, id_wid)
807 self.mod = FPAddStage0Mod(width)
808 self.out_z = FPNumBase(width, False)
809 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
810
811 def setup(self, m, in_a, in_b, in_mid):
812 """ links module to inputs and outputs
813 """
814 self.mod.setup(m, in_a, in_b)
815 if self.in_mid is not None:
816 m.d.comb += self.in_mid.eq(in_mid)
817
818 def action(self, m):
819 self.idsync(m)
820 # NOTE: these could be done as combinatorial (merge add0+add1)
821 m.d.sync += self.out_z.eq(self.mod.out_z)
822 m.d.sync += self.out_tot.eq(self.mod.out_tot)
823 m.next = "add_1"
824
825
826 class FPAddStage1Mod(FPState):
827 """ Second stage of add: preparation for normalisation.
828 detects when tot sum is too big (tot[27] is kinda a carry bit)
829 """
830
831 def __init__(self, width):
832 self.out_norm = Signal(reset_less=True)
833 self.in_z = FPNumBase(width, False)
834 self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
835 self.out_z = FPNumBase(width, False)
836 self.out_of = Overflow()
837
838 def setup(self, m, in_tot, in_z):
839 """ links module to inputs and outputs
840 """
841 m.submodules.add1 = self
842 m.submodules.add1_out_overflow = self.out_of
843
844 m.d.comb += self.in_z.eq(in_z)
845 m.d.comb += self.in_tot.eq(in_tot)
846
847 def elaborate(self, platform):
848 m = Module()
849 #m.submodules.norm1_in_overflow = self.in_of
850 #m.submodules.norm1_out_overflow = self.out_of
851 #m.submodules.norm1_in_z = self.in_z
852 #m.submodules.norm1_out_z = self.out_z
853 m.d.comb += self.out_z.eq(self.in_z)
854 # tot[-1] (MSB) gets set when the sum overflows. shift result down
855 with m.If(self.in_tot[-1]):
856 m.d.comb += [
857 self.out_z.m.eq(self.in_tot[4:]),
858 self.out_of.m0.eq(self.in_tot[4]),
859 self.out_of.guard.eq(self.in_tot[3]),
860 self.out_of.round_bit.eq(self.in_tot[2]),
861 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
862 self.out_z.e.eq(self.in_z.e + 1)
863 ]
864 # tot[-1] (MSB) zero case
865 with m.Else():
866 m.d.comb += [
867 self.out_z.m.eq(self.in_tot[3:]),
868 self.out_of.m0.eq(self.in_tot[3]),
869 self.out_of.guard.eq(self.in_tot[2]),
870 self.out_of.round_bit.eq(self.in_tot[1]),
871 self.out_of.sticky.eq(self.in_tot[0])
872 ]
873 return m
874
875
876 class FPAddStage1(FPState, FPID):
877
878 def __init__(self, width, id_wid):
879 FPState.__init__(self, "add_1")
880 FPID.__init__(self, id_wid)
881 self.mod = FPAddStage1Mod(width)
882 self.out_z = FPNumBase(width, False)
883 self.out_of = Overflow()
884 self.norm_stb = Signal()
885
886 def setup(self, m, in_tot, in_z, in_mid):
887 """ links module to inputs and outputs
888 """
889 self.mod.setup(m, in_tot, in_z)
890
891 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
892
893 if self.in_mid is not None:
894 m.d.comb += self.in_mid.eq(in_mid)
895
896 def action(self, m):
897 self.idsync(m)
898 m.d.sync += self.out_of.eq(self.mod.out_of)
899 m.d.sync += self.out_z.eq(self.mod.out_z)
900 m.d.sync += self.norm_stb.eq(1)
901 m.next = "normalise_1"
902
903
904 class FPNormaliseModSingle:
905
906 def __init__(self, width):
907 self.width = width
908 self.in_z = FPNumBase(width, False)
909 self.out_z = FPNumBase(width, False)
910
911 def setup(self, m, in_z, out_z, modname):
912 """ links module to inputs and outputs
913 """
914 m.submodules.normalise = self
915 m.d.comb += self.in_z.eq(in_z)
916 m.d.comb += out_z.eq(self.out_z)
917
918 def elaborate(self, platform):
919 m = Module()
920
921 mwid = self.out_z.m_width+2
922 pe = PriorityEncoder(mwid)
923 m.submodules.norm_pe = pe
924
925 m.submodules.norm1_out_z = self.out_z
926 m.submodules.norm1_in_z = self.in_z
927
928 in_z = FPNumBase(self.width, False)
929 in_of = Overflow()
930 m.submodules.norm1_insel_z = in_z
931 m.submodules.norm1_insel_overflow = in_of
932
933 espec = (len(in_z.e), True)
934 ediff_n126 = Signal(espec, reset_less=True)
935 msr = MultiShiftRMerge(mwid, espec)
936 m.submodules.multishift_r = msr
937
938 m.d.comb += in_z.eq(self.in_z)
939 m.d.comb += in_of.eq(self.in_of)
940 # initialise out from in (overridden below)
941 m.d.comb += self.out_z.eq(in_z)
942 m.d.comb += self.out_of.eq(in_of)
943 # normalisation increase/decrease conditions
944 decrease = Signal(reset_less=True)
945 m.d.comb += decrease.eq(in_z.m_msbzero)
946 # decrease exponent
947 with m.If(decrease):
948 # *sigh* not entirely obvious: count leading zeros (clz)
949 # with a PriorityEncoder: to find from the MSB
950 # we reverse the order of the bits.
951 temp_m = Signal(mwid, reset_less=True)
952 temp_s = Signal(mwid+1, reset_less=True)
953 clz = Signal((len(in_z.e), True), reset_less=True)
954 m.d.comb += [
955 # cat round and guard bits back into the mantissa
956 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
957 pe.i.eq(temp_m[::-1]), # inverted
958 clz.eq(pe.o), # count zeros from MSB down
959 temp_s.eq(temp_m << clz), # shift mantissa UP
960 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
961 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
962 ]
963
964 return m
965
966
967 class FPNorm1ModSingle:
968
969 def __init__(self, width):
970 self.width = width
971 self.out_norm = Signal(reset_less=True)
972 self.in_z = FPNumBase(width, False)
973 self.in_of = Overflow()
974 self.out_z = FPNumBase(width, False)
975 self.out_of = Overflow()
976
977 def setup(self, m, in_z, in_of, out_z):
978 """ links module to inputs and outputs
979 """
980 m.submodules.normalise_1 = self
981
982 m.d.comb += self.in_z.eq(in_z)
983 m.d.comb += self.in_of.eq(in_of)
984
985 m.d.comb += out_z.eq(self.out_z)
986
987 def elaborate(self, platform):
988 m = Module()
989
990 mwid = self.out_z.m_width+2
991 pe = PriorityEncoder(mwid)
992 m.submodules.norm_pe = pe
993
994 m.submodules.norm1_out_z = self.out_z
995 m.submodules.norm1_out_overflow = self.out_of
996 m.submodules.norm1_in_z = self.in_z
997 m.submodules.norm1_in_overflow = self.in_of
998
999 in_z = FPNumBase(self.width, False)
1000 in_of = Overflow()
1001 m.submodules.norm1_insel_z = in_z
1002 m.submodules.norm1_insel_overflow = in_of
1003
1004 espec = (len(in_z.e), True)
1005 ediff_n126 = Signal(espec, reset_less=True)
1006 msr = MultiShiftRMerge(mwid, espec)
1007 m.submodules.multishift_r = msr
1008
1009 m.d.comb += in_z.eq(self.in_z)
1010 m.d.comb += in_of.eq(self.in_of)
1011 # initialise out from in (overridden below)
1012 m.d.comb += self.out_z.eq(in_z)
1013 m.d.comb += self.out_of.eq(in_of)
1014 # normalisation increase/decrease conditions
1015 decrease = Signal(reset_less=True)
1016 increase = Signal(reset_less=True)
1017 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1018 m.d.comb += increase.eq(in_z.exp_lt_n126)
1019 # decrease exponent
1020 with m.If(decrease):
1021 # *sigh* not entirely obvious: count leading zeros (clz)
1022 # with a PriorityEncoder: to find from the MSB
1023 # we reverse the order of the bits.
1024 temp_m = Signal(mwid, reset_less=True)
1025 temp_s = Signal(mwid+1, reset_less=True)
1026 clz = Signal((len(in_z.e), True), reset_less=True)
1027 # make sure that the amount to decrease by does NOT
1028 # go below the minimum non-INF/NaN exponent
1029 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
1030 in_z.exp_sub_n126)
1031 m.d.comb += [
1032 # cat round and guard bits back into the mantissa
1033 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1034 pe.i.eq(temp_m[::-1]), # inverted
1035 clz.eq(limclz), # count zeros from MSB down
1036 temp_s.eq(temp_m << clz), # shift mantissa UP
1037 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
1038 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
1039 self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
1040 # overflow in bits 0..1: got shifted too (leave sticky)
1041 self.out_of.guard.eq(temp_s[1]), # guard
1042 self.out_of.round_bit.eq(temp_s[0]), # round
1043 ]
1044 # increase exponent
1045 with m.Elif(increase):
1046 temp_m = Signal(mwid+1, reset_less=True)
1047 m.d.comb += [
1048 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
1049 in_z.m)),
1050 ediff_n126.eq(in_z.N126 - in_z.e),
1051 # connect multi-shifter to inp/out mantissa (and ediff)
1052 msr.inp.eq(temp_m),
1053 msr.diff.eq(ediff_n126),
1054 self.out_z.m.eq(msr.m[3:]),
1055 self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
1056 # overflow in bits 0..1: got shifted too (leave sticky)
1057 self.out_of.guard.eq(temp_s[2]), # guard
1058 self.out_of.round_bit.eq(temp_s[1]), # round
1059 self.out_of.sticky.eq(temp_s[0]), # sticky
1060 self.out_z.e.eq(in_z.e + ediff_n126),
1061 ]
1062
1063 return m
1064
1065
1066 class FPNorm1ModMulti:
1067
1068 def __init__(self, width, single_cycle=True):
1069 self.width = width
1070 self.in_select = Signal(reset_less=True)
1071 self.out_norm = Signal(reset_less=True)
1072 self.in_z = FPNumBase(width, False)
1073 self.in_of = Overflow()
1074 self.temp_z = FPNumBase(width, False)
1075 self.temp_of = Overflow()
1076 self.out_z = FPNumBase(width, False)
1077 self.out_of = Overflow()
1078
1079 def elaborate(self, platform):
1080 m = Module()
1081
1082 m.submodules.norm1_out_z = self.out_z
1083 m.submodules.norm1_out_overflow = self.out_of
1084 m.submodules.norm1_temp_z = self.temp_z
1085 m.submodules.norm1_temp_of = self.temp_of
1086 m.submodules.norm1_in_z = self.in_z
1087 m.submodules.norm1_in_overflow = self.in_of
1088
1089 in_z = FPNumBase(self.width, False)
1090 in_of = Overflow()
1091 m.submodules.norm1_insel_z = in_z
1092 m.submodules.norm1_insel_overflow = in_of
1093
1094 # select which of temp or in z/of to use
1095 with m.If(self.in_select):
1096 m.d.comb += in_z.eq(self.in_z)
1097 m.d.comb += in_of.eq(self.in_of)
1098 with m.Else():
1099 m.d.comb += in_z.eq(self.temp_z)
1100 m.d.comb += in_of.eq(self.temp_of)
1101 # initialise out from in (overridden below)
1102 m.d.comb += self.out_z.eq(in_z)
1103 m.d.comb += self.out_of.eq(in_of)
1104 # normalisation increase/decrease conditions
1105 decrease = Signal(reset_less=True)
1106 increase = Signal(reset_less=True)
1107 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1108 m.d.comb += increase.eq(in_z.exp_lt_n126)
1109 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1110 # decrease exponent
1111 with m.If(decrease):
1112 m.d.comb += [
1113 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
1114 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1115 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1116 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1117 self.out_of.round_bit.eq(0), # reset round bit
1118 self.out_of.m0.eq(in_of.guard),
1119 ]
1120 # increase exponent
1121 with m.Elif(increase):
1122 m.d.comb += [
1123 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
1124 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1125 self.out_of.guard.eq(in_z.m[0]),
1126 self.out_of.m0.eq(in_z.m[1]),
1127 self.out_of.round_bit.eq(in_of.guard),
1128 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1129 ]
1130
1131 return m
1132
1133
1134 class FPNorm1Single(FPState, FPID):
1135
1136 def __init__(self, width, id_wid, single_cycle=True):
1137 FPID.__init__(self, id_wid)
1138 FPState.__init__(self, "normalise_1")
1139 self.mod = FPNorm1ModSingle(width)
1140 self.out_norm = Signal(reset_less=True)
1141 self.out_z = FPNumBase(width)
1142 self.out_roundz = Signal(reset_less=True)
1143
1144 def setup(self, m, in_z, in_of, in_mid):
1145 """ links module to inputs and outputs
1146 """
1147 self.mod.setup(m, in_z, in_of, self.out_z)
1148
1149 if self.in_mid is not None:
1150 m.d.comb += self.in_mid.eq(in_mid)
1151
1152 def action(self, m):
1153 self.idsync(m)
1154 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1155 m.next = "round"
1156
1157
1158 class FPNorm1Multi(FPState, FPID):
1159
1160 def __init__(self, width, id_wid):
1161 FPID.__init__(self, id_wid)
1162 FPState.__init__(self, "normalise_1")
1163 self.mod = FPNorm1ModMulti(width)
1164 self.stb = Signal(reset_less=True)
1165 self.ack = Signal(reset=0, reset_less=True)
1166 self.out_norm = Signal(reset_less=True)
1167 self.in_accept = Signal(reset_less=True)
1168 self.temp_z = FPNumBase(width)
1169 self.temp_of = Overflow()
1170 self.out_z = FPNumBase(width)
1171 self.out_roundz = Signal(reset_less=True)
1172
1173 def setup(self, m, in_z, in_of, norm_stb, in_mid):
1174 """ links module to inputs and outputs
1175 """
1176 self.mod.setup(m, in_z, in_of, norm_stb,
1177 self.in_accept, self.temp_z, self.temp_of,
1178 self.out_z, self.out_norm)
1179
1180 m.d.comb += self.stb.eq(norm_stb)
1181 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1182
1183 if self.in_mid is not None:
1184 m.d.comb += self.in_mid.eq(in_mid)
1185
1186 def action(self, m):
1187 self.idsync(m)
1188 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1189 m.d.sync += self.temp_of.eq(self.mod.out_of)
1190 m.d.sync += self.temp_z.eq(self.out_z)
1191 with m.If(self.out_norm):
1192 with m.If(self.in_accept):
1193 m.d.sync += [
1194 self.ack.eq(1),
1195 ]
1196 with m.Else():
1197 m.d.sync += self.ack.eq(0)
1198 with m.Else():
1199 # normalisation not required (or done).
1200 m.next = "round"
1201 m.d.sync += self.ack.eq(1)
1202 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1203
1204
1205 class FPNormToPack(FPState, FPID):
1206
1207 def __init__(self, width, id_wid):
1208 FPID.__init__(self, id_wid)
1209 FPState.__init__(self, "normalise_1")
1210 self.width = width
1211
1212 def setup(self, m, in_z, in_of, in_mid):
1213 """ links module to inputs and outputs
1214 """
1215
1216 # Normalisation (chained to input in_z+in_of)
1217 nmod = FPNorm1ModSingle(self.width)
1218 n_out_z = FPNumBase(self.width)
1219 n_out_roundz = Signal(reset_less=True)
1220 nmod.setup(m, in_z, in_of, n_out_z)
1221
1222 # Rounding (chained to normalisation)
1223 rmod = FPRoundMod(self.width)
1224 r_out_z = FPNumBase(self.width)
1225 rmod.setup(m, n_out_z, n_out_roundz)
1226 m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
1227 m.d.comb += r_out_z.eq(rmod.out_z)
1228
1229 # Corrections (chained to rounding)
1230 cmod = FPCorrectionsMod(self.width)
1231 c_out_z = FPNumBase(self.width)
1232 cmod.setup(m, r_out_z)
1233 m.d.comb += c_out_z.eq(cmod.out_z)
1234
1235 # Pack (chained to corrections)
1236 self.pmod = FPPackMod(self.width)
1237 self.out_z = FPNumBase(self.width)
1238 self.pmod.setup(m, c_out_z)
1239
1240 # Multiplex ID
1241 if self.in_mid is not None:
1242 m.d.comb += self.in_mid.eq(in_mid)
1243
1244 def action(self, m):
1245 self.idsync(m) # copies incoming ID to outgoing
1246 m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
1247 m.next = "pack_put_z"
1248
1249
1250 class FPRoundMod:
1251
1252 def __init__(self, width):
1253 self.in_roundz = Signal(reset_less=True)
1254 self.in_z = FPNumBase(width, False)
1255 self.out_z = FPNumBase(width, False)
1256
1257 def setup(self, m, in_z, roundz):
1258 m.submodules.roundz = self
1259
1260 m.d.comb += self.in_z.eq(in_z)
1261 m.d.comb += self.in_roundz.eq(roundz)
1262
1263 def elaborate(self, platform):
1264 m = Module()
1265 m.d.comb += self.out_z.eq(self.in_z)
1266 with m.If(self.in_roundz):
1267 m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
1268 with m.If(self.in_z.m == self.in_z.m1s): # all 1s
1269 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
1270 return m
1271
1272
1273 class FPRound(FPState, FPID):
1274
1275 def __init__(self, width, id_wid):
1276 FPState.__init__(self, "round")
1277 FPID.__init__(self, id_wid)
1278 self.mod = FPRoundMod(width)
1279 self.out_z = FPNumBase(width)
1280
1281 def setup(self, m, in_z, roundz, in_mid):
1282 """ links module to inputs and outputs
1283 """
1284 self.mod.setup(m, in_z, roundz)
1285
1286 if self.in_mid is not None:
1287 m.d.comb += self.in_mid.eq(in_mid)
1288
1289 def action(self, m):
1290 self.idsync(m)
1291 m.d.sync += self.out_z.eq(self.mod.out_z)
1292 m.next = "corrections"
1293
1294
1295 class FPCorrectionsMod:
1296
1297 def __init__(self, width):
1298 self.in_z = FPNumOut(width, False)
1299 self.out_z = FPNumOut(width, False)
1300
1301 def setup(self, m, in_z):
1302 """ links module to inputs and outputs
1303 """
1304 m.submodules.corrections = self
1305 m.d.comb += self.in_z.eq(in_z)
1306
1307 def elaborate(self, platform):
1308 m = Module()
1309 m.submodules.corr_in_z = self.in_z
1310 m.submodules.corr_out_z = self.out_z
1311 m.d.comb += self.out_z.eq(self.in_z)
1312 with m.If(self.in_z.is_denormalised):
1313 m.d.comb += self.out_z.e.eq(self.in_z.N127)
1314 return m
1315
1316
1317 class FPCorrections(FPState, FPID):
1318
1319 def __init__(self, width, id_wid):
1320 FPState.__init__(self, "corrections")
1321 FPID.__init__(self, id_wid)
1322 self.mod = FPCorrectionsMod(width)
1323 self.out_z = FPNumBase(width)
1324
1325 def setup(self, m, in_z, in_mid):
1326 """ links module to inputs and outputs
1327 """
1328 self.mod.setup(m, in_z)
1329 if self.in_mid is not None:
1330 m.d.comb += self.in_mid.eq(in_mid)
1331
1332 def action(self, m):
1333 self.idsync(m)
1334 m.d.sync += self.out_z.eq(self.mod.out_z)
1335 m.next = "pack"
1336
1337
1338 class FPPackMod:
1339
1340 def __init__(self, width):
1341 self.in_z = FPNumOut(width, False)
1342 self.out_z = FPNumOut(width, False)
1343
1344 def setup(self, m, in_z):
1345 """ links module to inputs and outputs
1346 """
1347 m.submodules.pack = self
1348 m.d.comb += self.in_z.eq(in_z)
1349
1350 def elaborate(self, platform):
1351 m = Module()
1352 m.submodules.pack_in_z = self.in_z
1353 with m.If(self.in_z.is_overflowed):
1354 m.d.comb += self.out_z.inf(self.in_z.s)
1355 with m.Else():
1356 m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
1357 return m
1358
1359
1360 class FPPack(FPState, FPID):
1361
1362 def __init__(self, width, id_wid):
1363 FPState.__init__(self, "pack")
1364 FPID.__init__(self, id_wid)
1365 self.mod = FPPackMod(width)
1366 self.out_z = FPNumOut(width, False)
1367
1368 def setup(self, m, in_z, in_mid):
1369 """ links module to inputs and outputs
1370 """
1371 self.mod.setup(m, in_z)
1372 if self.in_mid is not None:
1373 m.d.comb += self.in_mid.eq(in_mid)
1374
1375 def action(self, m):
1376 self.idsync(m)
1377 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1378 m.next = "pack_put_z"
1379
1380
1381 class FPPutZ(FPState):
1382
1383 def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1384 FPState.__init__(self, state)
1385 if to_state is None:
1386 to_state = "get_ops"
1387 self.to_state = to_state
1388 self.in_z = in_z
1389 self.out_z = out_z
1390 self.in_mid = in_mid
1391 self.out_mid = out_mid
1392
1393 def action(self, m):
1394 if self.in_mid is not None:
1395 m.d.sync += self.out_mid.eq(self.in_mid)
1396 m.d.sync += [
1397 self.out_z.v.eq(self.in_z.v)
1398 ]
1399 with m.If(self.out_z.stb & self.out_z.ack):
1400 m.d.sync += self.out_z.stb.eq(0)
1401 m.next = self.to_state
1402 with m.Else():
1403 m.d.sync += self.out_z.stb.eq(1)
1404
1405
1406 class FPPutZIdx(FPState):
1407
1408 def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1409 FPState.__init__(self, state)
1410 if to_state is None:
1411 to_state = "get_ops"
1412 self.to_state = to_state
1413 self.in_z = in_z
1414 self.out_zs = out_zs
1415 self.in_mid = in_mid
1416
1417 def action(self, m):
1418 outz_stb = Signal(reset_less=True)
1419 outz_ack = Signal(reset_less=True)
1420 m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1421 outz_ack.eq(self.out_zs[self.in_mid].ack),
1422 ]
1423 m.d.sync += [
1424 self.out_zs[self.in_mid].v.eq(self.in_z.v)
1425 ]
1426 with m.If(outz_stb & outz_ack):
1427 m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1428 m.next = self.to_state
1429 with m.Else():
1430 m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1431
1432
1433 class FPADDBaseMod(FPID):
1434
1435 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1436 """ IEEE754 FP Add
1437
1438 * width: bit-width of IEEE754. supported: 16, 32, 64
1439 * id_wid: an identifier that is sync-connected to the input
1440 * single_cycle: True indicates each stage to complete in 1 clock
1441 * compact: True indicates a reduced number of stages
1442 """
1443 FPID.__init__(self, id_wid)
1444 self.width = width
1445 self.single_cycle = single_cycle
1446 self.compact = compact
1447
1448 self.in_t = Trigger()
1449 self.in_a = Signal(width)
1450 self.in_b = Signal(width)
1451 self.out_z = FPOp(width)
1452
1453 self.states = []
1454
1455 def add_state(self, state):
1456 self.states.append(state)
1457 return state
1458
1459 def get_fragment(self, platform=None):
1460 """ creates the HDL code-fragment for FPAdd
1461 """
1462 m = Module()
1463 m.submodules.out_z = self.out_z
1464 m.submodules.in_t = self.in_t
1465 if self.compact:
1466 self.get_compact_fragment(m, platform)
1467 else:
1468 self.get_longer_fragment(m, platform)
1469
1470 with m.FSM() as fsm:
1471
1472 for state in self.states:
1473 with m.State(state.state_from):
1474 state.action(m)
1475
1476 return m
1477
1478 def get_longer_fragment(self, m, platform=None):
1479
1480 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1481 self.in_a, self.in_b, self.width))
1482 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1483 a = get.out_op1
1484 b = get.out_op2
1485
1486 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1487 sc.setup(m, a, b, self.in_mid)
1488
1489 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1490 dn.setup(m, a, b, sc.in_mid)
1491
1492 if self.single_cycle:
1493 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1494 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1495 else:
1496 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1497 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1498
1499 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1500 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1501
1502 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1503 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1504
1505 if self.single_cycle:
1506 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1507 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1508 else:
1509 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1510 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1511
1512 rn = self.add_state(FPRound(self.width, self.id_wid))
1513 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1514
1515 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1516 cor.setup(m, rn.out_z, rn.in_mid)
1517
1518 pa = self.add_state(FPPack(self.width, self.id_wid))
1519 pa.setup(m, cor.out_z, rn.in_mid)
1520
1521 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1522 pa.in_mid, self.out_mid))
1523
1524 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1525 pa.in_mid, self.out_mid))
1526
1527 def get_compact_fragment(self, m, platform=None):
1528
1529 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1530 self.in_a, self.in_b, self.width))
1531 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1532 a = get.out_op1
1533 b = get.out_op2
1534
1535 sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1536 sc.setup(m, a, b, self.in_mid)
1537
1538 alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1539 alm.setup(m, sc.o.a, sc.o.b, sc.in_mid)
1540
1541 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1542 n1.setup(m, alm.out_z, alm.out_of, alm.in_mid)
1543
1544 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
1545 n1.in_mid, self.out_mid))
1546
1547 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1548 sc.in_mid, self.out_mid))
1549
1550
1551 class FPADDBase(FPState, FPID):
1552
1553 def __init__(self, width, id_wid=None, single_cycle=False):
1554 """ IEEE754 FP Add
1555
1556 * width: bit-width of IEEE754. supported: 16, 32, 64
1557 * id_wid: an identifier that is sync-connected to the input
1558 * single_cycle: True indicates each stage to complete in 1 clock
1559 """
1560 FPID.__init__(self, id_wid)
1561 FPState.__init__(self, "fpadd")
1562 self.width = width
1563 self.single_cycle = single_cycle
1564 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1565
1566 self.in_t = Trigger()
1567 self.in_a = Signal(width)
1568 self.in_b = Signal(width)
1569 #self.out_z = FPOp(width)
1570
1571 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1572 self.in_accept = Signal(reset_less=True)
1573 self.add_stb = Signal(reset_less=True)
1574 self.add_ack = Signal(reset=0, reset_less=True)
1575
1576 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1577 self.out_z = out_z
1578 self.out_mid = out_mid
1579 m.d.comb += [self.in_a.eq(a),
1580 self.in_b.eq(b),
1581 self.mod.in_a.eq(self.in_a),
1582 self.mod.in_b.eq(self.in_b),
1583 self.in_mid.eq(in_mid),
1584 self.mod.in_mid.eq(self.in_mid),
1585 self.z_done.eq(self.mod.out_z.trigger),
1586 #self.add_stb.eq(add_stb),
1587 self.mod.in_t.stb.eq(self.in_t.stb),
1588 self.in_t.ack.eq(self.mod.in_t.ack),
1589 self.out_mid.eq(self.mod.out_mid),
1590 self.out_z.v.eq(self.mod.out_z.v),
1591 self.out_z.stb.eq(self.mod.out_z.stb),
1592 self.mod.out_z.ack.eq(self.out_z.ack),
1593 ]
1594
1595 m.d.sync += self.add_stb.eq(add_stb)
1596 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1597 m.d.sync += self.out_z.ack.eq(0) # likewise
1598 #m.d.sync += self.in_t.stb.eq(0)
1599
1600 m.submodules.fpadd = self.mod
1601
1602 def action(self, m):
1603
1604 # in_accept is set on incoming strobe HIGH and ack LOW.
1605 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1606
1607 #with m.If(self.in_t.ack):
1608 # m.d.sync += self.in_t.stb.eq(0)
1609 with m.If(~self.z_done):
1610 # not done: test for accepting an incoming operand pair
1611 with m.If(self.in_accept):
1612 m.d.sync += [
1613 self.add_ack.eq(1), # acknowledge receipt...
1614 self.in_t.stb.eq(1), # initiate add
1615 ]
1616 with m.Else():
1617 m.d.sync += [self.add_ack.eq(0),
1618 self.in_t.stb.eq(0),
1619 self.out_z.ack.eq(1),
1620 ]
1621 with m.Else():
1622 # done: acknowledge, and write out id and value
1623 m.d.sync += [self.add_ack.eq(1),
1624 self.in_t.stb.eq(0)
1625 ]
1626 m.next = "put_z"
1627
1628 return
1629
1630 if self.in_mid is not None:
1631 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1632
1633 m.d.sync += [
1634 self.out_z.v.eq(self.mod.out_z.v)
1635 ]
1636 # move to output state on detecting z ack
1637 with m.If(self.out_z.trigger):
1638 m.d.sync += self.out_z.stb.eq(0)
1639 m.next = "put_z"
1640 with m.Else():
1641 m.d.sync += self.out_z.stb.eq(1)
1642
1643 class ResArray:
1644 def __init__(self, width, id_wid):
1645 self.width = width
1646 self.id_wid = id_wid
1647 res = []
1648 for i in range(rs_sz):
1649 out_z = FPOp(width)
1650 out_z.name = "out_z_%d" % i
1651 res.append(out_z)
1652 self.res = Array(res)
1653 self.in_z = FPOp(width)
1654 self.in_mid = Signal(self.id_wid, reset_less=True)
1655
1656 def setup(self, m, in_z, in_mid):
1657 m.d.comb += [self.in_z.eq(in_z),
1658 self.in_mid.eq(in_mid)]
1659
1660 def get_fragment(self, platform=None):
1661 """ creates the HDL code-fragment for FPAdd
1662 """
1663 m = Module()
1664 m.submodules.res_in_z = self.in_z
1665 m.submodules += self.res
1666
1667 return m
1668
1669 def ports(self):
1670 res = []
1671 for z in self.res:
1672 res += z.ports()
1673 return res
1674
1675
1676 class FPADD(FPID):
1677 """ FPADD: stages as follows:
1678
1679 FPGetOp (a)
1680 |
1681 FPGetOp (b)
1682 |
1683 FPAddBase---> FPAddBaseMod
1684 | |
1685 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1686
1687 FPAddBase is tricky: it is both a stage and *has* stages.
1688 Connection to FPAddBaseMod therefore requires an in stb/ack
1689 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1690 needs to be the thing that raises the incoming stb.
1691 """
1692
1693 def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1694 """ IEEE754 FP Add
1695
1696 * width: bit-width of IEEE754. supported: 16, 32, 64
1697 * id_wid: an identifier that is sync-connected to the input
1698 * single_cycle: True indicates each stage to complete in 1 clock
1699 """
1700 self.width = width
1701 self.id_wid = id_wid
1702 self.single_cycle = single_cycle
1703
1704 #self.out_z = FPOp(width)
1705 self.ids = FPID(id_wid)
1706
1707 rs = []
1708 for i in range(rs_sz):
1709 in_a = FPOp(width)
1710 in_b = FPOp(width)
1711 in_a.name = "in_a_%d" % i
1712 in_b.name = "in_b_%d" % i
1713 rs.append((in_a, in_b))
1714 self.rs = Array(rs)
1715
1716 res = []
1717 for i in range(rs_sz):
1718 out_z = FPOp(width)
1719 out_z.name = "out_z_%d" % i
1720 res.append(out_z)
1721 self.res = Array(res)
1722
1723 self.states = []
1724
1725 def add_state(self, state):
1726 self.states.append(state)
1727 return state
1728
1729 def get_fragment(self, platform=None):
1730 """ creates the HDL code-fragment for FPAdd
1731 """
1732 m = Module()
1733 m.submodules += self.rs
1734
1735 in_a = self.rs[0][0]
1736 in_b = self.rs[0][1]
1737
1738 out_z = FPOp(self.width)
1739 out_mid = Signal(self.id_wid, reset_less=True)
1740 m.submodules.out_z = out_z
1741
1742 geta = self.add_state(FPGetOp("get_a", "get_b",
1743 in_a, self.width))
1744 geta.setup(m, in_a)
1745 a = geta.out_op
1746
1747 getb = self.add_state(FPGetOp("get_b", "fpadd",
1748 in_b, self.width))
1749 getb.setup(m, in_b)
1750 b = getb.out_op
1751
1752 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1753 ab = self.add_state(ab)
1754 ab.setup(m, a, b, getb.out_decode, self.ids.in_mid,
1755 out_z, out_mid)
1756
1757 pz = self.add_state(FPPutZIdx("put_z", ab.out_z, self.res,
1758 out_mid, "get_a"))
1759
1760 with m.FSM() as fsm:
1761
1762 for state in self.states:
1763 with m.State(state.state_from):
1764 state.action(m)
1765
1766 return m
1767
1768
1769 if __name__ == "__main__":
1770 if True:
1771 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1772 main(alu, ports=alu.rs[0][0].ports() + \
1773 alu.rs[0][1].ports() + \
1774 alu.res[0].ports() + \
1775 [alu.ids.in_mid, alu.ids.out_mid])
1776 else:
1777 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1778 main(alu, ports=[alu.in_a, alu.in_b] + \
1779 alu.in_t.ports() + \
1780 alu.out_z.ports() + \
1781 [alu.in_mid, alu.out_mid])
1782
1783
1784 # works... but don't use, just do "python fname.py convert -t v"
1785 #print (verilog.convert(alu, ports=[
1786 # ports=alu.in_a.ports() + \
1787 # alu.in_b.ports() + \
1788 # alu.out_z.ports())