src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux, Array, Const
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8 from math import log
   9
  10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  11 from fpbase import MultiShiftRMerge, Trigger
  12 from example_buf_pipe import StageChain
  13 #from fpbase import FPNumShiftMultiRight
  14
  15
  16 class FPState(FPBase):
  17     def __init__(self, state_from):
  18         self.state_from = state_from
  19
  20     def set_inputs(self, inputs):
  21         self.inputs = inputs
  22         for k,v in inputs.items():
  23             setattr(self, k, v)
  24
  25     def set_outputs(self, outputs):
  26         self.outputs = outputs
  27         for k,v in outputs.items():
  28             setattr(self, k, v)
  29
  30
  31 class FPGetSyncOpsMod:
  32     def __init__(self, width, num_ops=2):
  33         self.width = width
  34         self.num_ops = num_ops
  35         inops = []
  36         outops = []
  37         for i in range(num_ops):
  38             inops.append(Signal(width, reset_less=True))
  39             outops.append(Signal(width, reset_less=True))
  40         self.in_op = inops
  41         self.out_op = outops
  42         self.stb = Signal(num_ops)
  43         self.ack = Signal()
  44         self.ready = Signal(reset_less=True)
  45         self.out_decode = Signal(reset_less=True)
  46
  47     def elaborate(self, platform):
  48         m = Module()
  49         m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
  50         m.d.comb += self.out_decode.eq(self.ack & self.ready)
  51         with m.If(self.out_decode):
  52             for i in range(self.num_ops):
  53                 m.d.comb += [
  54                         self.out_op[i].eq(self.in_op[i]),
  55                 ]
  56         return m
  57
  58     def ports(self):
  59         return self.in_op + self.out_op + [self.stb, self.ack]
  60
  61
  62 class FPOps(Trigger):
  63     def __init__(self, width, num_ops):
  64         Trigger.__init__(self)
  65         self.width = width
  66         self.num_ops = num_ops
  67
  68         res = []
  69         for i in range(num_ops):
  70             res.append(Signal(width))
  71         self.v  = Array(res)
  72
  73     def ports(self):
  74         res = []
  75         for i in range(self.num_ops):
  76             res.append(self.v[i])
  77         res.append(self.ack)
  78         res.append(self.stb)
  79         return res
  80
  81
  82 class InputGroup:
  83     def __init__(self, width, num_ops=2, num_rows=4):
  84         self.width = width
  85         self.num_ops = num_ops
  86         self.num_rows = num_rows
  87         self.mmax = int(log(self.num_rows) / log(2))
  88         self.rs = []
  89         self.mid = Signal(self.mmax, reset_less=True) # multiplex id
  90         for i in range(num_rows):
  91             self.rs.append(FPGetSyncOpsMod(width, num_ops))
  92         self.rs = Array(self.rs)
  93
  94         self.out_op = FPOps(width, num_ops)
  95
  96     def elaborate(self, platform):
  97         m = Module()
  98
  99         pe = PriorityEncoder(self.num_rows)
 100         m.submodules.selector = pe
 101         m.submodules.out_op = self.out_op
 102         m.submodules += self.rs
 103
 104         # connect priority encoder
 105         in_ready = []
 106         for i in range(self.num_rows):
 107             in_ready.append(self.rs[i].ready)
 108         m.d.comb += pe.i.eq(Cat(*in_ready))
 109
 110         active = Signal(reset_less=True)
 111         out_en = Signal(reset_less=True)
 112         m.d.comb += active.eq(~pe.n) # encoder active
 113         m.d.comb += out_en.eq(active & self.out_op.trigger)
 114
 115         # encoder active: ack relevant input, record MID, pass output
 116         with m.If(out_en):
 117             rs = self.rs[pe.o]
 118             m.d.sync += self.mid.eq(pe.o)
 119             m.d.sync += rs.ack.eq(0)
 120             m.d.sync += self.out_op.stb.eq(0)
 121             for j in range(self.num_ops):
 122                 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
 123         with m.Else():
 124             m.d.sync += self.out_op.stb.eq(1)
 125             # acks all default to zero
 126             for i in range(self.num_rows):
 127                 m.d.sync += self.rs[i].ack.eq(1)
 128
 129         return m
 130
 131     def ports(self):
 132         res = []
 133         for i in range(self.num_rows):
 134             inop = self.rs[i]
 135             res += inop.in_op + [inop.stb]
 136         return self.out_op.ports() + res + [self.mid]
 137
 138
 139 class FPGetOpMod:
 140     def __init__(self, width):
 141         self.in_op = FPOp(width)
 142         self.out_op = Signal(width)
 143         self.out_decode = Signal(reset_less=True)
 144
 145     def elaborate(self, platform):
 146         m = Module()
 147         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
 148         m.submodules.get_op_in = self.in_op
 149         #m.submodules.get_op_out = self.out_op
 150         with m.If(self.out_decode):
 151             m.d.comb += [
 152                 self.out_op.eq(self.in_op.v),
 153             ]
 154         return m
 155
 156
 157 class FPGetOp(FPState):
 158     """ gets operand
 159     """
 160
 161     def __init__(self, in_state, out_state, in_op, width):
 162         FPState.__init__(self, in_state)
 163         self.out_state = out_state
 164         self.mod = FPGetOpMod(width)
 165         self.in_op = in_op
 166         self.out_op = Signal(width)
 167         self.out_decode = Signal(reset_less=True)
 168
 169     def setup(self, m, in_op):
 170         """ links module to inputs and outputs
 171         """
 172         setattr(m.submodules, self.state_from, self.mod)
 173         m.d.comb += self.mod.in_op.eq(in_op)
 174         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 175
 176     def action(self, m):
 177         with m.If(self.out_decode):
 178             m.next = self.out_state
 179             m.d.sync += [
 180                 self.in_op.ack.eq(0),
 181                 self.out_op.eq(self.mod.out_op)
 182             ]
 183         with m.Else():
 184             m.d.sync += self.in_op.ack.eq(1)
 185
 186
 187 class FPGet2OpMod(Trigger):
 188     def __init__(self, width, id_wid):
 189         Trigger.__init__(self)
 190         self.width = width
 191         self.id_wid = id_wid
 192         self.i = self.ispec()
 193         self.o = self.ospec()
 194
 195     def ispec(self):
 196         return FPADDBaseData(self.width, self.id_wid)
 197
 198     def ospec(self):
 199         return FPNumBase2Ops(self.width, self.id_wid)
 200
 201     def elaborate(self, platform):
 202         m = Trigger.elaborate(self, platform)
 203         m.submodules.get_op1_out = self.o.a
 204         m.submodules.get_op2_out = self.o.b
 205         out_op1 = FPNumIn(None, self.width)
 206         out_op2 = FPNumIn(None, self.width)
 207         with m.If(self.trigger):
 208             m.d.comb += [
 209                 out_op1.decode(self.i.a),
 210                 out_op2.decode(self.i.b),
 211                 self.o.a.eq(out_op1),
 212                 self.o.b.eq(out_op2),
 213                 self.o.mid.eq(self.i.mid)
 214             ]
 215         return m
 216
 217
 218 class FPGet2Op(FPState):
 219     """ gets operands
 220     """
 221
 222     def __init__(self, in_state, out_state, width, id_wid):
 223         FPState.__init__(self, in_state)
 224         self.out_state = out_state
 225         self.mod = FPGet2OpMod(width, id_wid)
 226         self.o = self.mod.ospec()
 227         self.in_stb = Signal(reset_less=True)
 228         self.out_ack = Signal(reset_less=True)
 229         self.out_decode = Signal(reset_less=True)
 230
 231     def setup(self, m, i, in_stb, in_ack):
 232         """ links module to inputs and outputs
 233         """
 234         m.submodules.get_ops = self.mod
 235         m.d.comb += self.mod.i.eq(i)
 236         m.d.comb += self.mod.stb.eq(in_stb)
 237         m.d.comb += self.out_ack.eq(self.mod.ack)
 238         m.d.comb += self.out_decode.eq(self.mod.trigger)
 239         m.d.comb += in_ack.eq(self.mod.ack)
 240
 241     def action(self, m):
 242         with m.If(self.out_decode):
 243             m.next = self.out_state
 244             m.d.sync += [
 245                 self.mod.ack.eq(0),
 246                 self.o.eq(self.mod.o),
 247             ]
 248         with m.Else():
 249             m.d.sync += self.mod.ack.eq(1)
 250
 251
 252 class FPNumBase2Ops:
 253
 254     def __init__(self, width, id_wid, m_extra=True):
 255         self.a = FPNumBase(width, m_extra)
 256         self.b = FPNumBase(width, m_extra)
 257         self.mid = Signal(id_wid, reset_less=True)
 258
 259     def eq(self, i):
 260         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 261
 262
 263 class FPSCData:
 264
 265     def __init__(self, width, id_wid):
 266         self.out_do_z = Signal(reset_less=True)
 267         self.a = FPNumBase(width, True)
 268         self.b = FPNumBase(width, True)
 269         self.z = FPNumOut(width, False)
 270         self.mid = Signal(id_wid, reset_less=True)
 271
 272     def eq(self, i):
 273         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z),
 274                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 275
 276 class FPAddSpecialCasesMod:
 277     """ special cases: NaNs, infs, zeros, denormalised
 278         NOTE: some of these are unique to add.  see "Special Operations"
 279         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 280     """
 281
 282     def __init__(self, width, id_wid):
 283         self.width = width
 284         self.id_wid = id_wid
 285         self.i = self.ispec()
 286         self.o = self.ospec()
 287
 288     def ispec(self):
 289         return FPNumBase2Ops(self.width, self.id_wid)
 290
 291     def ospec(self):
 292         return FPSCData(self.width, self.id_wid)
 293
 294     def setup(self, m, i):
 295         """ links module to inputs and outputs
 296         """
 297         m.submodules.specialcases = self
 298         m.d.comb += self.i.eq(i)
 299
 300     def elaborate(self, platform):
 301         m = Module()
 302
 303         m.submodules.sc_in_a = self.i.a
 304         m.submodules.sc_in_b = self.i.b
 305         m.submodules.sc_out_z = self.o.z
 306
 307         s_nomatch = Signal()
 308         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
 309
 310         m_match = Signal()
 311         m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
 312
 313         # if a is NaN or b is NaN return NaN
 314         with m.If(self.i.a.is_nan | self.i.b.is_nan):
 315             m.d.comb += self.o.out_do_z.eq(1)
 316             m.d.comb += self.o.z.nan(0)
 317
 318         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 319         # under review
 320
 321         ## if a is zero and b is NaN return -b
 322         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 323         #    m.d.comb += self.o.out_do_z.eq(1)
 324         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 325
 326         ## if b is zero and a is NaN return -a
 327         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 328         #    m.d.comb += self.o.out_do_z.eq(1)
 329         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 330
 331         ## if a is -zero and b is NaN return -b
 332         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 333         #    m.d.comb += self.o.out_do_z.eq(1)
 334         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 335
 336         ## if b is -zero and a is NaN return -a
 337         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 338         #    m.d.comb += self.o.out_do_z.eq(1)
 339         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 340
 341         # if a is inf return inf (or NaN)
 342         with m.Elif(self.i.a.is_inf):
 343             m.d.comb += self.o.out_do_z.eq(1)
 344             m.d.comb += self.o.z.inf(self.i.a.s)
 345             # if a is inf and signs don't match return NaN
 346             with m.If(self.i.b.exp_128 & s_nomatch):
 347                 m.d.comb += self.o.z.nan(0)
 348
 349         # if b is inf return inf
 350         with m.Elif(self.i.b.is_inf):
 351             m.d.comb += self.o.out_do_z.eq(1)
 352             m.d.comb += self.o.z.inf(self.i.b.s)
 353
 354         # if a is zero and b zero return signed-a/b
 355         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
 356             m.d.comb += self.o.out_do_z.eq(1)
 357             m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
 358                                           self.i.b.e,
 359                                           self.i.b.m[3:-1])
 360
 361         # if a is zero return b
 362         with m.Elif(self.i.a.is_zero):
 363             m.d.comb += self.o.out_do_z.eq(1)
 364             m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
 365                                       self.i.b.m[3:-1])
 366
 367         # if b is zero return a
 368         with m.Elif(self.i.b.is_zero):
 369             m.d.comb += self.o.out_do_z.eq(1)
 370             m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
 371                                       self.i.a.m[3:-1])
 372
 373         # if a equal to -b return zero (+ve zero)
 374         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
 375             m.d.comb += self.o.out_do_z.eq(1)
 376             m.d.comb += self.o.z.zero(0)
 377
 378         # Denormalised Number checks next, so pass a/b data through
 379         with m.Else():
 380             m.d.comb += self.o.out_do_z.eq(0)
 381             m.d.comb += self.o.a.eq(self.i.a)
 382             m.d.comb += self.o.b.eq(self.i.b)
 383
 384         m.d.comb += self.o.mid.eq(self.i.mid)
 385
 386         return m
 387
 388
 389 class FPID:
 390     def __init__(self, id_wid):
 391         self.id_wid = id_wid
 392         if self.id_wid:
 393             self.in_mid = Signal(id_wid, reset_less=True)
 394             self.out_mid = Signal(id_wid, reset_less=True)
 395         else:
 396             self.in_mid = None
 397             self.out_mid = None
 398
 399     def idsync(self, m):
 400         if self.id_wid is not None:
 401             m.d.sync += self.out_mid.eq(self.in_mid)
 402
 403
 404 class FPAddSpecialCases(FPState):
 405     """ special cases: NaNs, infs, zeros, denormalised
 406         NOTE: some of these are unique to add.  see "Special Operations"
 407         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 408     """
 409
 410     def __init__(self, width, id_wid):
 411         FPState.__init__(self, "special_cases")
 412         self.mod = FPAddSpecialCasesMod(width)
 413         self.out_z = self.mod.ospec()
 414         self.out_do_z = Signal(reset_less=True)
 415
 416     def setup(self, m, i):
 417         """ links module to inputs and outputs
 418         """
 419         self.mod.setup(m, i, self.out_do_z)
 420         m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 421         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)  # (and mid)
 422
 423     def action(self, m):
 424         self.idsync(m)
 425         with m.If(self.out_do_z):
 426             m.next = "put_z"
 427         with m.Else():
 428             m.next = "denormalise"
 429
 430
 431 class FPAddSpecialCasesDeNorm(FPState):
 432     """ special cases: NaNs, infs, zeros, denormalised
 433         NOTE: some of these are unique to add.  see "Special Operations"
 434         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 435     """
 436
 437     def __init__(self, width, id_wid):
 438         FPState.__init__(self, "special_cases")
 439         self.smod = FPAddSpecialCasesMod(width, id_wid)
 440         self.out_z = self.smod.ospec()
 441         self.out_do_z = Signal(reset_less=True)
 442
 443         self.dmod = FPAddDeNormMod(width, id_wid)
 444         self.o = self.dmod.ospec()
 445
 446     def setup(self, m, i):
 447         """ links module to inputs and outputs
 448         """
 449         self.smod.setup(m, i)
 450         self.dmod.setup(m, self.smod.o)
 451         m.d.comb += self.out_do_z.eq(self.smod.o.out_do_z)
 452
 453         # out_do_z=True
 454         m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
 455         m.d.sync += self.out_z.mid.eq(self.smod.o.mid)  # (and mid)
 456         # out_do_z=False
 457         m.d.sync += self.o.eq(self.dmod.o)
 458
 459     def action(self, m):
 460         with m.If(self.out_do_z):
 461             m.next = "put_z"
 462         with m.Else():
 463             m.next = "align"
 464
 465
 466 class FPAddDeNormMod(FPState):
 467
 468     def __init__(self, width, id_wid):
 469         self.width = width
 470         self.id_wid = id_wid
 471         self.i = self.ispec()
 472         self.o = self.ospec()
 473
 474     def ispec(self):
 475         return FPNumBase2Ops(self.width, self.id_wid)
 476
 477     def ospec(self):
 478         return FPNumBase2Ops(self.width, self.id_wid)
 479
 480     def setup(self, m, i):
 481         """ links module to inputs and outputs
 482         """
 483         m.submodules.denormalise = self
 484         m.d.comb += self.i.eq(i)
 485
 486     def elaborate(self, platform):
 487         m = Module()
 488         m.submodules.denorm_in_a = self.i.a
 489         m.submodules.denorm_in_b = self.i.b
 490         m.submodules.denorm_out_a = self.o.a
 491         m.submodules.denorm_out_b = self.o.b
 492         # hmmm, don't like repeating identical code
 493         m.d.comb += self.o.a.eq(self.i.a)
 494         with m.If(self.i.a.exp_n127):
 495             m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
 496         with m.Else():
 497             m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 498
 499         m.d.comb += self.o.b.eq(self.i.b)
 500         with m.If(self.i.b.exp_n127):
 501             m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
 502         with m.Else():
 503             m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 504
 505         m.d.comb += self.o.mid.eq(self.i.mid)
 506
 507         return m
 508
 509
 510 class FPAddDeNorm(FPState):
 511
 512     def __init__(self, width, id_wid):
 513         FPState.__init__(self, "denormalise")
 514         self.mod = FPAddDeNormMod(width)
 515         self.out_a = FPNumBase(width)
 516         self.out_b = FPNumBase(width)
 517
 518     def setup(self, m, i):
 519         """ links module to inputs and outputs
 520         """
 521         self.mod.setup(m, i)
 522
 523         m.d.sync += self.out_a.eq(self.mod.out_a)
 524         m.d.sync += self.out_b.eq(self.mod.out_b)
 525
 526     def action(self, m):
 527         # Denormalised Number checks
 528         m.next = "align"
 529
 530
 531 class FPAddAlignMultiMod(FPState):
 532
 533     def __init__(self, width):
 534         self.in_a = FPNumBase(width)
 535         self.in_b = FPNumBase(width)
 536         self.out_a = FPNumIn(None, width)
 537         self.out_b = FPNumIn(None, width)
 538         self.exp_eq = Signal(reset_less=True)
 539
 540     def elaborate(self, platform):
 541         # This one however (single-cycle) will do the shift
 542         # in one go.
 543
 544         m = Module()
 545
 546         m.submodules.align_in_a = self.in_a
 547         m.submodules.align_in_b = self.in_b
 548         m.submodules.align_out_a = self.out_a
 549         m.submodules.align_out_b = self.out_b
 550
 551         # NOTE: this does *not* do single-cycle multi-shifting,
 552         #       it *STAYS* in the align state until exponents match
 553
 554         # exponent of a greater than b: shift b down
 555         m.d.comb += self.exp_eq.eq(0)
 556         m.d.comb += self.out_a.eq(self.in_a)
 557         m.d.comb += self.out_b.eq(self.in_b)
 558         agtb = Signal(reset_less=True)
 559         altb = Signal(reset_less=True)
 560         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 561         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 562         with m.If(agtb):
 563             m.d.comb += self.out_b.shift_down(self.in_b)
 564         # exponent of b greater than a: shift a down
 565         with m.Elif(altb):
 566             m.d.comb += self.out_a.shift_down(self.in_a)
 567         # exponents equal: move to next stage.
 568         with m.Else():
 569             m.d.comb += self.exp_eq.eq(1)
 570         return m
 571
 572
 573 class FPAddAlignMulti(FPState):
 574
 575     def __init__(self, width, id_wid):
 576         FPState.__init__(self, "align")
 577         self.mod = FPAddAlignMultiMod(width)
 578         self.out_a = FPNumIn(None, width)
 579         self.out_b = FPNumIn(None, width)
 580         self.exp_eq = Signal(reset_less=True)
 581
 582     def setup(self, m, in_a, in_b):
 583         """ links module to inputs and outputs
 584         """
 585         m.submodules.align = self.mod
 586         m.d.comb += self.mod.in_a.eq(in_a)
 587         m.d.comb += self.mod.in_b.eq(in_b)
 588         #m.d.comb += self.out_a.eq(self.mod.out_a)
 589         #m.d.comb += self.out_b.eq(self.mod.out_b)
 590         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 591         m.d.sync += self.out_a.eq(self.mod.out_a)
 592         m.d.sync += self.out_b.eq(self.mod.out_b)
 593
 594     def action(self, m):
 595         with m.If(self.exp_eq):
 596             m.next = "add_0"
 597
 598
 599 class FPNumIn2Ops:
 600
 601     def __init__(self, width, id_wid):
 602         self.a = FPNumIn(None, width)
 603         self.b = FPNumIn(None, width)
 604         self.mid = Signal(id_wid, reset_less=True)
 605
 606     def eq(self, i):
 607         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 608
 609
 610 class FPAddAlignSingleMod:
 611
 612     def __init__(self, width, id_wid):
 613         self.width = width
 614         self.id_wid = id_wid
 615         self.i = self.ispec()
 616         self.o = self.ospec()
 617
 618     def ispec(self):
 619         return FPNumBase2Ops(self.width, self.id_wid)
 620
 621     def ospec(self):
 622         return FPNumIn2Ops(self.width, self.id_wid)
 623
 624     def process(self, i):
 625         return self.o
 626
 627     def setup(self, m, i):
 628         """ links module to inputs and outputs
 629         """
 630         m.submodules.align = self
 631         m.d.comb += self.i.eq(i)
 632
 633     def elaborate(self, platform):
 634         """ Aligns A against B or B against A, depending on which has the
 635             greater exponent.  This is done in a *single* cycle using
 636             variable-width bit-shift
 637
 638             the shifter used here is quite expensive in terms of gates.
 639             Mux A or B in (and out) into temporaries, as only one of them
 640             needs to be aligned against the other
 641         """
 642         m = Module()
 643
 644         m.submodules.align_in_a = self.i.a
 645         m.submodules.align_in_b = self.i.b
 646         m.submodules.align_out_a = self.o.a
 647         m.submodules.align_out_b = self.o.b
 648
 649         # temporary (muxed) input and output to be shifted
 650         t_inp = FPNumBase(self.width)
 651         t_out = FPNumIn(None, self.width)
 652         espec = (len(self.i.a.e), True)
 653         msr = MultiShiftRMerge(self.i.a.m_width, espec)
 654         m.submodules.align_t_in = t_inp
 655         m.submodules.align_t_out = t_out
 656         m.submodules.multishift_r = msr
 657
 658         ediff = Signal(espec, reset_less=True)
 659         ediffr = Signal(espec, reset_less=True)
 660         tdiff = Signal(espec, reset_less=True)
 661         elz = Signal(reset_less=True)
 662         egz = Signal(reset_less=True)
 663
 664         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 665         m.d.comb += msr.inp.eq(t_inp.m)
 666         m.d.comb += msr.diff.eq(tdiff)
 667         m.d.comb += t_out.m.eq(msr.m)
 668         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 669         m.d.comb += t_out.s.eq(t_inp.s)
 670
 671         m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
 672         m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
 673         m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
 674         m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
 675
 676         # default: A-exp == B-exp, A and B untouched (fall through)
 677         m.d.comb += self.o.a.eq(self.i.a)
 678         m.d.comb += self.o.b.eq(self.i.b)
 679         # only one shifter (muxed)
 680         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 681         # exponent of a greater than b: shift b down
 682         with m.If(egz):
 683             m.d.comb += [t_inp.eq(self.i.b),
 684                          tdiff.eq(ediff),
 685                          self.o.b.eq(t_out),
 686                          self.o.b.s.eq(self.i.b.s), # whoops forgot sign
 687                         ]
 688         # exponent of b greater than a: shift a down
 689         with m.Elif(elz):
 690             m.d.comb += [t_inp.eq(self.i.a),
 691                          tdiff.eq(ediffr),
 692                          self.o.a.eq(t_out),
 693                          self.o.a.s.eq(self.i.a.s), # whoops forgot sign
 694                         ]
 695
 696         m.d.comb += self.o.mid.eq(self.i.mid)
 697
 698         return m
 699
 700
 701 class FPAddAlignSingle(FPState):
 702
 703     def __init__(self, width, id_wid):
 704         FPState.__init__(self, "align")
 705         self.mod = FPAddAlignSingleMod(width, id_wid)
 706         self.out_a = FPNumIn(None, width)
 707         self.out_b = FPNumIn(None, width)
 708
 709     def setup(self, m, i):
 710         """ links module to inputs and outputs
 711         """
 712         self.mod.setup(m, i)
 713
 714         # NOTE: could be done as comb
 715         m.d.sync += self.out_a.eq(self.mod.out_a)
 716         m.d.sync += self.out_b.eq(self.mod.out_b)
 717
 718     def action(self, m):
 719         m.next = "add_0"
 720
 721
 722 class FPAddAlignSingleAdd(FPState):
 723
 724     def __init__(self, width, id_wid):
 725         FPState.__init__(self, "align")
 726         self.width = width
 727         self.id_wid = id_wid
 728         self.a1o = self.ospec()
 729
 730     def ispec(self):
 731         return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
 732
 733     def ospec(self):
 734         return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
 735
 736     def setup(self, m, i):
 737         """ links module to inputs and outputs
 738         """
 739
 740         # chain AddAlignSingle, AddStage0 and AddStage1
 741         mod = FPAddAlignSingleMod(self.width, self.id_wid)
 742         a0mod = FPAddStage0Mod(self.width, self.id_wid)
 743         a1mod = FPAddStage1Mod(self.width, self.id_wid)
 744
 745         chain = StageChain([mod, a0mod, a1mod])
 746         chain.setup(m, i)
 747
 748         m.d.sync += self.a1o.eq(a1mod.o)
 749
 750     def action(self, m):
 751         m.next = "normalise_1"
 752
 753
 754 class FPAddStage0Data:
 755
 756     def __init__(self, width, id_wid):
 757         self.z = FPNumBase(width, False)
 758         self.tot = Signal(self.z.m_width + 4, reset_less=True)
 759         self.mid = Signal(id_wid, reset_less=True)
 760
 761     def eq(self, i):
 762         return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
 763
 764
 765 class FPAddStage0Mod:
 766
 767     def __init__(self, width, id_wid):
 768         self.width = width
 769         self.id_wid = id_wid
 770         self.i = self.ispec()
 771         self.o = self.ospec()
 772
 773     def ispec(self):
 774         return FPNumBase2Ops(self.width, self.id_wid)
 775
 776     def ospec(self):
 777         return FPAddStage0Data(self.width, self.id_wid)
 778
 779     def process(self, i):
 780         return self.o
 781
 782     def setup(self, m, i):
 783         """ links module to inputs and outputs
 784         """
 785         m.submodules.add0 = self
 786         m.d.comb += self.i.eq(i)
 787
 788     def elaborate(self, platform):
 789         m = Module()
 790         m.submodules.add0_in_a = self.i.a
 791         m.submodules.add0_in_b = self.i.b
 792         m.submodules.add0_out_z = self.o.z
 793
 794         m.d.comb += self.o.mid.eq(self.i.mid)
 795         m.d.comb += self.o.z.e.eq(self.i.a.e)
 796
 797         # store intermediate tests (and zero-extended mantissas)
 798         seq = Signal(reset_less=True)
 799         mge = Signal(reset_less=True)
 800         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
 801         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
 802         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
 803                      mge.eq(self.i.a.m >= self.i.b.m),
 804                      am0.eq(Cat(self.i.a.m, 0)),
 805                      bm0.eq(Cat(self.i.b.m, 0))
 806                     ]
 807         # same-sign (both negative or both positive) add mantissas
 808         with m.If(seq):
 809             m.d.comb += [
 810                 self.o.tot.eq(am0 + bm0),
 811                 self.o.z.s.eq(self.i.a.s)
 812             ]
 813         # a mantissa greater than b, use a
 814         with m.Elif(mge):
 815             m.d.comb += [
 816                 self.o.tot.eq(am0 - bm0),
 817                 self.o.z.s.eq(self.i.a.s)
 818             ]
 819         # b mantissa greater than a, use b
 820         with m.Else():
 821             m.d.comb += [
 822                 self.o.tot.eq(bm0 - am0),
 823                 self.o.z.s.eq(self.i.b.s)
 824         ]
 825         return m
 826
 827
 828 class FPAddStage0(FPState):
 829     """ First stage of add.  covers same-sign (add) and subtract
 830         special-casing when mantissas are greater or equal, to
 831         give greatest accuracy.
 832     """
 833
 834     def __init__(self, width, id_wid):
 835         FPState.__init__(self, "add_0")
 836         self.mod = FPAddStage0Mod(width)
 837         self.o = self.mod.ospec()
 838
 839     def setup(self, m, i):
 840         """ links module to inputs and outputs
 841         """
 842         self.mod.setup(m, i)
 843
 844         # NOTE: these could be done as combinatorial (merge add0+add1)
 845         m.d.sync += self.o.eq(self.mod.o)
 846
 847     def action(self, m):
 848         m.next = "add_1"
 849
 850
 851 class FPAddStage1Data:
 852
 853     def __init__(self, width, id_wid):
 854         self.z = FPNumBase(width, False)
 855         self.of = Overflow()
 856         self.mid = Signal(id_wid, reset_less=True)
 857
 858     def eq(self, i):
 859         return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
 860
 861
 862
 863 class FPAddStage1Mod(FPState):
 864     """ Second stage of add: preparation for normalisation.
 865         detects when tot sum is too big (tot[27] is kinda a carry bit)
 866     """
 867
 868     def __init__(self, width, id_wid):
 869         self.width = width
 870         self.id_wid = id_wid
 871         self.i = self.ispec()
 872         self.o = self.ospec()
 873
 874     def ispec(self):
 875         return FPAddStage0Data(self.width, self.id_wid)
 876
 877     def ospec(self):
 878         return FPAddStage1Data(self.width, self.id_wid)
 879
 880     def process(self, i):
 881         return self.o
 882
 883     def setup(self, m, i):
 884         """ links module to inputs and outputs
 885         """
 886         m.submodules.add1 = self
 887         m.submodules.add1_out_overflow = self.o.of
 888
 889         m.d.comb += self.i.eq(i)
 890
 891     def elaborate(self, platform):
 892         m = Module()
 893         #m.submodules.norm1_in_overflow = self.in_of
 894         #m.submodules.norm1_out_overflow = self.out_of
 895         #m.submodules.norm1_in_z = self.in_z
 896         #m.submodules.norm1_out_z = self.out_z
 897         m.d.comb += self.o.z.eq(self.i.z)
 898         m.d.comb += self.o.mid.eq(self.i.mid)
 899         # tot[-1] (MSB) gets set when the sum overflows. shift result down
 900         with m.If(self.i.tot[-1]):
 901             m.d.comb += [
 902                 self.o.z.m.eq(self.i.tot[4:]),
 903                 self.o.of.m0.eq(self.i.tot[4]),
 904                 self.o.of.guard.eq(self.i.tot[3]),
 905                 self.o.of.round_bit.eq(self.i.tot[2]),
 906                 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
 907                 self.o.z.e.eq(self.i.z.e + 1)
 908         ]
 909         # tot[-1] (MSB) zero case
 910         with m.Else():
 911             m.d.comb += [
 912                 self.o.z.m.eq(self.i.tot[3:]),
 913                 self.o.of.m0.eq(self.i.tot[3]),
 914                 self.o.of.guard.eq(self.i.tot[2]),
 915                 self.o.of.round_bit.eq(self.i.tot[1]),
 916                 self.o.of.sticky.eq(self.i.tot[0])
 917         ]
 918         return m
 919
 920
 921 class FPAddStage1(FPState):
 922
 923     def __init__(self, width, id_wid):
 924         FPState.__init__(self, "add_1")
 925         self.mod = FPAddStage1Mod(width)
 926         self.out_z = FPNumBase(width, False)
 927         self.out_of = Overflow()
 928         self.norm_stb = Signal()
 929
 930     def setup(self, m, i):
 931         """ links module to inputs and outputs
 932         """
 933         self.mod.setup(m, i)
 934
 935         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 936
 937         m.d.sync += self.out_of.eq(self.mod.out_of)
 938         m.d.sync += self.out_z.eq(self.mod.out_z)
 939         m.d.sync += self.norm_stb.eq(1)
 940
 941     def action(self, m):
 942         m.next = "normalise_1"
 943
 944
 945 class FPNormaliseModSingle:
 946
 947     def __init__(self, width):
 948         self.width = width
 949         self.in_z = self.ispec()
 950         self.out_z = self.ospec()
 951
 952     def ispec(self):
 953         return FPNumBase(self.width, False)
 954
 955     def ospec(self):
 956         return FPNumBase(self.width, False)
 957
 958     def setup(self, m, i):
 959         """ links module to inputs and outputs
 960         """
 961         m.submodules.normalise = self
 962         m.d.comb += self.i.eq(i)
 963
 964     def elaborate(self, platform):
 965         m = Module()
 966
 967         mwid = self.out_z.m_width+2
 968         pe = PriorityEncoder(mwid)
 969         m.submodules.norm_pe = pe
 970
 971         m.submodules.norm1_out_z = self.out_z
 972         m.submodules.norm1_in_z = self.in_z
 973
 974         in_z = FPNumBase(self.width, False)
 975         in_of = Overflow()
 976         m.submodules.norm1_insel_z = in_z
 977         m.submodules.norm1_insel_overflow = in_of
 978
 979         espec = (len(in_z.e), True)
 980         ediff_n126 = Signal(espec, reset_less=True)
 981         msr = MultiShiftRMerge(mwid, espec)
 982         m.submodules.multishift_r = msr
 983
 984         m.d.comb += in_z.eq(self.in_z)
 985         m.d.comb += in_of.eq(self.in_of)
 986         # initialise out from in (overridden below)
 987         m.d.comb += self.out_z.eq(in_z)
 988         m.d.comb += self.out_of.eq(in_of)
 989         # normalisation decrease condition
 990         decrease = Signal(reset_less=True)
 991         m.d.comb += decrease.eq(in_z.m_msbzero)
 992         # decrease exponent
 993         with m.If(decrease):
 994             # *sigh* not entirely obvious: count leading zeros (clz)
 995             # with a PriorityEncoder: to find from the MSB
 996             # we reverse the order of the bits.
 997             temp_m = Signal(mwid, reset_less=True)
 998             temp_s = Signal(mwid+1, reset_less=True)
 999             clz = Signal((len(in_z.e), True), reset_less=True)
1000             m.d.comb += [
1001                 # cat round and guard bits back into the mantissa
1002                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1003                 pe.i.eq(temp_m[::-1]),          # inverted
1004                 clz.eq(pe.o),                   # count zeros from MSB down
1005                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1006                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
1007                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
1008             ]
1009
1010         return m
1011
1012 class FPNorm1Data:
1013
1014     def __init__(self, width, id_wid):
1015         self.roundz = Signal(reset_less=True)
1016         self.z = FPNumBase(width, False)
1017         self.mid = Signal(id_wid, reset_less=True)
1018
1019     def eq(self, i):
1020         return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1021
1022
1023 class FPNorm1ModSingle:
1024
1025     def __init__(self, width, id_wid):
1026         self.width = width
1027         self.id_wid = id_wid
1028         self.i = self.ispec()
1029         self.o = self.ospec()
1030
1031     def ispec(self):
1032         return FPAddStage1Data(self.width, self.id_wid)
1033
1034     def ospec(self):
1035         return FPNorm1Data(self.width, self.id_wid)
1036
1037     def setup(self, m, i):
1038         """ links module to inputs and outputs
1039         """
1040         m.submodules.normalise_1 = self
1041         m.d.comb += self.i.eq(i)
1042
1043     def process(self, i):
1044         return self.o
1045
1046     def elaborate(self, platform):
1047         m = Module()
1048
1049         mwid = self.o.z.m_width+2
1050         pe = PriorityEncoder(mwid)
1051         m.submodules.norm_pe = pe
1052
1053         of = Overflow()
1054         m.d.comb += self.o.roundz.eq(of.roundz)
1055
1056         m.submodules.norm1_out_z = self.o.z
1057         m.submodules.norm1_out_overflow = of
1058         m.submodules.norm1_in_z = self.i.z
1059         m.submodules.norm1_in_overflow = self.i.of
1060
1061         i = self.ispec()
1062         m.submodules.norm1_insel_z = i.z
1063         m.submodules.norm1_insel_overflow = i.of
1064
1065         espec = (len(i.z.e), True)
1066         ediff_n126 = Signal(espec, reset_less=True)
1067         msr = MultiShiftRMerge(mwid, espec)
1068         m.submodules.multishift_r = msr
1069
1070         m.d.comb += i.eq(self.i)
1071         # initialise out from in (overridden below)
1072         m.d.comb += self.o.z.eq(i.z)
1073         m.d.comb += self.o.mid.eq(self.i.mid)
1074         m.d.comb += of.eq(i.of)
1075         # normalisation increase/decrease conditions
1076         decrease = Signal(reset_less=True)
1077         increase = Signal(reset_less=True)
1078         m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1079         m.d.comb += increase.eq(i.z.exp_lt_n126)
1080         # decrease exponent
1081         with m.If(decrease):
1082             # *sigh* not entirely obvious: count leading zeros (clz)
1083             # with a PriorityEncoder: to find from the MSB
1084             # we reverse the order of the bits.
1085             temp_m = Signal(mwid, reset_less=True)
1086             temp_s = Signal(mwid+1, reset_less=True)
1087             clz = Signal((len(i.z.e), True), reset_less=True)
1088             # make sure that the amount to decrease by does NOT
1089             # go below the minimum non-INF/NaN exponent
1090             limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1091                          i.z.exp_sub_n126)
1092             m.d.comb += [
1093                 # cat round and guard bits back into the mantissa
1094                 temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1095                 pe.i.eq(temp_m[::-1]),          # inverted
1096                 clz.eq(limclz),                 # count zeros from MSB down
1097                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1098                 self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
1099                 self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
1100                 of.m0.eq(temp_s[2]),          # copy of mantissa[0]
1101                 # overflow in bits 0..1: got shifted too (leave sticky)
1102                 of.guard.eq(temp_s[1]),       # guard
1103                 of.round_bit.eq(temp_s[0]),   # round
1104             ]
1105         # increase exponent
1106         with m.Elif(increase):
1107             temp_m = Signal(mwid+1, reset_less=True)
1108             m.d.comb += [
1109                 temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1110                               i.z.m)),
1111                 ediff_n126.eq(i.z.N126 - i.z.e),
1112                 # connect multi-shifter to inp/out mantissa (and ediff)
1113                 msr.inp.eq(temp_m),
1114                 msr.diff.eq(ediff_n126),
1115                 self.o.z.m.eq(msr.m[3:]),
1116                 of.m0.eq(temp_s[3]),   # copy of mantissa[0]
1117                 # overflow in bits 0..1: got shifted too (leave sticky)
1118                 of.guard.eq(temp_s[2]),     # guard
1119                 of.round_bit.eq(temp_s[1]), # round
1120                 of.sticky.eq(temp_s[0]),    # sticky
1121                 self.o.z.e.eq(i.z.e + ediff_n126),
1122             ]
1123
1124         return m
1125
1126
1127 class FPNorm1ModMulti:
1128
1129     def __init__(self, width, single_cycle=True):
1130         self.width = width
1131         self.in_select = Signal(reset_less=True)
1132         self.in_z = FPNumBase(width, False)
1133         self.in_of = Overflow()
1134         self.temp_z = FPNumBase(width, False)
1135         self.temp_of = Overflow()
1136         self.out_z = FPNumBase(width, False)
1137         self.out_of = Overflow()
1138
1139     def elaborate(self, platform):
1140         m = Module()
1141
1142         m.submodules.norm1_out_z = self.out_z
1143         m.submodules.norm1_out_overflow = self.out_of
1144         m.submodules.norm1_temp_z = self.temp_z
1145         m.submodules.norm1_temp_of = self.temp_of
1146         m.submodules.norm1_in_z = self.in_z
1147         m.submodules.norm1_in_overflow = self.in_of
1148
1149         in_z = FPNumBase(self.width, False)
1150         in_of = Overflow()
1151         m.submodules.norm1_insel_z = in_z
1152         m.submodules.norm1_insel_overflow = in_of
1153
1154         # select which of temp or in z/of to use
1155         with m.If(self.in_select):
1156             m.d.comb += in_z.eq(self.in_z)
1157             m.d.comb += in_of.eq(self.in_of)
1158         with m.Else():
1159             m.d.comb += in_z.eq(self.temp_z)
1160             m.d.comb += in_of.eq(self.temp_of)
1161         # initialise out from in (overridden below)
1162         m.d.comb += self.out_z.eq(in_z)
1163         m.d.comb += self.out_of.eq(in_of)
1164         # normalisation increase/decrease conditions
1165         decrease = Signal(reset_less=True)
1166         increase = Signal(reset_less=True)
1167         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1168         m.d.comb += increase.eq(in_z.exp_lt_n126)
1169         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1170         # decrease exponent
1171         with m.If(decrease):
1172             m.d.comb += [
1173                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
1174                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1175                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1176                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1177                 self.out_of.round_bit.eq(0),        # reset round bit
1178                 self.out_of.m0.eq(in_of.guard),
1179             ]
1180         # increase exponent
1181         with m.Elif(increase):
1182             m.d.comb += [
1183                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
1184                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1185                 self.out_of.guard.eq(in_z.m[0]),
1186                 self.out_of.m0.eq(in_z.m[1]),
1187                 self.out_of.round_bit.eq(in_of.guard),
1188                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1189             ]
1190
1191         return m
1192
1193
1194 class FPNorm1Single(FPState):
1195
1196     def __init__(self, width, id_wid, single_cycle=True):
1197         FPState.__init__(self, "normalise_1")
1198         self.mod = FPNorm1ModSingle(width)
1199         self.o = self.ospec()
1200         self.out_z = FPNumBase(width, False)
1201         self.out_roundz = Signal(reset_less=True)
1202
1203     def ispec(self):
1204         return self.mod.ispec()
1205
1206     def ospec(self):
1207         return self.mod.ospec()
1208
1209     def setup(self, m, i):
1210         """ links module to inputs and outputs
1211         """
1212         self.mod.setup(m, i)
1213
1214     def action(self, m):
1215         m.next = "round"
1216
1217
1218 class FPNorm1Multi(FPState):
1219
1220     def __init__(self, width, id_wid):
1221         FPState.__init__(self, "normalise_1")
1222         self.mod = FPNorm1ModMulti(width)
1223         self.stb = Signal(reset_less=True)
1224         self.ack = Signal(reset=0, reset_less=True)
1225         self.out_norm = Signal(reset_less=True)
1226         self.in_accept = Signal(reset_less=True)
1227         self.temp_z = FPNumBase(width)
1228         self.temp_of = Overflow()
1229         self.out_z = FPNumBase(width)
1230         self.out_roundz = Signal(reset_less=True)
1231
1232     def setup(self, m, in_z, in_of, norm_stb):
1233         """ links module to inputs and outputs
1234         """
1235         self.mod.setup(m, in_z, in_of, norm_stb,
1236                        self.in_accept, self.temp_z, self.temp_of,
1237                        self.out_z, self.out_norm)
1238
1239         m.d.comb += self.stb.eq(norm_stb)
1240         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1241
1242     def action(self, m):
1243         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1244         m.d.sync += self.temp_of.eq(self.mod.out_of)
1245         m.d.sync += self.temp_z.eq(self.out_z)
1246         with m.If(self.out_norm):
1247             with m.If(self.in_accept):
1248                 m.d.sync += [
1249                     self.ack.eq(1),
1250                 ]
1251             with m.Else():
1252                 m.d.sync += self.ack.eq(0)
1253         with m.Else():
1254             # normalisation not required (or done).
1255             m.next = "round"
1256             m.d.sync += self.ack.eq(1)
1257             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1258
1259
1260 class FPNormToPack(FPState):
1261
1262     def __init__(self, width, id_wid):
1263         FPState.__init__(self, "normalise_1")
1264         self.id_wid = id_wid
1265         self.width = width
1266
1267     def ispec(self):
1268         return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
1269
1270     def ospec(self):
1271         return FPPackData(self.width, self.id_wid) # FPPackMod ospec
1272
1273     def setup(self, m, i):
1274         """ links module to inputs and outputs
1275         """
1276
1277         # Normalisation, Rounding Corrections, Pack - in a chain
1278         nmod = FPNorm1ModSingle(self.width, self.id_wid)
1279         rmod = FPRoundMod(self.width, self.id_wid)
1280         cmod = FPCorrectionsMod(self.width, self.id_wid)
1281         pmod = FPPackMod(self.width, self.id_wid)
1282         chain = StageChain([nmod, rmod, cmod, pmod])
1283         chain.setup(m, i)
1284         self.out_z = pmod.ospec()
1285
1286         m.d.sync += self.out_z.mid.eq(pmod.o.mid)
1287         m.d.sync += self.out_z.z.v.eq(pmod.o.z.v) # outputs packed result
1288
1289     def action(self, m):
1290         m.next = "pack_put_z"
1291
1292
1293 class FPRoundData:
1294
1295     def __init__(self, width, id_wid):
1296         self.z = FPNumBase(width, False)
1297         self.mid = Signal(id_wid, reset_less=True)
1298
1299     def eq(self, i):
1300         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1301
1302
1303 class FPRoundMod:
1304
1305     def __init__(self, width, id_wid):
1306         self.width = width
1307         self.id_wid = id_wid
1308         self.i = self.ispec()
1309         self.out_z = self.ospec()
1310
1311     def ispec(self):
1312         return FPNorm1Data(self.width, self.id_wid)
1313
1314     def ospec(self):
1315         return FPRoundData(self.width, self.id_wid)
1316
1317     def process(self, i):
1318         return self.out_z
1319
1320     def setup(self, m, i):
1321         m.submodules.roundz = self
1322         m.d.comb += self.i.eq(i)
1323
1324     def elaborate(self, platform):
1325         m = Module()
1326         m.d.comb += self.out_z.eq(self.i)
1327         with m.If(self.i.roundz):
1328             m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
1329             with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1330                 m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1331         return m
1332
1333
1334 class FPRound(FPState):
1335
1336     def __init__(self, width, id_wid):
1337         FPState.__init__(self, "round")
1338         self.mod = FPRoundMod(width)
1339         self.out_z = self.ospec()
1340
1341     def ispec(self):
1342         return self.mod.ispec()
1343
1344     def ospec(self):
1345         return self.mod.ospec()
1346
1347     def setup(self, m, i):
1348         """ links module to inputs and outputs
1349         """
1350         self.mod.setup(m, i)
1351
1352         self.idsync(m)
1353         m.d.sync += self.out_z.eq(self.mod.out_z)
1354         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1355
1356     def action(self, m):
1357         m.next = "corrections"
1358
1359
1360 class FPCorrectionsMod:
1361
1362     def __init__(self, width, id_wid):
1363         self.width = width
1364         self.id_wid = id_wid
1365         self.i = self.ispec()
1366         self.out_z = self.ospec()
1367
1368     def ispec(self):
1369         return FPRoundData(self.width, self.id_wid)
1370
1371     def ospec(self):
1372         return FPRoundData(self.width, self.id_wid)
1373
1374     def process(self, i):
1375         return self.out_z
1376
1377     def setup(self, m, i):
1378         """ links module to inputs and outputs
1379         """
1380         m.submodules.corrections = self
1381         m.d.comb += self.i.eq(i)
1382
1383     def elaborate(self, platform):
1384         m = Module()
1385         m.submodules.corr_in_z = self.i.z
1386         m.submodules.corr_out_z = self.out_z.z
1387         m.d.comb += self.out_z.eq(self.i)
1388         with m.If(self.i.z.is_denormalised):
1389             m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
1390         return m
1391
1392
1393 class FPCorrections(FPState):
1394
1395     def __init__(self, width, id_wid):
1396         FPState.__init__(self, "corrections")
1397         self.mod = FPCorrectionsMod(width)
1398         self.out_z = self.ospec()
1399
1400     def ispec(self):
1401         return self.mod.ispec()
1402
1403     def ospec(self):
1404         return self.mod.ospec()
1405
1406     def setup(self, m, in_z):
1407         """ links module to inputs and outputs
1408         """
1409         self.mod.setup(m, in_z)
1410
1411         m.d.sync += self.out_z.eq(self.mod.out_z)
1412         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1413
1414     def action(self, m):
1415         m.next = "pack"
1416
1417
1418 class FPPackData:
1419
1420     def __init__(self, width, id_wid):
1421         self.z = FPNumOut(width, False)
1422         self.mid = Signal(id_wid, reset_less=True)
1423
1424     def eq(self, i):
1425         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1426
1427
1428 class FPPackMod:
1429
1430     def __init__(self, width, id_wid):
1431         self.width = width
1432         self.id_wid = id_wid
1433         self.i = self.ispec()
1434         self.o = self.ospec()
1435
1436     def ispec(self):
1437         return FPRoundData(self.width, self.id_wid)
1438
1439     def ospec(self):
1440         return FPPackData(self.width, self.id_wid)
1441
1442     def process(self, i):
1443         return self.o
1444
1445     def setup(self, m, in_z):
1446         """ links module to inputs and outputs
1447         """
1448         m.submodules.pack = self
1449         m.d.comb += self.i.eq(in_z)
1450
1451     def elaborate(self, platform):
1452         m = Module()
1453         m.submodules.pack_in_z = self.i.z
1454         m.d.comb += self.o.mid.eq(self.i.mid)
1455         with m.If(self.i.z.is_overflowed):
1456             m.d.comb += self.o.z.inf(self.i.z.s)
1457         with m.Else():
1458             m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1459         return m
1460
1461
1462 class FPPackData:
1463     def __init__(self, width, id_wid):
1464         self.z = FPNumOut(width, False)
1465         self.mid = Signal(id_wid, reset_less=True)
1466
1467     def eq(self, i):
1468         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1469
1470
1471 class FPPack(FPState):
1472
1473     def __init__(self, width, id_wid):
1474         FPState.__init__(self, "pack")
1475         self.mod = FPPackMod(width)
1476         self.out_z = self.ospec()
1477
1478     def ispec(self):
1479         return self.mod.ispec()
1480
1481     def ospec(self):
1482         return self.mod.ospec()
1483
1484     def setup(self, m, in_z):
1485         """ links module to inputs and outputs
1486         """
1487         self.mod.setup(m, in_z)
1488
1489         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1490         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1491
1492     def action(self, m):
1493         m.next = "pack_put_z"
1494
1495
1496 class FPPutZ(FPState):
1497
1498     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1499         FPState.__init__(self, state)
1500         if to_state is None:
1501             to_state = "get_ops"
1502         self.to_state = to_state
1503         self.in_z = in_z
1504         self.out_z = out_z
1505         self.in_mid = in_mid
1506         self.out_mid = out_mid
1507
1508     def action(self, m):
1509         if self.in_mid is not None:
1510             m.d.sync += self.out_mid.eq(self.in_mid)
1511         m.d.sync += [
1512           self.out_z.z.v.eq(self.in_z.v)
1513         ]
1514         with m.If(self.out_z.z.stb & self.out_z.z.ack):
1515             m.d.sync += self.out_z.z.stb.eq(0)
1516             m.next = self.to_state
1517         with m.Else():
1518             m.d.sync += self.out_z.z.stb.eq(1)
1519
1520
1521 class FPPutZIdx(FPState):
1522
1523     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1524         FPState.__init__(self, state)
1525         if to_state is None:
1526             to_state = "get_ops"
1527         self.to_state = to_state
1528         self.in_z = in_z
1529         self.out_zs = out_zs
1530         self.in_mid = in_mid
1531
1532     def action(self, m):
1533         outz_stb = Signal(reset_less=True)
1534         outz_ack = Signal(reset_less=True)
1535         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1536                      outz_ack.eq(self.out_zs[self.in_mid].ack),
1537                     ]
1538         m.d.sync += [
1539           self.out_zs[self.in_mid].v.eq(self.in_z.v)
1540         ]
1541         with m.If(outz_stb & outz_ack):
1542             m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1543             m.next = self.to_state
1544         with m.Else():
1545             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1546
1547 class FPADDBaseData:
1548
1549     def __init__(self, width, id_wid):
1550         self.width = width
1551         self.id_wid = id_wid
1552         self.a  = Signal(width)
1553         self.b  = Signal(width)
1554         self.mid = Signal(id_wid, reset_less=True)
1555
1556     def eq(self, i):
1557         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1558
1559
1560 class FPOpData:
1561     def __init__(self, width, id_wid):
1562         self.z = FPOp(width)
1563         self.mid = Signal(id_wid, reset_less=True)
1564
1565     def eq(self, i):
1566         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1567
1568
1569 class FPADDBaseMod:
1570
1571     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1572         """ IEEE754 FP Add
1573
1574             * width: bit-width of IEEE754.  supported: 16, 32, 64
1575             * id_wid: an identifier that is sync-connected to the input
1576             * single_cycle: True indicates each stage to complete in 1 clock
1577             * compact: True indicates a reduced number of stages
1578         """
1579         self.width = width
1580         self.id_wid = id_wid
1581         self.single_cycle = single_cycle
1582         self.compact = compact
1583
1584         self.in_t = Trigger()
1585         self.i = self.ispec()
1586         self.o = self.ospec()
1587
1588         self.states = []
1589
1590     def ispec(self):
1591         return FPADDBaseData(self.width, self.id_wid)
1592
1593     def ospec(self):
1594         return FPOpData(self.width, self.id_wid)
1595
1596     def add_state(self, state):
1597         self.states.append(state)
1598         return state
1599
1600     def get_fragment(self, platform=None):
1601         """ creates the HDL code-fragment for FPAdd
1602         """
1603         m = Module()
1604         m.submodules.out_z = self.o.z
1605         m.submodules.in_t = self.in_t
1606         if self.compact:
1607             self.get_compact_fragment(m, platform)
1608         else:
1609             self.get_longer_fragment(m, platform)
1610
1611         with m.FSM() as fsm:
1612
1613             for state in self.states:
1614                 with m.State(state.state_from):
1615                     state.action(m)
1616
1617         return m
1618
1619     def get_longer_fragment(self, m, platform=None):
1620
1621         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1622                                       self.width))
1623         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1624         a = get.out_op1
1625         b = get.out_op2
1626
1627         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1628         sc.setup(m, a, b, self.in_mid)
1629
1630         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1631         dn.setup(m, a, b, sc.in_mid)
1632
1633         if self.single_cycle:
1634             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1635             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1636         else:
1637             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1638             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1639
1640         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1641         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1642
1643         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1644         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1645
1646         if self.single_cycle:
1647             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1648             n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1649         else:
1650             n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1651             n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1652
1653         rn = self.add_state(FPRound(self.width, self.id_wid))
1654         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1655
1656         cor = self.add_state(FPCorrections(self.width, self.id_wid))
1657         cor.setup(m, rn.out_z, rn.in_mid)
1658
1659         pa = self.add_state(FPPack(self.width, self.id_wid))
1660         pa.setup(m, cor.out_z, rn.in_mid)
1661
1662         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1663                                     pa.in_mid, self.out_mid))
1664
1665         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1666                                     pa.in_mid, self.out_mid))
1667
1668     def get_compact_fragment(self, m, platform=None):
1669
1670         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1671                                       self.width, self.id_wid))
1672         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1673
1674         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1675         sc.setup(m, get.o)
1676
1677         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1678         alm.setup(m, sc.o)
1679
1680         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1681         n1.setup(m, alm.a1o)
1682
1683         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
1684                                     n1.out_z.mid, self.o.mid))
1685
1686         pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
1687                                     sc.o.mid, self.o.mid))
1688
1689
1690 class FPADDBase(FPState):
1691
1692     def __init__(self, width, id_wid=None, single_cycle=False):
1693         """ IEEE754 FP Add
1694
1695             * width: bit-width of IEEE754.  supported: 16, 32, 64
1696             * id_wid: an identifier that is sync-connected to the input
1697             * single_cycle: True indicates each stage to complete in 1 clock
1698         """
1699         FPState.__init__(self, "fpadd")
1700         self.width = width
1701         self.single_cycle = single_cycle
1702         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1703         self.o = self.ospec()
1704
1705         self.in_t = Trigger()
1706         self.i = self.ispec()
1707
1708         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1709         self.in_accept = Signal(reset_less=True)
1710         self.add_stb = Signal(reset_less=True)
1711         self.add_ack = Signal(reset=0, reset_less=True)
1712
1713     def ispec(self):
1714         return self.mod.ispec()
1715
1716     def ospec(self):
1717         return self.mod.ospec()
1718
1719     def setup(self, m, i, add_stb, in_mid):
1720         m.d.comb += [self.i.eq(i),
1721                      self.mod.i.eq(self.i),
1722                      self.z_done.eq(self.mod.o.z.trigger),
1723                      #self.add_stb.eq(add_stb),
1724                      self.mod.in_t.stb.eq(self.in_t.stb),
1725                      self.in_t.ack.eq(self.mod.in_t.ack),
1726                      self.o.mid.eq(self.mod.o.mid),
1727                      self.o.z.v.eq(self.mod.o.z.v),
1728                      self.o.z.stb.eq(self.mod.o.z.stb),
1729                      self.mod.o.z.ack.eq(self.o.z.ack),
1730                     ]
1731
1732         m.d.sync += self.add_stb.eq(add_stb)
1733         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1734         m.d.sync += self.o.z.ack.eq(0) # likewise
1735         #m.d.sync += self.in_t.stb.eq(0)
1736
1737         m.submodules.fpadd = self.mod
1738
1739     def action(self, m):
1740
1741         # in_accept is set on incoming strobe HIGH and ack LOW.
1742         m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1743
1744         #with m.If(self.in_t.ack):
1745         #    m.d.sync += self.in_t.stb.eq(0)
1746         with m.If(~self.z_done):
1747             # not done: test for accepting an incoming operand pair
1748             with m.If(self.in_accept):
1749                 m.d.sync += [
1750                     self.add_ack.eq(1), # acknowledge receipt...
1751                     self.in_t.stb.eq(1), # initiate add
1752                 ]
1753             with m.Else():
1754                 m.d.sync += [self.add_ack.eq(0),
1755                              self.in_t.stb.eq(0),
1756                              self.o.z.ack.eq(1),
1757                             ]
1758         with m.Else():
1759             # done: acknowledge, and write out id and value
1760             m.d.sync += [self.add_ack.eq(1),
1761                          self.in_t.stb.eq(0)
1762                         ]
1763             m.next = "put_z"
1764
1765             return
1766
1767             if self.in_mid is not None:
1768                 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1769
1770             m.d.sync += [
1771               self.out_z.v.eq(self.mod.out_z.v)
1772             ]
1773             # move to output state on detecting z ack
1774             with m.If(self.out_z.trigger):
1775                 m.d.sync += self.out_z.stb.eq(0)
1776                 m.next = "put_z"
1777             with m.Else():
1778                 m.d.sync += self.out_z.stb.eq(1)
1779
1780
1781 class ResArray:
1782     def __init__(self, width, id_wid):
1783         self.width = width
1784         self.id_wid = id_wid
1785         res = []
1786         for i in range(rs_sz):
1787             out_z = FPOp(width)
1788             out_z.name = "out_z_%d" % i
1789             res.append(out_z)
1790         self.res = Array(res)
1791         self.in_z = FPOp(width)
1792         self.in_mid = Signal(self.id_wid, reset_less=True)
1793
1794     def setup(self, m, in_z, in_mid):
1795         m.d.comb += [self.in_z.eq(in_z),
1796                      self.in_mid.eq(in_mid)]
1797
1798     def get_fragment(self, platform=None):
1799         """ creates the HDL code-fragment for FPAdd
1800         """
1801         m = Module()
1802         m.submodules.res_in_z = self.in_z
1803         m.submodules += self.res
1804
1805         return m
1806
1807     def ports(self):
1808         res = []
1809         for z in self.res:
1810             res += z.ports()
1811         return res
1812
1813
1814 class FPADD(FPID):
1815     """ FPADD: stages as follows:
1816
1817         FPGetOp (a)
1818            |
1819         FPGetOp (b)
1820            |
1821         FPAddBase---> FPAddBaseMod
1822            |            |
1823         PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1824
1825         FPAddBase is tricky: it is both a stage and *has* stages.
1826         Connection to FPAddBaseMod therefore requires an in stb/ack
1827         and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
1828         needs to be the thing that raises the incoming stb.
1829     """
1830
1831     def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1832         """ IEEE754 FP Add
1833
1834             * width: bit-width of IEEE754.  supported: 16, 32, 64
1835             * id_wid: an identifier that is sync-connected to the input
1836             * single_cycle: True indicates each stage to complete in 1 clock
1837         """
1838         self.width = width
1839         self.id_wid = id_wid
1840         self.single_cycle = single_cycle
1841
1842         #self.out_z = FPOp(width)
1843         self.ids = FPID(id_wid)
1844
1845         rs = []
1846         for i in range(rs_sz):
1847             in_a  = FPOp(width)
1848             in_b  = FPOp(width)
1849             in_a.name = "in_a_%d" % i
1850             in_b.name = "in_b_%d" % i
1851             rs.append((in_a, in_b))
1852         self.rs = Array(rs)
1853
1854         res = []
1855         for i in range(rs_sz):
1856             out_z = FPOp(width)
1857             out_z.name = "out_z_%d" % i
1858             res.append(out_z)
1859         self.res = Array(res)
1860
1861         self.states = []
1862
1863     def add_state(self, state):
1864         self.states.append(state)
1865         return state
1866
1867     def get_fragment(self, platform=None):
1868         """ creates the HDL code-fragment for FPAdd
1869         """
1870         m = Module()
1871         m.submodules += self.rs
1872
1873         in_a = self.rs[0][0]
1874         in_b = self.rs[0][1]
1875
1876         geta = self.add_state(FPGetOp("get_a", "get_b",
1877                                       in_a, self.width))
1878         geta.setup(m, in_a)
1879         a = geta.out_op
1880
1881         getb = self.add_state(FPGetOp("get_b", "fpadd",
1882                                       in_b, self.width))
1883         getb.setup(m, in_b)
1884         b = getb.out_op
1885
1886         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1887         ab = self.add_state(ab)
1888         abd = ab.ispec() # create an input spec object for FPADDBase
1889         m.d.sync += [abd.a.eq(a), abd.b.eq(b), abd.mid.eq(self.ids.in_mid)]
1890         ab.setup(m, abd, getb.out_decode, self.ids.in_mid)
1891         o = ab.o
1892
1893         pz = self.add_state(FPPutZIdx("put_z", o.z, self.res,
1894                                     o.mid, "get_a"))
1895
1896         with m.FSM() as fsm:
1897
1898             for state in self.states:
1899                 with m.State(state.state_from):
1900                     state.action(m)
1901
1902         return m
1903
1904
1905 if __name__ == "__main__":
1906     if True:
1907         alu = FPADD(width=32, id_wid=5, single_cycle=True)
1908         main(alu, ports=alu.rs[0][0].ports() + \
1909                         alu.rs[0][1].ports() + \
1910                         alu.res[0].ports() + \
1911                         [alu.ids.in_mid, alu.ids.out_mid])
1912     else:
1913         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1914         main(alu, ports=[alu.in_a, alu.in_b] + \
1915                         alu.in_t.ports() + \
1916                         alu.out_z.ports() + \
1917                         [alu.in_mid, alu.out_mid])
1918
1919
1920     # works... but don't use, just do "python fname.py convert -t v"
1921     #print (verilog.convert(alu, ports=[
1922     #                        ports=alu.in_a.ports() + \
1923     #                              alu.in_b.ports() + \
1924     #                              alu.out_z.ports())