src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat, Mux, Array, Const
   6 from nmigen.lib.coding import PriorityEncoder
   7 from nmigen.cli import main, verilog
   8 from math import log
   9
  10 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
  11 from fpbase import MultiShiftRMerge, Trigger
  12 from example_buf_pipe import StageChain
  13 #from fpbase import FPNumShiftMultiRight
  14
  15
  16 class FPState(FPBase):
  17     def __init__(self, state_from):
  18         self.state_from = state_from
  19
  20     def set_inputs(self, inputs):
  21         self.inputs = inputs
  22         for k,v in inputs.items():
  23             setattr(self, k, v)
  24
  25     def set_outputs(self, outputs):
  26         self.outputs = outputs
  27         for k,v in outputs.items():
  28             setattr(self, k, v)
  29
  30
  31 class FPGetSyncOpsMod:
  32     def __init__(self, width, num_ops=2):
  33         self.width = width
  34         self.num_ops = num_ops
  35         inops = []
  36         outops = []
  37         for i in range(num_ops):
  38             inops.append(Signal(width, reset_less=True))
  39             outops.append(Signal(width, reset_less=True))
  40         self.in_op = inops
  41         self.out_op = outops
  42         self.stb = Signal(num_ops)
  43         self.ack = Signal()
  44         self.ready = Signal(reset_less=True)
  45         self.out_decode = Signal(reset_less=True)
  46
  47     def elaborate(self, platform):
  48         m = Module()
  49         m.d.comb += self.ready.eq(self.stb == Const(-1, (self.num_ops, False)))
  50         m.d.comb += self.out_decode.eq(self.ack & self.ready)
  51         with m.If(self.out_decode):
  52             for i in range(self.num_ops):
  53                 m.d.comb += [
  54                         self.out_op[i].eq(self.in_op[i]),
  55                 ]
  56         return m
  57
  58     def ports(self):
  59         return self.in_op + self.out_op + [self.stb, self.ack]
  60
  61
  62 class FPOps(Trigger):
  63     def __init__(self, width, num_ops):
  64         Trigger.__init__(self)
  65         self.width = width
  66         self.num_ops = num_ops
  67
  68         res = []
  69         for i in range(num_ops):
  70             res.append(Signal(width))
  71         self.v  = Array(res)
  72
  73     def ports(self):
  74         res = []
  75         for i in range(self.num_ops):
  76             res.append(self.v[i])
  77         res.append(self.ack)
  78         res.append(self.stb)
  79         return res
  80
  81
  82 class InputGroup:
  83     def __init__(self, width, num_ops=2, num_rows=4):
  84         self.width = width
  85         self.num_ops = num_ops
  86         self.num_rows = num_rows
  87         self.mmax = int(log(self.num_rows) / log(2))
  88         self.rs = []
  89         self.mid = Signal(self.mmax, reset_less=True) # multiplex id
  90         for i in range(num_rows):
  91             self.rs.append(FPGetSyncOpsMod(width, num_ops))
  92         self.rs = Array(self.rs)
  93
  94         self.out_op = FPOps(width, num_ops)
  95
  96     def elaborate(self, platform):
  97         m = Module()
  98
  99         pe = PriorityEncoder(self.num_rows)
 100         m.submodules.selector = pe
 101         m.submodules.out_op = self.out_op
 102         m.submodules += self.rs
 103
 104         # connect priority encoder
 105         in_ready = []
 106         for i in range(self.num_rows):
 107             in_ready.append(self.rs[i].ready)
 108         m.d.comb += pe.i.eq(Cat(*in_ready))
 109
 110         active = Signal(reset_less=True)
 111         out_en = Signal(reset_less=True)
 112         m.d.comb += active.eq(~pe.n) # encoder active
 113         m.d.comb += out_en.eq(active & self.out_op.trigger)
 114
 115         # encoder active: ack relevant input, record MID, pass output
 116         with m.If(out_en):
 117             rs = self.rs[pe.o]
 118             m.d.sync += self.mid.eq(pe.o)
 119             m.d.sync += rs.ack.eq(0)
 120             m.d.sync += self.out_op.stb.eq(0)
 121             for j in range(self.num_ops):
 122                 m.d.sync += self.out_op.v[j].eq(rs.out_op[j])
 123         with m.Else():
 124             m.d.sync += self.out_op.stb.eq(1)
 125             # acks all default to zero
 126             for i in range(self.num_rows):
 127                 m.d.sync += self.rs[i].ack.eq(1)
 128
 129         return m
 130
 131     def ports(self):
 132         res = []
 133         for i in range(self.num_rows):
 134             inop = self.rs[i]
 135             res += inop.in_op + [inop.stb]
 136         return self.out_op.ports() + res + [self.mid]
 137
 138
 139 class FPGetOpMod:
 140     def __init__(self, width):
 141         self.in_op = FPOp(width)
 142         self.out_op = Signal(width)
 143         self.out_decode = Signal(reset_less=True)
 144
 145     def elaborate(self, platform):
 146         m = Module()
 147         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
 148         m.submodules.get_op_in = self.in_op
 149         #m.submodules.get_op_out = self.out_op
 150         with m.If(self.out_decode):
 151             m.d.comb += [
 152                 self.out_op.eq(self.in_op.v),
 153             ]
 154         return m
 155
 156
 157 class FPGetOp(FPState):
 158     """ gets operand
 159     """
 160
 161     def __init__(self, in_state, out_state, in_op, width):
 162         FPState.__init__(self, in_state)
 163         self.out_state = out_state
 164         self.mod = FPGetOpMod(width)
 165         self.in_op = in_op
 166         self.out_op = Signal(width)
 167         self.out_decode = Signal(reset_less=True)
 168
 169     def setup(self, m, in_op):
 170         """ links module to inputs and outputs
 171         """
 172         setattr(m.submodules, self.state_from, self.mod)
 173         m.d.comb += self.mod.in_op.eq(in_op)
 174         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 175
 176     def action(self, m):
 177         with m.If(self.out_decode):
 178             m.next = self.out_state
 179             m.d.sync += [
 180                 self.in_op.ack.eq(0),
 181                 self.out_op.eq(self.mod.out_op)
 182             ]
 183         with m.Else():
 184             m.d.sync += self.in_op.ack.eq(1)
 185
 186
 187 class FPGet2OpMod(Trigger):
 188     def __init__(self, width, id_wid):
 189         Trigger.__init__(self)
 190         self.width = width
 191         self.id_wid = id_wid
 192         self.i = self.ispec()
 193         self.o = self.ospec()
 194
 195     def ispec(self):
 196         return FPADDBaseData(self.width, self.id_wid)
 197
 198     def ospec(self):
 199         return FPNumBase2Ops(self.width, self.id_wid)
 200
 201     def elaborate(self, platform):
 202         m = Trigger.elaborate(self, platform)
 203         m.submodules.get_op1_out = self.o.a
 204         m.submodules.get_op2_out = self.o.b
 205         out_op1 = FPNumIn(None, self.width)
 206         out_op2 = FPNumIn(None, self.width)
 207         with m.If(self.trigger):
 208             m.d.comb += [
 209                 out_op1.decode(self.i.a),
 210                 out_op2.decode(self.i.b),
 211                 self.o.a.eq(out_op1),
 212                 self.o.b.eq(out_op2),
 213                 self.o.mid.eq(self.i.mid)
 214             ]
 215         return m
 216
 217
 218 class FPGet2Op(FPState):
 219     """ gets operands
 220     """
 221
 222     def __init__(self, in_state, out_state, width, id_wid):
 223         FPState.__init__(self, in_state)
 224         self.out_state = out_state
 225         self.mod = FPGet2OpMod(width, id_wid)
 226         self.o = self.mod.ospec()
 227         self.in_stb = Signal(reset_less=True)
 228         self.out_ack = Signal(reset_less=True)
 229         self.out_decode = Signal(reset_less=True)
 230
 231     def setup(self, m, i, in_stb, in_ack):
 232         """ links module to inputs and outputs
 233         """
 234         m.submodules.get_ops = self.mod
 235         m.d.comb += self.mod.i.eq(i)
 236         m.d.comb += self.mod.stb.eq(in_stb)
 237         m.d.comb += self.out_ack.eq(self.mod.ack)
 238         m.d.comb += self.out_decode.eq(self.mod.trigger)
 239         m.d.comb += in_ack.eq(self.mod.ack)
 240
 241     def action(self, m):
 242         with m.If(self.out_decode):
 243             m.next = self.out_state
 244             m.d.sync += [
 245                 self.mod.ack.eq(0),
 246                 self.o.eq(self.mod.o),
 247             ]
 248         with m.Else():
 249             m.d.sync += self.mod.ack.eq(1)
 250
 251
 252 class FPNumBase2Ops:
 253
 254     def __init__(self, width, id_wid, m_extra=True):
 255         self.a = FPNumBase(width, m_extra)
 256         self.b = FPNumBase(width, m_extra)
 257         self.mid = Signal(id_wid, reset_less=True)
 258
 259     def eq(self, i):
 260         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 261
 262
 263 class FPSCData:
 264
 265     def __init__(self, width, id_wid):
 266         self.a = FPNumBase(width, True)
 267         self.b = FPNumBase(width, True)
 268         self.z = FPNumOut(width, False)
 269         self.out_do_z = Signal(reset_less=True)
 270         self.mid = Signal(id_wid, reset_less=True)
 271
 272     def eq(self, i):
 273         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z),
 274                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 275
 276
 277 class FPAddSpecialCasesMod:
 278     """ special cases: NaNs, infs, zeros, denormalised
 279         NOTE: some of these are unique to add.  see "Special Operations"
 280         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 281     """
 282
 283     def __init__(self, width, id_wid):
 284         self.width = width
 285         self.id_wid = id_wid
 286         self.i = self.ispec()
 287         self.o = self.ospec()
 288
 289     def ispec(self):
 290         return FPNumBase2Ops(self.width, self.id_wid)
 291
 292     def ospec(self):
 293         return FPSCData(self.width, self.id_wid)
 294
 295     def setup(self, m, i):
 296         """ links module to inputs and outputs
 297         """
 298         m.submodules.specialcases = self
 299         m.d.comb += self.i.eq(i)
 300
 301     def elaborate(self, platform):
 302         m = Module()
 303
 304         m.submodules.sc_in_a = self.i.a
 305         m.submodules.sc_in_b = self.i.b
 306         m.submodules.sc_out_z = self.o.z
 307
 308         s_nomatch = Signal()
 309         m.d.comb += s_nomatch.eq(self.i.a.s != self.i.b.s)
 310
 311         m_match = Signal()
 312         m.d.comb += m_match.eq(self.i.a.m == self.i.b.m)
 313
 314         # if a is NaN or b is NaN return NaN
 315         with m.If(self.i.a.is_nan | self.i.b.is_nan):
 316             m.d.comb += self.o.out_do_z.eq(1)
 317             m.d.comb += self.o.z.nan(0)
 318
 319         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 320         # under review
 321
 322         ## if a is zero and b is NaN return -b
 323         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 324         #    m.d.comb += self.o.out_do_z.eq(1)
 325         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 326
 327         ## if b is zero and a is NaN return -a
 328         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 329         #    m.d.comb += self.o.out_do_z.eq(1)
 330         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 331
 332         ## if a is -zero and b is NaN return -b
 333         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 334         #    m.d.comb += self.o.out_do_z.eq(1)
 335         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 336
 337         ## if b is -zero and a is NaN return -a
 338         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 339         #    m.d.comb += self.o.out_do_z.eq(1)
 340         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 341
 342         # if a is inf return inf (or NaN)
 343         with m.Elif(self.i.a.is_inf):
 344             m.d.comb += self.o.out_do_z.eq(1)
 345             m.d.comb += self.o.z.inf(self.i.a.s)
 346             # if a is inf and signs don't match return NaN
 347             with m.If(self.i.b.exp_128 & s_nomatch):
 348                 m.d.comb += self.o.z.nan(0)
 349
 350         # if b is inf return inf
 351         with m.Elif(self.i.b.is_inf):
 352             m.d.comb += self.o.out_do_z.eq(1)
 353             m.d.comb += self.o.z.inf(self.i.b.s)
 354
 355         # if a is zero and b zero return signed-a/b
 356         with m.Elif(self.i.a.is_zero & self.i.b.is_zero):
 357             m.d.comb += self.o.out_do_z.eq(1)
 358             m.d.comb += self.o.z.create(self.i.a.s & self.i.b.s,
 359                                           self.i.b.e,
 360                                           self.i.b.m[3:-1])
 361
 362         # if a is zero return b
 363         with m.Elif(self.i.a.is_zero):
 364             m.d.comb += self.o.out_do_z.eq(1)
 365             m.d.comb += self.o.z.create(self.i.b.s, self.i.b.e,
 366                                       self.i.b.m[3:-1])
 367
 368         # if b is zero return a
 369         with m.Elif(self.i.b.is_zero):
 370             m.d.comb += self.o.out_do_z.eq(1)
 371             m.d.comb += self.o.z.create(self.i.a.s, self.i.a.e,
 372                                       self.i.a.m[3:-1])
 373
 374         # if a equal to -b return zero (+ve zero)
 375         with m.Elif(s_nomatch & m_match & (self.i.a.e == self.i.b.e)):
 376             m.d.comb += self.o.out_do_z.eq(1)
 377             m.d.comb += self.o.z.zero(0)
 378
 379         # Denormalised Number checks next, so pass a/b data through
 380         with m.Else():
 381             m.d.comb += self.o.out_do_z.eq(0)
 382             m.d.comb += self.o.a.eq(self.i.a)
 383             m.d.comb += self.o.b.eq(self.i.b)
 384
 385         m.d.comb += self.o.mid.eq(self.i.mid)
 386
 387         return m
 388
 389
 390 class FPID:
 391     def __init__(self, id_wid):
 392         self.id_wid = id_wid
 393         if self.id_wid:
 394             self.in_mid = Signal(id_wid, reset_less=True)
 395             self.out_mid = Signal(id_wid, reset_less=True)
 396         else:
 397             self.in_mid = None
 398             self.out_mid = None
 399
 400     def idsync(self, m):
 401         if self.id_wid is not None:
 402             m.d.sync += self.out_mid.eq(self.in_mid)
 403
 404
 405 class FPAddSpecialCases(FPState):
 406     """ special cases: NaNs, infs, zeros, denormalised
 407         NOTE: some of these are unique to add.  see "Special Operations"
 408         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 409     """
 410
 411     def __init__(self, width, id_wid):
 412         FPState.__init__(self, "special_cases")
 413         self.mod = FPAddSpecialCasesMod(width)
 414         self.out_z = self.mod.ospec()
 415         self.out_do_z = Signal(reset_less=True)
 416
 417     def setup(self, m, i):
 418         """ links module to inputs and outputs
 419         """
 420         self.mod.setup(m, i, self.out_do_z)
 421         m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 422         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)  # (and mid)
 423
 424     def action(self, m):
 425         self.idsync(m)
 426         with m.If(self.out_do_z):
 427             m.next = "put_z"
 428         with m.Else():
 429             m.next = "denormalise"
 430
 431
 432 class FPAddSpecialCasesDeNorm(FPState):
 433     """ special cases: NaNs, infs, zeros, denormalised
 434         NOTE: some of these are unique to add.  see "Special Operations"
 435         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 436     """
 437
 438     def __init__(self, width, id_wid):
 439         FPState.__init__(self, "special_cases")
 440         self.smod = FPAddSpecialCasesMod(width, id_wid)
 441         self.out_z = self.smod.ospec()
 442         self.out_do_z = Signal(reset_less=True)
 443
 444         self.dmod = FPAddDeNormMod(width, id_wid)
 445         self.o = self.dmod.ospec()
 446
 447     def setup(self, m, i):
 448         """ links module to inputs and outputs
 449         """
 450         self.smod.setup(m, i)
 451         self.dmod.setup(m, self.smod.o)
 452         m.d.comb += self.out_do_z.eq(self.smod.o.out_do_z)
 453
 454         # out_do_z=True
 455         m.d.sync += self.out_z.z.v.eq(self.smod.o.z.v) # only take output
 456         m.d.sync += self.out_z.mid.eq(self.smod.o.mid)  # (and mid)
 457         # out_do_z=False
 458         m.d.sync += self.o.eq(self.dmod.o)
 459
 460     def action(self, m):
 461         with m.If(self.out_do_z):
 462             m.next = "put_z"
 463         with m.Else():
 464             m.next = "align"
 465
 466
 467 class FPAddDeNormMod(FPState):
 468
 469     def __init__(self, width, id_wid):
 470         self.width = width
 471         self.id_wid = id_wid
 472         self.i = self.ispec()
 473         self.o = self.ospec()
 474
 475     def ispec(self):
 476         return FPSCData(self.width, self.id_wid)
 477
 478     def ospec(self):
 479         return FPSCData(self.width, self.id_wid)
 480
 481     def setup(self, m, i):
 482         """ links module to inputs and outputs
 483         """
 484         m.submodules.denormalise = self
 485         m.d.comb += self.i.eq(i)
 486
 487     def elaborate(self, platform):
 488         m = Module()
 489         m.submodules.denorm_in_a = self.i.a
 490         m.submodules.denorm_in_b = self.i.b
 491         m.submodules.denorm_out_a = self.o.a
 492         m.submodules.denorm_out_b = self.o.b
 493
 494         with m.If(~self.i.out_do_z):
 495             # XXX hmmm, don't like repeating identical code
 496             m.d.comb += self.o.a.eq(self.i.a)
 497             with m.If(self.i.a.exp_n127):
 498                 m.d.comb += self.o.a.e.eq(self.i.a.N126) # limit a exponent
 499             with m.Else():
 500                 m.d.comb += self.o.a.m[-1].eq(1) # set top mantissa bit
 501
 502             m.d.comb += self.o.b.eq(self.i.b)
 503             with m.If(self.i.b.exp_n127):
 504                 m.d.comb += self.o.b.e.eq(self.i.b.N126) # limit a exponent
 505             with m.Else():
 506                 m.d.comb += self.o.b.m[-1].eq(1) # set top mantissa bit
 507
 508         m.d.comb += self.o.mid.eq(self.i.mid)
 509         m.d.comb += self.o.z.eq(self.i.z)
 510         m.d.comb += self.o.out_do_z.eq(self.i.out_do_z)
 511
 512         return m
 513
 514
 515 class FPAddDeNorm(FPState):
 516
 517     def __init__(self, width, id_wid):
 518         FPState.__init__(self, "denormalise")
 519         self.mod = FPAddDeNormMod(width)
 520         self.out_a = FPNumBase(width)
 521         self.out_b = FPNumBase(width)
 522
 523     def setup(self, m, i):
 524         """ links module to inputs and outputs
 525         """
 526         self.mod.setup(m, i)
 527
 528         m.d.sync += self.out_a.eq(self.mod.out_a)
 529         m.d.sync += self.out_b.eq(self.mod.out_b)
 530
 531     def action(self, m):
 532         # Denormalised Number checks
 533         m.next = "align"
 534
 535
 536 class FPAddAlignMultiMod(FPState):
 537
 538     def __init__(self, width):
 539         self.in_a = FPNumBase(width)
 540         self.in_b = FPNumBase(width)
 541         self.out_a = FPNumIn(None, width)
 542         self.out_b = FPNumIn(None, width)
 543         self.exp_eq = Signal(reset_less=True)
 544
 545     def elaborate(self, platform):
 546         # This one however (single-cycle) will do the shift
 547         # in one go.
 548
 549         m = Module()
 550
 551         m.submodules.align_in_a = self.in_a
 552         m.submodules.align_in_b = self.in_b
 553         m.submodules.align_out_a = self.out_a
 554         m.submodules.align_out_b = self.out_b
 555
 556         # NOTE: this does *not* do single-cycle multi-shifting,
 557         #       it *STAYS* in the align state until exponents match
 558
 559         # exponent of a greater than b: shift b down
 560         m.d.comb += self.exp_eq.eq(0)
 561         m.d.comb += self.out_a.eq(self.in_a)
 562         m.d.comb += self.out_b.eq(self.in_b)
 563         agtb = Signal(reset_less=True)
 564         altb = Signal(reset_less=True)
 565         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 566         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 567         with m.If(agtb):
 568             m.d.comb += self.out_b.shift_down(self.in_b)
 569         # exponent of b greater than a: shift a down
 570         with m.Elif(altb):
 571             m.d.comb += self.out_a.shift_down(self.in_a)
 572         # exponents equal: move to next stage.
 573         with m.Else():
 574             m.d.comb += self.exp_eq.eq(1)
 575         return m
 576
 577
 578 class FPAddAlignMulti(FPState):
 579
 580     def __init__(self, width, id_wid):
 581         FPState.__init__(self, "align")
 582         self.mod = FPAddAlignMultiMod(width)
 583         self.out_a = FPNumIn(None, width)
 584         self.out_b = FPNumIn(None, width)
 585         self.exp_eq = Signal(reset_less=True)
 586
 587     def setup(self, m, in_a, in_b):
 588         """ links module to inputs and outputs
 589         """
 590         m.submodules.align = self.mod
 591         m.d.comb += self.mod.in_a.eq(in_a)
 592         m.d.comb += self.mod.in_b.eq(in_b)
 593         #m.d.comb += self.out_a.eq(self.mod.out_a)
 594         #m.d.comb += self.out_b.eq(self.mod.out_b)
 595         m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
 596         m.d.sync += self.out_a.eq(self.mod.out_a)
 597         m.d.sync += self.out_b.eq(self.mod.out_b)
 598
 599     def action(self, m):
 600         with m.If(self.exp_eq):
 601             m.next = "add_0"
 602
 603
 604 class FPNumIn2Ops:
 605
 606     def __init__(self, width, id_wid):
 607         self.a = FPNumIn(None, width)
 608         self.b = FPNumIn(None, width)
 609         self.z = FPNumOut(width, False)
 610         self.out_do_z = Signal(reset_less=True)
 611         self.mid = Signal(id_wid, reset_less=True)
 612
 613     def eq(self, i):
 614         return [self.z.eq(i.z), self.out_do_z.eq(i.out_do_z),
 615                 self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
 616
 617
 618 class FPAddAlignSingleMod:
 619
 620     def __init__(self, width, id_wid):
 621         self.width = width
 622         self.id_wid = id_wid
 623         self.i = self.ispec()
 624         self.o = self.ospec()
 625
 626     def ispec(self):
 627         return FPNumBase2Ops(self.width, self.id_wid)
 628
 629     def ospec(self):
 630         return FPNumIn2Ops(self.width, self.id_wid)
 631
 632     def process(self, i):
 633         return self.o
 634
 635     def setup(self, m, i):
 636         """ links module to inputs and outputs
 637         """
 638         m.submodules.align = self
 639         m.d.comb += self.i.eq(i)
 640
 641     def elaborate(self, platform):
 642         """ Aligns A against B or B against A, depending on which has the
 643             greater exponent.  This is done in a *single* cycle using
 644             variable-width bit-shift
 645
 646             the shifter used here is quite expensive in terms of gates.
 647             Mux A or B in (and out) into temporaries, as only one of them
 648             needs to be aligned against the other
 649         """
 650         m = Module()
 651
 652         m.submodules.align_in_a = self.i.a
 653         m.submodules.align_in_b = self.i.b
 654         m.submodules.align_out_a = self.o.a
 655         m.submodules.align_out_b = self.o.b
 656
 657         # temporary (muxed) input and output to be shifted
 658         t_inp = FPNumBase(self.width)
 659         t_out = FPNumIn(None, self.width)
 660         espec = (len(self.i.a.e), True)
 661         msr = MultiShiftRMerge(self.i.a.m_width, espec)
 662         m.submodules.align_t_in = t_inp
 663         m.submodules.align_t_out = t_out
 664         m.submodules.multishift_r = msr
 665
 666         ediff = Signal(espec, reset_less=True)
 667         ediffr = Signal(espec, reset_less=True)
 668         tdiff = Signal(espec, reset_less=True)
 669         elz = Signal(reset_less=True)
 670         egz = Signal(reset_less=True)
 671
 672         # connect multi-shifter to t_inp/out mantissa (and tdiff)
 673         m.d.comb += msr.inp.eq(t_inp.m)
 674         m.d.comb += msr.diff.eq(tdiff)
 675         m.d.comb += t_out.m.eq(msr.m)
 676         m.d.comb += t_out.e.eq(t_inp.e + tdiff)
 677         m.d.comb += t_out.s.eq(t_inp.s)
 678
 679         m.d.comb += ediff.eq(self.i.a.e - self.i.b.e)
 680         m.d.comb += ediffr.eq(self.i.b.e - self.i.a.e)
 681         m.d.comb += elz.eq(self.i.a.e < self.i.b.e)
 682         m.d.comb += egz.eq(self.i.a.e > self.i.b.e)
 683
 684         # default: A-exp == B-exp, A and B untouched (fall through)
 685         m.d.comb += self.o.a.eq(self.i.a)
 686         m.d.comb += self.o.b.eq(self.i.b)
 687         # only one shifter (muxed)
 688         #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
 689         # exponent of a greater than b: shift b down
 690         with m.If(egz):
 691             m.d.comb += [t_inp.eq(self.i.b),
 692                          tdiff.eq(ediff),
 693                          self.o.b.eq(t_out),
 694                          self.o.b.s.eq(self.i.b.s), # whoops forgot sign
 695                         ]
 696         # exponent of b greater than a: shift a down
 697         with m.Elif(elz):
 698             m.d.comb += [t_inp.eq(self.i.a),
 699                          tdiff.eq(ediffr),
 700                          self.o.a.eq(t_out),
 701                          self.o.a.s.eq(self.i.a.s), # whoops forgot sign
 702                         ]
 703
 704         m.d.comb += self.o.mid.eq(self.i.mid)
 705
 706         return m
 707
 708
 709 class FPAddAlignSingle(FPState):
 710
 711     def __init__(self, width, id_wid):
 712         FPState.__init__(self, "align")
 713         self.mod = FPAddAlignSingleMod(width, id_wid)
 714         self.out_a = FPNumIn(None, width)
 715         self.out_b = FPNumIn(None, width)
 716
 717     def setup(self, m, i):
 718         """ links module to inputs and outputs
 719         """
 720         self.mod.setup(m, i)
 721
 722         # NOTE: could be done as comb
 723         m.d.sync += self.out_a.eq(self.mod.out_a)
 724         m.d.sync += self.out_b.eq(self.mod.out_b)
 725
 726     def action(self, m):
 727         m.next = "add_0"
 728
 729
 730 class FPAddAlignSingleAdd(FPState):
 731
 732     def __init__(self, width, id_wid):
 733         FPState.__init__(self, "align")
 734         self.width = width
 735         self.id_wid = id_wid
 736         self.a1o = self.ospec()
 737
 738     def ispec(self):
 739         return FPNumBase2Ops(self.width, self.id_wid) # AlignSingle ispec
 740
 741     def ospec(self):
 742         return FPAddStage1Data(self.width, self.id_wid) # AddStage1 ospec
 743
 744     def setup(self, m, i):
 745         """ links module to inputs and outputs
 746         """
 747
 748         # chain AddAlignSingle, AddStage0 and AddStage1
 749         mod = FPAddAlignSingleMod(self.width, self.id_wid)
 750         a0mod = FPAddStage0Mod(self.width, self.id_wid)
 751         a1mod = FPAddStage1Mod(self.width, self.id_wid)
 752
 753         chain = StageChain([mod, a0mod, a1mod])
 754         chain.setup(m, i)
 755
 756         m.d.sync += self.a1o.eq(a1mod.o)
 757
 758     def action(self, m):
 759         m.next = "normalise_1"
 760
 761
 762 class FPAddStage0Data:
 763
 764     def __init__(self, width, id_wid):
 765         self.z = FPNumBase(width, False)
 766         self.tot = Signal(self.z.m_width + 4, reset_less=True)
 767         self.mid = Signal(id_wid, reset_less=True)
 768
 769     def eq(self, i):
 770         return [self.z.eq(i.z), self.tot.eq(i.tot), self.mid.eq(i.mid)]
 771
 772
 773 class FPAddStage0Mod:
 774
 775     def __init__(self, width, id_wid):
 776         self.width = width
 777         self.id_wid = id_wid
 778         self.i = self.ispec()
 779         self.o = self.ospec()
 780
 781     def ispec(self):
 782         return FPNumBase2Ops(self.width, self.id_wid)
 783
 784     def ospec(self):
 785         return FPAddStage0Data(self.width, self.id_wid)
 786
 787     def process(self, i):
 788         return self.o
 789
 790     def setup(self, m, i):
 791         """ links module to inputs and outputs
 792         """
 793         m.submodules.add0 = self
 794         m.d.comb += self.i.eq(i)
 795
 796     def elaborate(self, platform):
 797         m = Module()
 798         m.submodules.add0_in_a = self.i.a
 799         m.submodules.add0_in_b = self.i.b
 800         m.submodules.add0_out_z = self.o.z
 801
 802         m.d.comb += self.o.mid.eq(self.i.mid)
 803         m.d.comb += self.o.z.e.eq(self.i.a.e)
 804
 805         # store intermediate tests (and zero-extended mantissas)
 806         seq = Signal(reset_less=True)
 807         mge = Signal(reset_less=True)
 808         am0 = Signal(len(self.i.a.m)+1, reset_less=True)
 809         bm0 = Signal(len(self.i.b.m)+1, reset_less=True)
 810         m.d.comb += [seq.eq(self.i.a.s == self.i.b.s),
 811                      mge.eq(self.i.a.m >= self.i.b.m),
 812                      am0.eq(Cat(self.i.a.m, 0)),
 813                      bm0.eq(Cat(self.i.b.m, 0))
 814                     ]
 815         # same-sign (both negative or both positive) add mantissas
 816         with m.If(seq):
 817             m.d.comb += [
 818                 self.o.tot.eq(am0 + bm0),
 819                 self.o.z.s.eq(self.i.a.s)
 820             ]
 821         # a mantissa greater than b, use a
 822         with m.Elif(mge):
 823             m.d.comb += [
 824                 self.o.tot.eq(am0 - bm0),
 825                 self.o.z.s.eq(self.i.a.s)
 826             ]
 827         # b mantissa greater than a, use b
 828         with m.Else():
 829             m.d.comb += [
 830                 self.o.tot.eq(bm0 - am0),
 831                 self.o.z.s.eq(self.i.b.s)
 832         ]
 833         return m
 834
 835
 836 class FPAddStage0(FPState):
 837     """ First stage of add.  covers same-sign (add) and subtract
 838         special-casing when mantissas are greater or equal, to
 839         give greatest accuracy.
 840     """
 841
 842     def __init__(self, width, id_wid):
 843         FPState.__init__(self, "add_0")
 844         self.mod = FPAddStage0Mod(width)
 845         self.o = self.mod.ospec()
 846
 847     def setup(self, m, i):
 848         """ links module to inputs and outputs
 849         """
 850         self.mod.setup(m, i)
 851
 852         # NOTE: these could be done as combinatorial (merge add0+add1)
 853         m.d.sync += self.o.eq(self.mod.o)
 854
 855     def action(self, m):
 856         m.next = "add_1"
 857
 858
 859 class FPAddStage1Data:
 860
 861     def __init__(self, width, id_wid):
 862         self.z = FPNumBase(width, False)
 863         self.of = Overflow()
 864         self.mid = Signal(id_wid, reset_less=True)
 865
 866     def eq(self, i):
 867         return [self.z.eq(i.z), self.of.eq(i.of), self.mid.eq(i.mid)]
 868
 869
 870
 871 class FPAddStage1Mod(FPState):
 872     """ Second stage of add: preparation for normalisation.
 873         detects when tot sum is too big (tot[27] is kinda a carry bit)
 874     """
 875
 876     def __init__(self, width, id_wid):
 877         self.width = width
 878         self.id_wid = id_wid
 879         self.i = self.ispec()
 880         self.o = self.ospec()
 881
 882     def ispec(self):
 883         return FPAddStage0Data(self.width, self.id_wid)
 884
 885     def ospec(self):
 886         return FPAddStage1Data(self.width, self.id_wid)
 887
 888     def process(self, i):
 889         return self.o
 890
 891     def setup(self, m, i):
 892         """ links module to inputs and outputs
 893         """
 894         m.submodules.add1 = self
 895         m.submodules.add1_out_overflow = self.o.of
 896
 897         m.d.comb += self.i.eq(i)
 898
 899     def elaborate(self, platform):
 900         m = Module()
 901         #m.submodules.norm1_in_overflow = self.in_of
 902         #m.submodules.norm1_out_overflow = self.out_of
 903         #m.submodules.norm1_in_z = self.in_z
 904         #m.submodules.norm1_out_z = self.out_z
 905         m.d.comb += self.o.z.eq(self.i.z)
 906         m.d.comb += self.o.mid.eq(self.i.mid)
 907         # tot[-1] (MSB) gets set when the sum overflows. shift result down
 908         with m.If(self.i.tot[-1]):
 909             m.d.comb += [
 910                 self.o.z.m.eq(self.i.tot[4:]),
 911                 self.o.of.m0.eq(self.i.tot[4]),
 912                 self.o.of.guard.eq(self.i.tot[3]),
 913                 self.o.of.round_bit.eq(self.i.tot[2]),
 914                 self.o.of.sticky.eq(self.i.tot[1] | self.i.tot[0]),
 915                 self.o.z.e.eq(self.i.z.e + 1)
 916         ]
 917         # tot[-1] (MSB) zero case
 918         with m.Else():
 919             m.d.comb += [
 920                 self.o.z.m.eq(self.i.tot[3:]),
 921                 self.o.of.m0.eq(self.i.tot[3]),
 922                 self.o.of.guard.eq(self.i.tot[2]),
 923                 self.o.of.round_bit.eq(self.i.tot[1]),
 924                 self.o.of.sticky.eq(self.i.tot[0])
 925         ]
 926         return m
 927
 928
 929 class FPAddStage1(FPState):
 930
 931     def __init__(self, width, id_wid):
 932         FPState.__init__(self, "add_1")
 933         self.mod = FPAddStage1Mod(width)
 934         self.out_z = FPNumBase(width, False)
 935         self.out_of = Overflow()
 936         self.norm_stb = Signal()
 937
 938     def setup(self, m, i):
 939         """ links module to inputs and outputs
 940         """
 941         self.mod.setup(m, i)
 942
 943         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 944
 945         m.d.sync += self.out_of.eq(self.mod.out_of)
 946         m.d.sync += self.out_z.eq(self.mod.out_z)
 947         m.d.sync += self.norm_stb.eq(1)
 948
 949     def action(self, m):
 950         m.next = "normalise_1"
 951
 952
 953 class FPNormaliseModSingle:
 954
 955     def __init__(self, width):
 956         self.width = width
 957         self.in_z = self.ispec()
 958         self.out_z = self.ospec()
 959
 960     def ispec(self):
 961         return FPNumBase(self.width, False)
 962
 963     def ospec(self):
 964         return FPNumBase(self.width, False)
 965
 966     def setup(self, m, i):
 967         """ links module to inputs and outputs
 968         """
 969         m.submodules.normalise = self
 970         m.d.comb += self.i.eq(i)
 971
 972     def elaborate(self, platform):
 973         m = Module()
 974
 975         mwid = self.out_z.m_width+2
 976         pe = PriorityEncoder(mwid)
 977         m.submodules.norm_pe = pe
 978
 979         m.submodules.norm1_out_z = self.out_z
 980         m.submodules.norm1_in_z = self.in_z
 981
 982         in_z = FPNumBase(self.width, False)
 983         in_of = Overflow()
 984         m.submodules.norm1_insel_z = in_z
 985         m.submodules.norm1_insel_overflow = in_of
 986
 987         espec = (len(in_z.e), True)
 988         ediff_n126 = Signal(espec, reset_less=True)
 989         msr = MultiShiftRMerge(mwid, espec)
 990         m.submodules.multishift_r = msr
 991
 992         m.d.comb += in_z.eq(self.in_z)
 993         m.d.comb += in_of.eq(self.in_of)
 994         # initialise out from in (overridden below)
 995         m.d.comb += self.out_z.eq(in_z)
 996         m.d.comb += self.out_of.eq(in_of)
 997         # normalisation decrease condition
 998         decrease = Signal(reset_less=True)
 999         m.d.comb += decrease.eq(in_z.m_msbzero)
1000         # decrease exponent
1001         with m.If(decrease):
1002             # *sigh* not entirely obvious: count leading zeros (clz)
1003             # with a PriorityEncoder: to find from the MSB
1004             # we reverse the order of the bits.
1005             temp_m = Signal(mwid, reset_less=True)
1006             temp_s = Signal(mwid+1, reset_less=True)
1007             clz = Signal((len(in_z.e), True), reset_less=True)
1008             m.d.comb += [
1009                 # cat round and guard bits back into the mantissa
1010                 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
1011                 pe.i.eq(temp_m[::-1]),          # inverted
1012                 clz.eq(pe.o),                   # count zeros from MSB down
1013                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1014                 self.out_z.e.eq(in_z.e - clz),  # DECREASE exponent
1015                 self.out_z.m.eq(temp_s[2:]),    # exclude bits 0&1
1016             ]
1017
1018         return m
1019
1020 class FPNorm1Data:
1021
1022     def __init__(self, width, id_wid):
1023         self.roundz = Signal(reset_less=True)
1024         self.z = FPNumBase(width, False)
1025         self.mid = Signal(id_wid, reset_less=True)
1026
1027     def eq(self, i):
1028         return [self.z.eq(i.z), self.roundz.eq(i.roundz), self.mid.eq(i.mid)]
1029
1030
1031 class FPNorm1ModSingle:
1032
1033     def __init__(self, width, id_wid):
1034         self.width = width
1035         self.id_wid = id_wid
1036         self.i = self.ispec()
1037         self.o = self.ospec()
1038
1039     def ispec(self):
1040         return FPAddStage1Data(self.width, self.id_wid)
1041
1042     def ospec(self):
1043         return FPNorm1Data(self.width, self.id_wid)
1044
1045     def setup(self, m, i):
1046         """ links module to inputs and outputs
1047         """
1048         m.submodules.normalise_1 = self
1049         m.d.comb += self.i.eq(i)
1050
1051     def process(self, i):
1052         return self.o
1053
1054     def elaborate(self, platform):
1055         m = Module()
1056
1057         mwid = self.o.z.m_width+2
1058         pe = PriorityEncoder(mwid)
1059         m.submodules.norm_pe = pe
1060
1061         of = Overflow()
1062         m.d.comb += self.o.roundz.eq(of.roundz)
1063
1064         m.submodules.norm1_out_z = self.o.z
1065         m.submodules.norm1_out_overflow = of
1066         m.submodules.norm1_in_z = self.i.z
1067         m.submodules.norm1_in_overflow = self.i.of
1068
1069         i = self.ispec()
1070         m.submodules.norm1_insel_z = i.z
1071         m.submodules.norm1_insel_overflow = i.of
1072
1073         espec = (len(i.z.e), True)
1074         ediff_n126 = Signal(espec, reset_less=True)
1075         msr = MultiShiftRMerge(mwid, espec)
1076         m.submodules.multishift_r = msr
1077
1078         m.d.comb += i.eq(self.i)
1079         # initialise out from in (overridden below)
1080         m.d.comb += self.o.z.eq(i.z)
1081         m.d.comb += self.o.mid.eq(self.i.mid)
1082         m.d.comb += of.eq(i.of)
1083         # normalisation increase/decrease conditions
1084         decrease = Signal(reset_less=True)
1085         increase = Signal(reset_less=True)
1086         m.d.comb += decrease.eq(i.z.m_msbzero & i.z.exp_gt_n126)
1087         m.d.comb += increase.eq(i.z.exp_lt_n126)
1088         # decrease exponent
1089         with m.If(decrease):
1090             # *sigh* not entirely obvious: count leading zeros (clz)
1091             # with a PriorityEncoder: to find from the MSB
1092             # we reverse the order of the bits.
1093             temp_m = Signal(mwid, reset_less=True)
1094             temp_s = Signal(mwid+1, reset_less=True)
1095             clz = Signal((len(i.z.e), True), reset_less=True)
1096             # make sure that the amount to decrease by does NOT
1097             # go below the minimum non-INF/NaN exponent
1098             limclz = Mux(i.z.exp_sub_n126 > pe.o, pe.o,
1099                          i.z.exp_sub_n126)
1100             m.d.comb += [
1101                 # cat round and guard bits back into the mantissa
1102                 temp_m.eq(Cat(i.of.round_bit, i.of.guard, i.z.m)),
1103                 pe.i.eq(temp_m[::-1]),          # inverted
1104                 clz.eq(limclz),                 # count zeros from MSB down
1105                 temp_s.eq(temp_m << clz),       # shift mantissa UP
1106                 self.o.z.e.eq(i.z.e - clz),  # DECREASE exponent
1107                 self.o.z.m.eq(temp_s[2:]),    # exclude bits 0&1
1108                 of.m0.eq(temp_s[2]),          # copy of mantissa[0]
1109                 # overflow in bits 0..1: got shifted too (leave sticky)
1110                 of.guard.eq(temp_s[1]),       # guard
1111                 of.round_bit.eq(temp_s[0]),   # round
1112             ]
1113         # increase exponent
1114         with m.Elif(increase):
1115             temp_m = Signal(mwid+1, reset_less=True)
1116             m.d.comb += [
1117                 temp_m.eq(Cat(i.of.sticky, i.of.round_bit, i.of.guard,
1118                               i.z.m)),
1119                 ediff_n126.eq(i.z.N126 - i.z.e),
1120                 # connect multi-shifter to inp/out mantissa (and ediff)
1121                 msr.inp.eq(temp_m),
1122                 msr.diff.eq(ediff_n126),
1123                 self.o.z.m.eq(msr.m[3:]),
1124                 of.m0.eq(temp_s[3]),   # copy of mantissa[0]
1125                 # overflow in bits 0..1: got shifted too (leave sticky)
1126                 of.guard.eq(temp_s[2]),     # guard
1127                 of.round_bit.eq(temp_s[1]), # round
1128                 of.sticky.eq(temp_s[0]),    # sticky
1129                 self.o.z.e.eq(i.z.e + ediff_n126),
1130             ]
1131
1132         return m
1133
1134
1135 class FPNorm1ModMulti:
1136
1137     def __init__(self, width, single_cycle=True):
1138         self.width = width
1139         self.in_select = Signal(reset_less=True)
1140         self.in_z = FPNumBase(width, False)
1141         self.in_of = Overflow()
1142         self.temp_z = FPNumBase(width, False)
1143         self.temp_of = Overflow()
1144         self.out_z = FPNumBase(width, False)
1145         self.out_of = Overflow()
1146
1147     def elaborate(self, platform):
1148         m = Module()
1149
1150         m.submodules.norm1_out_z = self.out_z
1151         m.submodules.norm1_out_overflow = self.out_of
1152         m.submodules.norm1_temp_z = self.temp_z
1153         m.submodules.norm1_temp_of = self.temp_of
1154         m.submodules.norm1_in_z = self.in_z
1155         m.submodules.norm1_in_overflow = self.in_of
1156
1157         in_z = FPNumBase(self.width, False)
1158         in_of = Overflow()
1159         m.submodules.norm1_insel_z = in_z
1160         m.submodules.norm1_insel_overflow = in_of
1161
1162         # select which of temp or in z/of to use
1163         with m.If(self.in_select):
1164             m.d.comb += in_z.eq(self.in_z)
1165             m.d.comb += in_of.eq(self.in_of)
1166         with m.Else():
1167             m.d.comb += in_z.eq(self.temp_z)
1168             m.d.comb += in_of.eq(self.temp_of)
1169         # initialise out from in (overridden below)
1170         m.d.comb += self.out_z.eq(in_z)
1171         m.d.comb += self.out_of.eq(in_of)
1172         # normalisation increase/decrease conditions
1173         decrease = Signal(reset_less=True)
1174         increase = Signal(reset_less=True)
1175         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
1176         m.d.comb += increase.eq(in_z.exp_lt_n126)
1177         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
1178         # decrease exponent
1179         with m.If(decrease):
1180             m.d.comb += [
1181                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
1182                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
1183                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
1184                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
1185                 self.out_of.round_bit.eq(0),        # reset round bit
1186                 self.out_of.m0.eq(in_of.guard),
1187             ]
1188         # increase exponent
1189         with m.Elif(increase):
1190             m.d.comb += [
1191                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
1192                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
1193                 self.out_of.guard.eq(in_z.m[0]),
1194                 self.out_of.m0.eq(in_z.m[1]),
1195                 self.out_of.round_bit.eq(in_of.guard),
1196                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
1197             ]
1198
1199         return m
1200
1201
1202 class FPNorm1Single(FPState):
1203
1204     def __init__(self, width, id_wid, single_cycle=True):
1205         FPState.__init__(self, "normalise_1")
1206         self.mod = FPNorm1ModSingle(width)
1207         self.o = self.ospec()
1208         self.out_z = FPNumBase(width, False)
1209         self.out_roundz = Signal(reset_less=True)
1210
1211     def ispec(self):
1212         return self.mod.ispec()
1213
1214     def ospec(self):
1215         return self.mod.ospec()
1216
1217     def setup(self, m, i):
1218         """ links module to inputs and outputs
1219         """
1220         self.mod.setup(m, i)
1221
1222     def action(self, m):
1223         m.next = "round"
1224
1225
1226 class FPNorm1Multi(FPState):
1227
1228     def __init__(self, width, id_wid):
1229         FPState.__init__(self, "normalise_1")
1230         self.mod = FPNorm1ModMulti(width)
1231         self.stb = Signal(reset_less=True)
1232         self.ack = Signal(reset=0, reset_less=True)
1233         self.out_norm = Signal(reset_less=True)
1234         self.in_accept = Signal(reset_less=True)
1235         self.temp_z = FPNumBase(width)
1236         self.temp_of = Overflow()
1237         self.out_z = FPNumBase(width)
1238         self.out_roundz = Signal(reset_less=True)
1239
1240     def setup(self, m, in_z, in_of, norm_stb):
1241         """ links module to inputs and outputs
1242         """
1243         self.mod.setup(m, in_z, in_of, norm_stb,
1244                        self.in_accept, self.temp_z, self.temp_of,
1245                        self.out_z, self.out_norm)
1246
1247         m.d.comb += self.stb.eq(norm_stb)
1248         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
1249
1250     def action(self, m):
1251         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
1252         m.d.sync += self.temp_of.eq(self.mod.out_of)
1253         m.d.sync += self.temp_z.eq(self.out_z)
1254         with m.If(self.out_norm):
1255             with m.If(self.in_accept):
1256                 m.d.sync += [
1257                     self.ack.eq(1),
1258                 ]
1259             with m.Else():
1260                 m.d.sync += self.ack.eq(0)
1261         with m.Else():
1262             # normalisation not required (or done).
1263             m.next = "round"
1264             m.d.sync += self.ack.eq(1)
1265             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
1266
1267
1268 class FPNormToPack(FPState):
1269
1270     def __init__(self, width, id_wid):
1271         FPState.__init__(self, "normalise_1")
1272         self.id_wid = id_wid
1273         self.width = width
1274
1275     def ispec(self):
1276         return FPAddStage1Data(self.width, self.id_wid) # Norm1ModSingle ispec
1277
1278     def ospec(self):
1279         return FPPackData(self.width, self.id_wid) # FPPackMod ospec
1280
1281     def setup(self, m, i):
1282         """ links module to inputs and outputs
1283         """
1284
1285         # Normalisation, Rounding Corrections, Pack - in a chain
1286         nmod = FPNorm1ModSingle(self.width, self.id_wid)
1287         rmod = FPRoundMod(self.width, self.id_wid)
1288         cmod = FPCorrectionsMod(self.width, self.id_wid)
1289         pmod = FPPackMod(self.width, self.id_wid)
1290         chain = StageChain([nmod, rmod, cmod, pmod])
1291         chain.setup(m, i)
1292         self.out_z = pmod.ospec()
1293
1294         m.d.sync += self.out_z.mid.eq(pmod.o.mid)
1295         m.d.sync += self.out_z.z.v.eq(pmod.o.z.v) # outputs packed result
1296
1297     def action(self, m):
1298         m.next = "pack_put_z"
1299
1300
1301 class FPRoundData:
1302
1303     def __init__(self, width, id_wid):
1304         self.z = FPNumBase(width, False)
1305         self.mid = Signal(id_wid, reset_less=True)
1306
1307     def eq(self, i):
1308         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1309
1310
1311 class FPRoundMod:
1312
1313     def __init__(self, width, id_wid):
1314         self.width = width
1315         self.id_wid = id_wid
1316         self.i = self.ispec()
1317         self.out_z = self.ospec()
1318
1319     def ispec(self):
1320         return FPNorm1Data(self.width, self.id_wid)
1321
1322     def ospec(self):
1323         return FPRoundData(self.width, self.id_wid)
1324
1325     def process(self, i):
1326         return self.out_z
1327
1328     def setup(self, m, i):
1329         m.submodules.roundz = self
1330         m.d.comb += self.i.eq(i)
1331
1332     def elaborate(self, platform):
1333         m = Module()
1334         m.d.comb += self.out_z.eq(self.i)
1335         with m.If(self.i.roundz):
1336             m.d.comb += self.out_z.z.m.eq(self.i.z.m + 1) # mantissa rounds up
1337             with m.If(self.i.z.m == self.i.z.m1s): # all 1s
1338                 m.d.comb += self.out_z.z.e.eq(self.i.z.e + 1) # exponent up
1339         return m
1340
1341
1342 class FPRound(FPState):
1343
1344     def __init__(self, width, id_wid):
1345         FPState.__init__(self, "round")
1346         self.mod = FPRoundMod(width)
1347         self.out_z = self.ospec()
1348
1349     def ispec(self):
1350         return self.mod.ispec()
1351
1352     def ospec(self):
1353         return self.mod.ospec()
1354
1355     def setup(self, m, i):
1356         """ links module to inputs and outputs
1357         """
1358         self.mod.setup(m, i)
1359
1360         self.idsync(m)
1361         m.d.sync += self.out_z.eq(self.mod.out_z)
1362         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1363
1364     def action(self, m):
1365         m.next = "corrections"
1366
1367
1368 class FPCorrectionsMod:
1369
1370     def __init__(self, width, id_wid):
1371         self.width = width
1372         self.id_wid = id_wid
1373         self.i = self.ispec()
1374         self.out_z = self.ospec()
1375
1376     def ispec(self):
1377         return FPRoundData(self.width, self.id_wid)
1378
1379     def ospec(self):
1380         return FPRoundData(self.width, self.id_wid)
1381
1382     def process(self, i):
1383         return self.out_z
1384
1385     def setup(self, m, i):
1386         """ links module to inputs and outputs
1387         """
1388         m.submodules.corrections = self
1389         m.d.comb += self.i.eq(i)
1390
1391     def elaborate(self, platform):
1392         m = Module()
1393         m.submodules.corr_in_z = self.i.z
1394         m.submodules.corr_out_z = self.out_z.z
1395         m.d.comb += self.out_z.eq(self.i)
1396         with m.If(self.i.z.is_denormalised):
1397             m.d.comb += self.out_z.z.e.eq(self.i.z.N127)
1398         return m
1399
1400
1401 class FPCorrections(FPState):
1402
1403     def __init__(self, width, id_wid):
1404         FPState.__init__(self, "corrections")
1405         self.mod = FPCorrectionsMod(width)
1406         self.out_z = self.ospec()
1407
1408     def ispec(self):
1409         return self.mod.ispec()
1410
1411     def ospec(self):
1412         return self.mod.ospec()
1413
1414     def setup(self, m, in_z):
1415         """ links module to inputs and outputs
1416         """
1417         self.mod.setup(m, in_z)
1418
1419         m.d.sync += self.out_z.eq(self.mod.out_z)
1420         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1421
1422     def action(self, m):
1423         m.next = "pack"
1424
1425
1426 class FPPackData:
1427
1428     def __init__(self, width, id_wid):
1429         self.z = FPNumOut(width, False)
1430         self.mid = Signal(id_wid, reset_less=True)
1431
1432     def eq(self, i):
1433         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1434
1435
1436 class FPPackMod:
1437
1438     def __init__(self, width, id_wid):
1439         self.width = width
1440         self.id_wid = id_wid
1441         self.i = self.ispec()
1442         self.o = self.ospec()
1443
1444     def ispec(self):
1445         return FPRoundData(self.width, self.id_wid)
1446
1447     def ospec(self):
1448         return FPPackData(self.width, self.id_wid)
1449
1450     def process(self, i):
1451         return self.o
1452
1453     def setup(self, m, in_z):
1454         """ links module to inputs and outputs
1455         """
1456         m.submodules.pack = self
1457         m.d.comb += self.i.eq(in_z)
1458
1459     def elaborate(self, platform):
1460         m = Module()
1461         m.submodules.pack_in_z = self.i.z
1462         m.d.comb += self.o.mid.eq(self.i.mid)
1463         with m.If(self.i.z.is_overflowed):
1464             m.d.comb += self.o.z.inf(self.i.z.s)
1465         with m.Else():
1466             m.d.comb += self.o.z.create(self.i.z.s, self.i.z.e, self.i.z.m)
1467         return m
1468
1469
1470 class FPPackData:
1471     def __init__(self, width, id_wid):
1472         self.z = FPNumOut(width, False)
1473         self.mid = Signal(id_wid, reset_less=True)
1474
1475     def eq(self, i):
1476         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1477
1478
1479 class FPPack(FPState):
1480
1481     def __init__(self, width, id_wid):
1482         FPState.__init__(self, "pack")
1483         self.mod = FPPackMod(width)
1484         self.out_z = self.ospec()
1485
1486     def ispec(self):
1487         return self.mod.ispec()
1488
1489     def ospec(self):
1490         return self.mod.ospec()
1491
1492     def setup(self, m, in_z):
1493         """ links module to inputs and outputs
1494         """
1495         self.mod.setup(m, in_z)
1496
1497         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1498         m.d.sync += self.out_z.mid.eq(self.mod.o.mid)
1499
1500     def action(self, m):
1501         m.next = "pack_put_z"
1502
1503
1504 class FPPutZ(FPState):
1505
1506     def __init__(self, state, in_z, out_z, in_mid, out_mid, to_state=None):
1507         FPState.__init__(self, state)
1508         if to_state is None:
1509             to_state = "get_ops"
1510         self.to_state = to_state
1511         self.in_z = in_z
1512         self.out_z = out_z
1513         self.in_mid = in_mid
1514         self.out_mid = out_mid
1515
1516     def action(self, m):
1517         if self.in_mid is not None:
1518             m.d.sync += self.out_mid.eq(self.in_mid)
1519         m.d.sync += [
1520           self.out_z.z.v.eq(self.in_z.v)
1521         ]
1522         with m.If(self.out_z.z.stb & self.out_z.z.ack):
1523             m.d.sync += self.out_z.z.stb.eq(0)
1524             m.next = self.to_state
1525         with m.Else():
1526             m.d.sync += self.out_z.z.stb.eq(1)
1527
1528
1529 class FPPutZIdx(FPState):
1530
1531     def __init__(self, state, in_z, out_zs, in_mid, to_state=None):
1532         FPState.__init__(self, state)
1533         if to_state is None:
1534             to_state = "get_ops"
1535         self.to_state = to_state
1536         self.in_z = in_z
1537         self.out_zs = out_zs
1538         self.in_mid = in_mid
1539
1540     def action(self, m):
1541         outz_stb = Signal(reset_less=True)
1542         outz_ack = Signal(reset_less=True)
1543         m.d.comb += [outz_stb.eq(self.out_zs[self.in_mid].stb),
1544                      outz_ack.eq(self.out_zs[self.in_mid].ack),
1545                     ]
1546         m.d.sync += [
1547           self.out_zs[self.in_mid].v.eq(self.in_z.v)
1548         ]
1549         with m.If(outz_stb & outz_ack):
1550             m.d.sync += self.out_zs[self.in_mid].stb.eq(0)
1551             m.next = self.to_state
1552         with m.Else():
1553             m.d.sync += self.out_zs[self.in_mid].stb.eq(1)
1554
1555 class FPADDBaseData:
1556
1557     def __init__(self, width, id_wid):
1558         self.width = width
1559         self.id_wid = id_wid
1560         self.a  = Signal(width)
1561         self.b  = Signal(width)
1562         self.mid = Signal(id_wid, reset_less=True)
1563
1564     def eq(self, i):
1565         return [self.a.eq(i.a), self.b.eq(i.b), self.mid.eq(i.mid)]
1566
1567
1568 class FPOpData:
1569     def __init__(self, width, id_wid):
1570         self.z = FPOp(width)
1571         self.mid = Signal(id_wid, reset_less=True)
1572
1573     def eq(self, i):
1574         return [self.z.eq(i.z), self.mid.eq(i.mid)]
1575
1576
1577 class FPADDBaseMod:
1578
1579     def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1580         """ IEEE754 FP Add
1581
1582             * width: bit-width of IEEE754.  supported: 16, 32, 64
1583             * id_wid: an identifier that is sync-connected to the input
1584             * single_cycle: True indicates each stage to complete in 1 clock
1585             * compact: True indicates a reduced number of stages
1586         """
1587         self.width = width
1588         self.id_wid = id_wid
1589         self.single_cycle = single_cycle
1590         self.compact = compact
1591
1592         self.in_t = Trigger()
1593         self.i = self.ispec()
1594         self.o = self.ospec()
1595
1596         self.states = []
1597
1598     def ispec(self):
1599         return FPADDBaseData(self.width, self.id_wid)
1600
1601     def ospec(self):
1602         return FPOpData(self.width, self.id_wid)
1603
1604     def add_state(self, state):
1605         self.states.append(state)
1606         return state
1607
1608     def get_fragment(self, platform=None):
1609         """ creates the HDL code-fragment for FPAdd
1610         """
1611         m = Module()
1612         m.submodules.out_z = self.o.z
1613         m.submodules.in_t = self.in_t
1614         if self.compact:
1615             self.get_compact_fragment(m, platform)
1616         else:
1617             self.get_longer_fragment(m, platform)
1618
1619         with m.FSM() as fsm:
1620
1621             for state in self.states:
1622                 with m.State(state.state_from):
1623                     state.action(m)
1624
1625         return m
1626
1627     def get_longer_fragment(self, m, platform=None):
1628
1629         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1630                                       self.width))
1631         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1632         a = get.out_op1
1633         b = get.out_op2
1634
1635         sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1636         sc.setup(m, a, b, self.in_mid)
1637
1638         dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1639         dn.setup(m, a, b, sc.in_mid)
1640
1641         if self.single_cycle:
1642             alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1643             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1644         else:
1645             alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1646             alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1647
1648         add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1649         add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1650
1651         add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1652         add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1653
1654         if self.single_cycle:
1655             n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1656             n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1657         else:
1658             n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1659             n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1660
1661         rn = self.add_state(FPRound(self.width, self.id_wid))
1662         rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1663
1664         cor = self.add_state(FPCorrections(self.width, self.id_wid))
1665         cor.setup(m, rn.out_z, rn.in_mid)
1666
1667         pa = self.add_state(FPPack(self.width, self.id_wid))
1668         pa.setup(m, cor.out_z, rn.in_mid)
1669
1670         ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1671                                     pa.in_mid, self.out_mid))
1672
1673         pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1674                                     pa.in_mid, self.out_mid))
1675
1676     def get_compact_fragment(self, m, platform=None):
1677
1678         get = self.add_state(FPGet2Op("get_ops", "special_cases",
1679                                       self.width, self.id_wid))
1680         get.setup(m, self.i, self.in_t.stb, self.in_t.ack)
1681
1682         sc = self.add_state(FPAddSpecialCasesDeNorm(self.width, self.id_wid))
1683         sc.setup(m, get.o)
1684
1685         alm = self.add_state(FPAddAlignSingleAdd(self.width, self.id_wid))
1686         alm.setup(m, sc.o)
1687
1688         n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1689         n1.setup(m, alm.a1o)
1690
1691         ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z.z, self.o,
1692                                     n1.out_z.mid, self.o.mid))
1693
1694         pz = self.add_state(FPPutZ("put_z", sc.out_z.z, self.o,
1695                                     sc.o.mid, self.o.mid))
1696
1697
1698 class FPADDBase(FPState):
1699
1700     def __init__(self, width, id_wid=None, single_cycle=False):
1701         """ IEEE754 FP Add
1702
1703             * width: bit-width of IEEE754.  supported: 16, 32, 64
1704             * id_wid: an identifier that is sync-connected to the input
1705             * single_cycle: True indicates each stage to complete in 1 clock
1706         """
1707         FPState.__init__(self, "fpadd")
1708         self.width = width
1709         self.single_cycle = single_cycle
1710         self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1711         self.o = self.ospec()
1712
1713         self.in_t = Trigger()
1714         self.i = self.ispec()
1715
1716         self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1717         self.in_accept = Signal(reset_less=True)
1718         self.add_stb = Signal(reset_less=True)
1719         self.add_ack = Signal(reset=0, reset_less=True)
1720
1721     def ispec(self):
1722         return self.mod.ispec()
1723
1724     def ospec(self):
1725         return self.mod.ospec()
1726
1727     def setup(self, m, i, add_stb, in_mid):
1728         m.d.comb += [self.i.eq(i),
1729                      self.mod.i.eq(self.i),
1730                      self.z_done.eq(self.mod.o.z.trigger),
1731                      #self.add_stb.eq(add_stb),
1732                      self.mod.in_t.stb.eq(self.in_t.stb),
1733                      self.in_t.ack.eq(self.mod.in_t.ack),
1734                      self.o.mid.eq(self.mod.o.mid),
1735                      self.o.z.v.eq(self.mod.o.z.v),
1736                      self.o.z.stb.eq(self.mod.o.z.stb),
1737                      self.mod.o.z.ack.eq(self.o.z.ack),
1738                     ]
1739
1740         m.d.sync += self.add_stb.eq(add_stb)
1741         m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1742         m.d.sync += self.o.z.ack.eq(0) # likewise
1743         #m.d.sync += self.in_t.stb.eq(0)
1744
1745         m.submodules.fpadd = self.mod
1746
1747     def action(self, m):
1748
1749         # in_accept is set on incoming strobe HIGH and ack LOW.
1750         m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1751
1752         #with m.If(self.in_t.ack):
1753         #    m.d.sync += self.in_t.stb.eq(0)
1754         with m.If(~self.z_done):
1755             # not done: test for accepting an incoming operand pair
1756             with m.If(self.in_accept):
1757                 m.d.sync += [
1758                     self.add_ack.eq(1), # acknowledge receipt...
1759                     self.in_t.stb.eq(1), # initiate add
1760                 ]
1761             with m.Else():
1762                 m.d.sync += [self.add_ack.eq(0),
1763                              self.in_t.stb.eq(0),
1764                              self.o.z.ack.eq(1),
1765                             ]
1766         with m.Else():
1767             # done: acknowledge, and write out id and value
1768             m.d.sync += [self.add_ack.eq(1),
1769                          self.in_t.stb.eq(0)
1770                         ]
1771             m.next = "put_z"
1772
1773             return
1774
1775             if self.in_mid is not None:
1776                 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1777
1778             m.d.sync += [
1779               self.out_z.v.eq(self.mod.out_z.v)
1780             ]
1781             # move to output state on detecting z ack
1782             with m.If(self.out_z.trigger):
1783                 m.d.sync += self.out_z.stb.eq(0)
1784                 m.next = "put_z"
1785             with m.Else():
1786                 m.d.sync += self.out_z.stb.eq(1)
1787
1788
1789 class ResArray:
1790     def __init__(self, width, id_wid):
1791         self.width = width
1792         self.id_wid = id_wid
1793         res = []
1794         for i in range(rs_sz):
1795             out_z = FPOp(width)
1796             out_z.name = "out_z_%d" % i
1797             res.append(out_z)
1798         self.res = Array(res)
1799         self.in_z = FPOp(width)
1800         self.in_mid = Signal(self.id_wid, reset_less=True)
1801
1802     def setup(self, m, in_z, in_mid):
1803         m.d.comb += [self.in_z.eq(in_z),
1804                      self.in_mid.eq(in_mid)]
1805
1806     def get_fragment(self, platform=None):
1807         """ creates the HDL code-fragment for FPAdd
1808         """
1809         m = Module()
1810         m.submodules.res_in_z = self.in_z
1811         m.submodules += self.res
1812
1813         return m
1814
1815     def ports(self):
1816         res = []
1817         for z in self.res:
1818             res += z.ports()
1819         return res
1820
1821
1822 class FPADD(FPID):
1823     """ FPADD: stages as follows:
1824
1825         FPGetOp (a)
1826            |
1827         FPGetOp (b)
1828            |
1829         FPAddBase---> FPAddBaseMod
1830            |            |
1831         PutZ          GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1832
1833         FPAddBase is tricky: it is both a stage and *has* stages.
1834         Connection to FPAddBaseMod therefore requires an in stb/ack
1835         and an out stb/ack.  Just as with Add1-Norm1 interaction, FPGetOp
1836         needs to be the thing that raises the incoming stb.
1837     """
1838
1839     def __init__(self, width, id_wid=None, single_cycle=False, rs_sz=2):
1840         """ IEEE754 FP Add
1841
1842             * width: bit-width of IEEE754.  supported: 16, 32, 64
1843             * id_wid: an identifier that is sync-connected to the input
1844             * single_cycle: True indicates each stage to complete in 1 clock
1845         """
1846         self.width = width
1847         self.id_wid = id_wid
1848         self.single_cycle = single_cycle
1849
1850         #self.out_z = FPOp(width)
1851         self.ids = FPID(id_wid)
1852
1853         rs = []
1854         for i in range(rs_sz):
1855             in_a  = FPOp(width)
1856             in_b  = FPOp(width)
1857             in_a.name = "in_a_%d" % i
1858             in_b.name = "in_b_%d" % i
1859             rs.append((in_a, in_b))
1860         self.rs = Array(rs)
1861
1862         res = []
1863         for i in range(rs_sz):
1864             out_z = FPOp(width)
1865             out_z.name = "out_z_%d" % i
1866             res.append(out_z)
1867         self.res = Array(res)
1868
1869         self.states = []
1870
1871     def add_state(self, state):
1872         self.states.append(state)
1873         return state
1874
1875     def get_fragment(self, platform=None):
1876         """ creates the HDL code-fragment for FPAdd
1877         """
1878         m = Module()
1879         m.submodules += self.rs
1880
1881         in_a = self.rs[0][0]
1882         in_b = self.rs[0][1]
1883
1884         geta = self.add_state(FPGetOp("get_a", "get_b",
1885                                       in_a, self.width))
1886         geta.setup(m, in_a)
1887         a = geta.out_op
1888
1889         getb = self.add_state(FPGetOp("get_b", "fpadd",
1890                                       in_b, self.width))
1891         getb.setup(m, in_b)
1892         b = getb.out_op
1893
1894         ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1895         ab = self.add_state(ab)
1896         abd = ab.ispec() # create an input spec object for FPADDBase
1897         m.d.sync += [abd.a.eq(a), abd.b.eq(b), abd.mid.eq(self.ids.in_mid)]
1898         ab.setup(m, abd, getb.out_decode, self.ids.in_mid)
1899         o = ab.o
1900
1901         pz = self.add_state(FPPutZIdx("put_z", o.z, self.res,
1902                                     o.mid, "get_a"))
1903
1904         with m.FSM() as fsm:
1905
1906             for state in self.states:
1907                 with m.State(state.state_from):
1908                     state.action(m)
1909
1910         return m
1911
1912
1913 if __name__ == "__main__":
1914     if True:
1915         alu = FPADD(width=32, id_wid=5, single_cycle=True)
1916         main(alu, ports=alu.rs[0][0].ports() + \
1917                         alu.rs[0][1].ports() + \
1918                         alu.res[0].ports() + \
1919                         [alu.ids.in_mid, alu.ids.out_mid])
1920     else:
1921         alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1922         main(alu, ports=[alu.in_a, alu.in_b] + \
1923                         alu.in_t.ports() + \
1924                         alu.out_z.ports() + \
1925                         [alu.in_mid, alu.out_mid])
1926
1927
1928     # works... but don't use, just do "python fname.py convert -t v"
1929     #print (verilog.convert(alu, ports=[
1930     #                        ports=alu.in_a.ports() + \
1931     #                              alu.in_b.ports() + \
1932     #                              alu.out_z.ports())