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[ieee754fpu.git] / src / add / nmigen_add_experiment.py
1 # IEEE Floating Point Adder (Single Precision)
2 # Copyright (C) Jonathan P Dawson 2013
3 # 2013-12-12
4
5 from nmigen import Module, Signal, Cat, Mux
6 from nmigen.lib.coding import PriorityEncoder
7 from nmigen.cli import main, verilog
8
9 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
10 from fpbase import MultiShiftRMerge, Trigger
11 #from fpbase import FPNumShiftMultiRight
12
13 class FPState(FPBase):
14 def __init__(self, state_from):
15 self.state_from = state_from
16
17 def set_inputs(self, inputs):
18 self.inputs = inputs
19 for k,v in inputs.items():
20 setattr(self, k, v)
21
22 def set_outputs(self, outputs):
23 self.outputs = outputs
24 for k,v in outputs.items():
25 setattr(self, k, v)
26
27
28 class FPGetOpMod:
29 def __init__(self, width):
30 self.in_op = FPOp(width)
31 self.out_op = Signal(width)
32 self.out_decode = Signal(reset_less=True)
33
34 def elaborate(self, platform):
35 m = Module()
36 m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
37 m.submodules.get_op_in = self.in_op
38 #m.submodules.get_op_out = self.out_op
39 with m.If(self.out_decode):
40 m.d.comb += [
41 self.out_op.eq(self.in_op.v),
42 ]
43 return m
44
45
46 class FPGetOp(FPState):
47 """ gets operand
48 """
49
50 def __init__(self, in_state, out_state, in_op, width):
51 FPState.__init__(self, in_state)
52 self.out_state = out_state
53 self.mod = FPGetOpMod(width)
54 self.in_op = in_op
55 self.out_op = Signal(width)
56 self.out_decode = Signal(reset_less=True)
57
58 def setup(self, m, in_op):
59 """ links module to inputs and outputs
60 """
61 setattr(m.submodules, self.state_from, self.mod)
62 m.d.comb += self.mod.in_op.copy(in_op)
63 #m.d.comb += self.out_op.eq(self.mod.out_op)
64 m.d.comb += self.out_decode.eq(self.mod.out_decode)
65
66 def action(self, m):
67 with m.If(self.out_decode):
68 m.next = self.out_state
69 m.d.sync += [
70 self.in_op.ack.eq(0),
71 self.out_op.eq(self.mod.out_op)
72 ]
73 with m.Else():
74 m.d.sync += self.in_op.ack.eq(1)
75
76
77 class FPGet2OpMod(Trigger):
78 def __init__(self, width):
79 Trigger.__init__(self)
80 self.in_op1 = Signal(width, reset_less=True)
81 self.in_op2 = Signal(width, reset_less=True)
82 self.out_op1 = FPNumIn(None, width)
83 self.out_op2 = FPNumIn(None, width)
84
85 def elaborate(self, platform):
86 m = Trigger.elaborate(self, platform)
87 #m.submodules.get_op_in = self.in_op
88 m.submodules.get_op1_out = self.out_op1
89 m.submodules.get_op2_out = self.out_op2
90 with m.If(self.trigger):
91 m.d.comb += [
92 self.out_op1.decode(self.in_op1),
93 self.out_op2.decode(self.in_op2),
94 ]
95 return m
96
97
98 class FPGet2Op(FPState):
99 """ gets operands
100 """
101
102 def __init__(self, in_state, out_state, in_op1, in_op2, width):
103 FPState.__init__(self, in_state)
104 self.out_state = out_state
105 self.mod = FPGet2OpMod(width)
106 self.in_op1 = in_op1
107 self.in_op2 = in_op2
108 self.out_op1 = FPNumIn(None, width)
109 self.out_op2 = FPNumIn(None, width)
110 self.in_stb = Signal(reset_less=True)
111 self.out_ack = Signal(reset_less=True)
112 self.out_decode = Signal(reset_less=True)
113
114 def setup(self, m, in_op1, in_op2, in_stb, in_ack):
115 """ links module to inputs and outputs
116 """
117 m.submodules.get_ops = self.mod
118 m.d.comb += self.mod.in_op1.eq(in_op1)
119 m.d.comb += self.mod.in_op2.eq(in_op2)
120 m.d.comb += self.mod.stb.eq(in_stb)
121 m.d.comb += self.out_ack.eq(self.mod.ack)
122 m.d.comb += self.out_decode.eq(self.mod.trigger)
123 m.d.comb += in_ack.eq(self.mod.ack)
124
125 def action(self, m):
126 with m.If(self.out_decode):
127 m.next = self.out_state
128 m.d.sync += [
129 self.mod.ack.eq(0),
130 #self.out_op1.v.eq(self.mod.out_op1.v),
131 #self.out_op2.v.eq(self.mod.out_op2.v),
132 self.out_op1.copy(self.mod.out_op1),
133 self.out_op2.copy(self.mod.out_op2)
134 ]
135 with m.Else():
136 m.d.sync += self.mod.ack.eq(1)
137
138
139 class FPAddSpecialCasesMod:
140 """ special cases: NaNs, infs, zeros, denormalised
141 NOTE: some of these are unique to add. see "Special Operations"
142 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
143 """
144
145 def __init__(self, width):
146 self.in_a = FPNumBase(width)
147 self.in_b = FPNumBase(width)
148 self.out_z = FPNumOut(width, False)
149 self.out_do_z = Signal(reset_less=True)
150
151 def elaborate(self, platform):
152 m = Module()
153
154 m.submodules.sc_in_a = self.in_a
155 m.submodules.sc_in_b = self.in_b
156 m.submodules.sc_out_z = self.out_z
157
158 s_nomatch = Signal()
159 m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
160
161 m_match = Signal()
162 m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
163
164 # if a is NaN or b is NaN return NaN
165 with m.If(self.in_a.is_nan | self.in_b.is_nan):
166 m.d.comb += self.out_do_z.eq(1)
167 m.d.comb += self.out_z.nan(0)
168
169 # XXX WEIRDNESS for FP16 non-canonical NaN handling
170 # under review
171
172 ## if a is zero and b is NaN return -b
173 #with m.If(a.is_zero & (a.s==0) & b.is_nan):
174 # m.d.comb += self.out_do_z.eq(1)
175 # m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
176
177 ## if b is zero and a is NaN return -a
178 #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
179 # m.d.comb += self.out_do_z.eq(1)
180 # m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
181
182 ## if a is -zero and b is NaN return -b
183 #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
184 # m.d.comb += self.out_do_z.eq(1)
185 # m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
186
187 ## if b is -zero and a is NaN return -a
188 #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
189 # m.d.comb += self.out_do_z.eq(1)
190 # m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
191
192 # if a is inf return inf (or NaN)
193 with m.Elif(self.in_a.is_inf):
194 m.d.comb += self.out_do_z.eq(1)
195 m.d.comb += self.out_z.inf(self.in_a.s)
196 # if a is inf and signs don't match return NaN
197 with m.If(self.in_b.exp_128 & s_nomatch):
198 m.d.comb += self.out_z.nan(0)
199
200 # if b is inf return inf
201 with m.Elif(self.in_b.is_inf):
202 m.d.comb += self.out_do_z.eq(1)
203 m.d.comb += self.out_z.inf(self.in_b.s)
204
205 # if a is zero and b zero return signed-a/b
206 with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
207 m.d.comb += self.out_do_z.eq(1)
208 m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
209 self.in_b.e,
210 self.in_b.m[3:-1])
211
212 # if a is zero return b
213 with m.Elif(self.in_a.is_zero):
214 m.d.comb += self.out_do_z.eq(1)
215 m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
216 self.in_b.m[3:-1])
217
218 # if b is zero return a
219 with m.Elif(self.in_b.is_zero):
220 m.d.comb += self.out_do_z.eq(1)
221 m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
222 self.in_a.m[3:-1])
223
224 # if a equal to -b return zero (+ve zero)
225 with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
226 m.d.comb += self.out_do_z.eq(1)
227 m.d.comb += self.out_z.zero(0)
228
229 # Denormalised Number checks
230 with m.Else():
231 m.d.comb += self.out_do_z.eq(0)
232
233 return m
234
235
236 class FPID:
237 def __init__(self, id_wid):
238 self.id_wid = id_wid
239 if self.id_wid:
240 self.in_mid = Signal(id_wid, reset_less=True)
241 self.out_mid = Signal(id_wid, reset_less=True)
242 else:
243 self.in_mid = None
244 self.out_mid = None
245
246 def idsync(self, m):
247 if self.id_wid is not None:
248 m.d.sync += self.out_mid.eq(self.in_mid)
249
250
251 class FPAddSpecialCases(FPState, FPID):
252 """ special cases: NaNs, infs, zeros, denormalised
253 NOTE: some of these are unique to add. see "Special Operations"
254 https://steve.hollasch.net/cgindex/coding/ieeefloat.html
255 """
256
257 def __init__(self, width, id_wid):
258 FPState.__init__(self, "special_cases")
259 FPID.__init__(self, id_wid)
260 self.mod = FPAddSpecialCasesMod(width)
261 self.out_z = FPNumOut(width, False)
262 self.out_do_z = Signal(reset_less=True)
263
264 def setup(self, m, in_a, in_b, in_mid):
265 """ links module to inputs and outputs
266 """
267 m.submodules.specialcases = self.mod
268 m.d.comb += self.mod.in_a.copy(in_a)
269 m.d.comb += self.mod.in_b.copy(in_b)
270 #m.d.comb += self.out_z.v.eq(self.mod.out_z.v)
271 m.d.comb += self.out_do_z.eq(self.mod.out_do_z)
272 if self.in_mid is not None:
273 m.d.comb += self.in_mid.eq(in_mid)
274
275 def action(self, m):
276 self.idsync(m)
277 with m.If(self.out_do_z):
278 m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
279 m.next = "put_z"
280 with m.Else():
281 m.next = "denormalise"
282
283
284 class FPAddDeNormMod(FPState):
285
286 def __init__(self, width):
287 self.in_a = FPNumBase(width)
288 self.in_b = FPNumBase(width)
289 self.out_a = FPNumBase(width)
290 self.out_b = FPNumBase(width)
291
292 def elaborate(self, platform):
293 m = Module()
294 m.submodules.denorm_in_a = self.in_a
295 m.submodules.denorm_in_b = self.in_b
296 m.submodules.denorm_out_a = self.out_a
297 m.submodules.denorm_out_b = self.out_b
298 # hmmm, don't like repeating identical code
299 m.d.comb += self.out_a.copy(self.in_a)
300 with m.If(self.in_a.exp_n127):
301 m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
302 with m.Else():
303 m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
304
305 m.d.comb += self.out_b.copy(self.in_b)
306 with m.If(self.in_b.exp_n127):
307 m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
308 with m.Else():
309 m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
310
311 return m
312
313
314 class FPAddDeNorm(FPState, FPID):
315
316 def __init__(self, width, id_wid):
317 FPState.__init__(self, "denormalise")
318 FPID.__init__(self, id_wid)
319 self.mod = FPAddDeNormMod(width)
320 self.out_a = FPNumBase(width)
321 self.out_b = FPNumBase(width)
322
323 def setup(self, m, in_a, in_b, in_mid):
324 """ links module to inputs and outputs
325 """
326 m.submodules.denormalise = self.mod
327 m.d.comb += self.mod.in_a.copy(in_a)
328 m.d.comb += self.mod.in_b.copy(in_b)
329 if self.in_mid is not None:
330 m.d.comb += self.in_mid.eq(in_mid)
331
332 def action(self, m):
333 self.idsync(m)
334 # Denormalised Number checks
335 m.next = "align"
336 m.d.sync += self.out_a.copy(self.mod.out_a)
337 m.d.sync += self.out_b.copy(self.mod.out_b)
338
339
340 class FPAddAlignMultiMod(FPState):
341
342 def __init__(self, width):
343 self.in_a = FPNumBase(width)
344 self.in_b = FPNumBase(width)
345 self.out_a = FPNumIn(None, width)
346 self.out_b = FPNumIn(None, width)
347 self.exp_eq = Signal(reset_less=True)
348
349 def elaborate(self, platform):
350 # This one however (single-cycle) will do the shift
351 # in one go.
352
353 m = Module()
354
355 m.submodules.align_in_a = self.in_a
356 m.submodules.align_in_b = self.in_b
357 m.submodules.align_out_a = self.out_a
358 m.submodules.align_out_b = self.out_b
359
360 # NOTE: this does *not* do single-cycle multi-shifting,
361 # it *STAYS* in the align state until exponents match
362
363 # exponent of a greater than b: shift b down
364 m.d.comb += self.exp_eq.eq(0)
365 m.d.comb += self.out_a.copy(self.in_a)
366 m.d.comb += self.out_b.copy(self.in_b)
367 agtb = Signal(reset_less=True)
368 altb = Signal(reset_less=True)
369 m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
370 m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
371 with m.If(agtb):
372 m.d.comb += self.out_b.shift_down(self.in_b)
373 # exponent of b greater than a: shift a down
374 with m.Elif(altb):
375 m.d.comb += self.out_a.shift_down(self.in_a)
376 # exponents equal: move to next stage.
377 with m.Else():
378 m.d.comb += self.exp_eq.eq(1)
379 return m
380
381
382 class FPAddAlignMulti(FPState, FPID):
383
384 def __init__(self, width, id_wid):
385 FPID.__init__(self, id_wid)
386 FPState.__init__(self, "align")
387 self.mod = FPAddAlignMultiMod(width)
388 self.out_a = FPNumIn(None, width)
389 self.out_b = FPNumIn(None, width)
390 self.exp_eq = Signal(reset_less=True)
391
392 def setup(self, m, in_a, in_b, in_mid):
393 """ links module to inputs and outputs
394 """
395 m.submodules.align = self.mod
396 m.d.comb += self.mod.in_a.copy(in_a)
397 m.d.comb += self.mod.in_b.copy(in_b)
398 #m.d.comb += self.out_a.copy(self.mod.out_a)
399 #m.d.comb += self.out_b.copy(self.mod.out_b)
400 m.d.comb += self.exp_eq.eq(self.mod.exp_eq)
401 if self.in_mid is not None:
402 m.d.comb += self.in_mid.eq(in_mid)
403
404 def action(self, m):
405 self.idsync(m)
406 m.d.sync += self.out_a.copy(self.mod.out_a)
407 m.d.sync += self.out_b.copy(self.mod.out_b)
408 with m.If(self.exp_eq):
409 m.next = "add_0"
410
411
412 class FPAddAlignSingleMod:
413
414 def __init__(self, width):
415 self.width = width
416 self.in_a = FPNumBase(width)
417 self.in_b = FPNumBase(width)
418 self.out_a = FPNumIn(None, width)
419 self.out_b = FPNumIn(None, width)
420
421 def elaborate(self, platform):
422 """ Aligns A against B or B against A, depending on which has the
423 greater exponent. This is done in a *single* cycle using
424 variable-width bit-shift
425
426 the shifter used here is quite expensive in terms of gates.
427 Mux A or B in (and out) into temporaries, as only one of them
428 needs to be aligned against the other
429 """
430 m = Module()
431
432 m.submodules.align_in_a = self.in_a
433 m.submodules.align_in_b = self.in_b
434 m.submodules.align_out_a = self.out_a
435 m.submodules.align_out_b = self.out_b
436
437 # temporary (muxed) input and output to be shifted
438 t_inp = FPNumBase(self.width)
439 t_out = FPNumIn(None, self.width)
440 espec = (len(self.in_a.e), True)
441 msr = MultiShiftRMerge(self.in_a.m_width, espec)
442 m.submodules.align_t_in = t_inp
443 m.submodules.align_t_out = t_out
444 m.submodules.multishift_r = msr
445
446 ediff = Signal(espec, reset_less=True)
447 ediffr = Signal(espec, reset_less=True)
448 tdiff = Signal(espec, reset_less=True)
449 elz = Signal(reset_less=True)
450 egz = Signal(reset_less=True)
451
452 # connect multi-shifter to t_inp/out mantissa (and tdiff)
453 m.d.comb += msr.inp.eq(t_inp.m)
454 m.d.comb += msr.diff.eq(tdiff)
455 m.d.comb += t_out.m.eq(msr.m)
456 m.d.comb += t_out.e.eq(t_inp.e + tdiff)
457 m.d.comb += t_out.s.eq(t_inp.s)
458
459 m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
460 m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
461 m.d.comb += elz.eq(self.in_a.e < self.in_b.e)
462 m.d.comb += egz.eq(self.in_a.e > self.in_b.e)
463
464 # default: A-exp == B-exp, A and B untouched (fall through)
465 m.d.comb += self.out_a.copy(self.in_a)
466 m.d.comb += self.out_b.copy(self.in_b)
467 # only one shifter (muxed)
468 #m.d.comb += t_out.shift_down_multi(tdiff, t_inp)
469 # exponent of a greater than b: shift b down
470 with m.If(egz):
471 m.d.comb += [t_inp.copy(self.in_b),
472 tdiff.eq(ediff),
473 self.out_b.copy(t_out),
474 self.out_b.s.eq(self.in_b.s), # whoops forgot sign
475 ]
476 # exponent of b greater than a: shift a down
477 with m.Elif(elz):
478 m.d.comb += [t_inp.copy(self.in_a),
479 tdiff.eq(ediffr),
480 self.out_a.copy(t_out),
481 self.out_a.s.eq(self.in_a.s), # whoops forgot sign
482 ]
483 return m
484
485
486 class FPAddAlignSingle(FPState, FPID):
487
488 def __init__(self, width, id_wid):
489 FPState.__init__(self, "align")
490 FPID.__init__(self, id_wid)
491 self.mod = FPAddAlignSingleMod(width)
492 self.out_a = FPNumIn(None, width)
493 self.out_b = FPNumIn(None, width)
494
495 def setup(self, m, in_a, in_b, in_mid):
496 """ links module to inputs and outputs
497 """
498 m.submodules.align = self.mod
499 m.d.comb += self.mod.in_a.copy(in_a)
500 m.d.comb += self.mod.in_b.copy(in_b)
501 if self.in_mid is not None:
502 m.d.comb += self.in_mid.eq(in_mid)
503
504 def action(self, m):
505 self.idsync(m)
506 # NOTE: could be done as comb
507 m.d.sync += self.out_a.copy(self.mod.out_a)
508 m.d.sync += self.out_b.copy(self.mod.out_b)
509 m.next = "add_0"
510
511
512 class FPAddStage0Mod:
513
514 def __init__(self, width):
515 self.in_a = FPNumBase(width)
516 self.in_b = FPNumBase(width)
517 self.in_z = FPNumBase(width, False)
518 self.out_z = FPNumBase(width, False)
519 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
520
521 def elaborate(self, platform):
522 m = Module()
523 m.submodules.add0_in_a = self.in_a
524 m.submodules.add0_in_b = self.in_b
525 m.submodules.add0_out_z = self.out_z
526
527 m.d.comb += self.out_z.e.eq(self.in_a.e)
528
529 # store intermediate tests (and zero-extended mantissas)
530 seq = Signal(reset_less=True)
531 mge = Signal(reset_less=True)
532 am0 = Signal(len(self.in_a.m)+1, reset_less=True)
533 bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
534 m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
535 mge.eq(self.in_a.m >= self.in_b.m),
536 am0.eq(Cat(self.in_a.m, 0)),
537 bm0.eq(Cat(self.in_b.m, 0))
538 ]
539 # same-sign (both negative or both positive) add mantissas
540 with m.If(seq):
541 m.d.comb += [
542 self.out_tot.eq(am0 + bm0),
543 self.out_z.s.eq(self.in_a.s)
544 ]
545 # a mantissa greater than b, use a
546 with m.Elif(mge):
547 m.d.comb += [
548 self.out_tot.eq(am0 - bm0),
549 self.out_z.s.eq(self.in_a.s)
550 ]
551 # b mantissa greater than a, use b
552 with m.Else():
553 m.d.comb += [
554 self.out_tot.eq(bm0 - am0),
555 self.out_z.s.eq(self.in_b.s)
556 ]
557 return m
558
559
560 class FPAddStage0(FPState, FPID):
561 """ First stage of add. covers same-sign (add) and subtract
562 special-casing when mantissas are greater or equal, to
563 give greatest accuracy.
564 """
565
566 def __init__(self, width, id_wid):
567 FPState.__init__(self, "add_0")
568 FPID.__init__(self, id_wid)
569 self.mod = FPAddStage0Mod(width)
570 self.out_z = FPNumBase(width, False)
571 self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
572
573 def setup(self, m, in_a, in_b, in_mid):
574 """ links module to inputs and outputs
575 """
576 m.submodules.add0 = self.mod
577 m.d.comb += self.mod.in_a.copy(in_a)
578 m.d.comb += self.mod.in_b.copy(in_b)
579 if self.in_mid is not None:
580 m.d.comb += self.in_mid.eq(in_mid)
581
582 def action(self, m):
583 self.idsync(m)
584 # NOTE: these could be done as combinatorial (merge add0+add1)
585 m.d.sync += self.out_z.copy(self.mod.out_z)
586 m.d.sync += self.out_tot.eq(self.mod.out_tot)
587 m.next = "add_1"
588
589
590 class FPAddStage1Mod(FPState):
591 """ Second stage of add: preparation for normalisation.
592 detects when tot sum is too big (tot[27] is kinda a carry bit)
593 """
594
595 def __init__(self, width):
596 self.out_norm = Signal(reset_less=True)
597 self.in_z = FPNumBase(width, False)
598 self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
599 self.out_z = FPNumBase(width, False)
600 self.out_of = Overflow()
601
602 def elaborate(self, platform):
603 m = Module()
604 #m.submodules.norm1_in_overflow = self.in_of
605 #m.submodules.norm1_out_overflow = self.out_of
606 #m.submodules.norm1_in_z = self.in_z
607 #m.submodules.norm1_out_z = self.out_z
608 m.d.comb += self.out_z.copy(self.in_z)
609 # tot[27] gets set when the sum overflows. shift result down
610 with m.If(self.in_tot[-1]):
611 m.d.comb += [
612 self.out_z.m.eq(self.in_tot[4:]),
613 self.out_of.m0.eq(self.in_tot[4]),
614 self.out_of.guard.eq(self.in_tot[3]),
615 self.out_of.round_bit.eq(self.in_tot[2]),
616 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
617 self.out_z.e.eq(self.in_z.e + 1)
618 ]
619 # tot[27] zero case
620 with m.Else():
621 m.d.comb += [
622 self.out_z.m.eq(self.in_tot[3:]),
623 self.out_of.m0.eq(self.in_tot[3]),
624 self.out_of.guard.eq(self.in_tot[2]),
625 self.out_of.round_bit.eq(self.in_tot[1]),
626 self.out_of.sticky.eq(self.in_tot[0])
627 ]
628 return m
629
630
631 class FPAddStage1(FPState, FPID):
632
633 def __init__(self, width, id_wid):
634 FPState.__init__(self, "add_1")
635 FPID.__init__(self, id_wid)
636 self.mod = FPAddStage1Mod(width)
637 self.out_z = FPNumBase(width, False)
638 self.out_of = Overflow()
639 self.norm_stb = Signal()
640
641 def setup(self, m, in_tot, in_z, in_mid):
642 """ links module to inputs and outputs
643 """
644 m.submodules.add1 = self.mod
645 m.submodules.add1_out_overflow = self.out_of
646
647 m.d.comb += self.mod.in_z.copy(in_z)
648 m.d.comb += self.mod.in_tot.eq(in_tot)
649
650 m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
651
652 if self.in_mid is not None:
653 m.d.comb += self.in_mid.eq(in_mid)
654
655 def action(self, m):
656 self.idsync(m)
657 m.d.sync += self.out_of.copy(self.mod.out_of)
658 m.d.sync += self.out_z.copy(self.mod.out_z)
659 m.d.sync += self.norm_stb.eq(1)
660 m.next = "normalise_1"
661
662
663 class FPNorm1ModSingle:
664
665 def __init__(self, width):
666 self.width = width
667 self.out_norm = Signal(reset_less=True)
668 self.in_z = FPNumBase(width, False)
669 self.in_of = Overflow()
670 self.out_z = FPNumBase(width, False)
671 self.out_of = Overflow()
672
673 def setup(self, m, in_z, in_of, out_z):
674 """ links module to inputs and outputs
675 """
676 m.submodules.normalise_1 = self
677
678 m.d.comb += self.in_z.copy(in_z)
679 m.d.comb += self.in_of.copy(in_of)
680
681 m.d.comb += out_z.copy(self.out_z)
682
683 def elaborate(self, platform):
684 m = Module()
685
686 mwid = self.out_z.m_width+2
687 pe = PriorityEncoder(mwid)
688 m.submodules.norm_pe = pe
689
690 m.submodules.norm1_out_z = self.out_z
691 m.submodules.norm1_out_overflow = self.out_of
692 m.submodules.norm1_in_z = self.in_z
693 m.submodules.norm1_in_overflow = self.in_of
694
695 in_z = FPNumBase(self.width, False)
696 in_of = Overflow()
697 m.submodules.norm1_insel_z = in_z
698 m.submodules.norm1_insel_overflow = in_of
699
700 espec = (len(in_z.e), True)
701 ediff_n126 = Signal(espec, reset_less=True)
702 msr = MultiShiftRMerge(mwid, espec)
703 m.submodules.multishift_r = msr
704
705 m.d.comb += in_z.copy(self.in_z)
706 m.d.comb += in_of.copy(self.in_of)
707 # initialise out from in (overridden below)
708 m.d.comb += self.out_z.copy(in_z)
709 m.d.comb += self.out_of.copy(in_of)
710 # normalisation increase/decrease conditions
711 decrease = Signal(reset_less=True)
712 increase = Signal(reset_less=True)
713 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
714 m.d.comb += increase.eq(in_z.exp_lt_n126)
715 # decrease exponent
716 with m.If(decrease):
717 # *sigh* not entirely obvious: count leading zeros (clz)
718 # with a PriorityEncoder: to find from the MSB
719 # we reverse the order of the bits.
720 temp_m = Signal(mwid, reset_less=True)
721 temp_s = Signal(mwid+1, reset_less=True)
722 clz = Signal((len(in_z.e), True), reset_less=True)
723 # make sure that the amount to decrease by does NOT
724 # go below the minimum non-INF/NaN exponent
725 limclz = Mux(in_z.exp_sub_n126 > pe.o, pe.o,
726 in_z.exp_sub_n126)
727 m.d.comb += [
728 # cat round and guard bits back into the mantissa
729 temp_m.eq(Cat(in_of.round_bit, in_of.guard, in_z.m)),
730 pe.i.eq(temp_m[::-1]), # inverted
731 clz.eq(limclz), # count zeros from MSB down
732 temp_s.eq(temp_m << clz), # shift mantissa UP
733 self.out_z.e.eq(in_z.e - clz), # DECREASE exponent
734 self.out_z.m.eq(temp_s[2:]), # exclude bits 0&1
735 self.out_of.m0.eq(temp_s[2]), # copy of mantissa[0]
736 # overflow in bits 0..1: got shifted too (leave sticky)
737 self.out_of.guard.eq(temp_s[1]), # guard
738 self.out_of.round_bit.eq(temp_s[0]), # round
739 ]
740 # increase exponent
741 with m.Elif(increase):
742 temp_m = Signal(mwid+1, reset_less=True)
743 m.d.comb += [
744 temp_m.eq(Cat(in_of.sticky, in_of.round_bit, in_of.guard,
745 in_z.m)),
746 ediff_n126.eq(in_z.N126 - in_z.e),
747 # connect multi-shifter to inp/out mantissa (and ediff)
748 msr.inp.eq(temp_m),
749 msr.diff.eq(ediff_n126),
750 self.out_z.m.eq(msr.m[3:]),
751 self.out_of.m0.eq(temp_s[3]), # copy of mantissa[0]
752 # overflow in bits 0..1: got shifted too (leave sticky)
753 self.out_of.guard.eq(temp_s[2]), # guard
754 self.out_of.round_bit.eq(temp_s[1]), # round
755 self.out_of.sticky.eq(temp_s[0]), # sticky
756 self.out_z.e.eq(in_z.e + ediff_n126),
757 ]
758
759 return m
760
761
762 class FPNorm1ModMulti:
763
764 def __init__(self, width, single_cycle=True):
765 self.width = width
766 self.in_select = Signal(reset_less=True)
767 self.out_norm = Signal(reset_less=True)
768 self.in_z = FPNumBase(width, False)
769 self.in_of = Overflow()
770 self.temp_z = FPNumBase(width, False)
771 self.temp_of = Overflow()
772 self.out_z = FPNumBase(width, False)
773 self.out_of = Overflow()
774
775 def elaborate(self, platform):
776 m = Module()
777
778 m.submodules.norm1_out_z = self.out_z
779 m.submodules.norm1_out_overflow = self.out_of
780 m.submodules.norm1_temp_z = self.temp_z
781 m.submodules.norm1_temp_of = self.temp_of
782 m.submodules.norm1_in_z = self.in_z
783 m.submodules.norm1_in_overflow = self.in_of
784
785 in_z = FPNumBase(self.width, False)
786 in_of = Overflow()
787 m.submodules.norm1_insel_z = in_z
788 m.submodules.norm1_insel_overflow = in_of
789
790 # select which of temp or in z/of to use
791 with m.If(self.in_select):
792 m.d.comb += in_z.copy(self.in_z)
793 m.d.comb += in_of.copy(self.in_of)
794 with m.Else():
795 m.d.comb += in_z.copy(self.temp_z)
796 m.d.comb += in_of.copy(self.temp_of)
797 # initialise out from in (overridden below)
798 m.d.comb += self.out_z.copy(in_z)
799 m.d.comb += self.out_of.copy(in_of)
800 # normalisation increase/decrease conditions
801 decrease = Signal(reset_less=True)
802 increase = Signal(reset_less=True)
803 m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
804 m.d.comb += increase.eq(in_z.exp_lt_n126)
805 m.d.comb += self.out_norm.eq(decrease | increase) # loop-end
806 # decrease exponent
807 with m.If(decrease):
808 m.d.comb += [
809 self.out_z.e.eq(in_z.e - 1), # DECREASE exponent
810 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
811 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
812 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
813 self.out_of.round_bit.eq(0), # reset round bit
814 self.out_of.m0.eq(in_of.guard),
815 ]
816 # increase exponent
817 with m.Elif(increase):
818 m.d.comb += [
819 self.out_z.e.eq(in_z.e + 1), # INCREASE exponent
820 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
821 self.out_of.guard.eq(in_z.m[0]),
822 self.out_of.m0.eq(in_z.m[1]),
823 self.out_of.round_bit.eq(in_of.guard),
824 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
825 ]
826
827 return m
828
829
830 class FPNorm1Single(FPState, FPID):
831
832 def __init__(self, width, id_wid, single_cycle=True):
833 FPID.__init__(self, id_wid)
834 FPState.__init__(self, "normalise_1")
835 self.mod = FPNorm1ModSingle(width)
836 self.out_norm = Signal(reset_less=True)
837 self.out_z = FPNumBase(width)
838 self.out_roundz = Signal(reset_less=True)
839
840 def setup(self, m, in_z, in_of, in_mid):
841 """ links module to inputs and outputs
842 """
843 self.mod.setup(m, in_z, in_of, self.out_z)
844
845 if self.in_mid is not None:
846 m.d.comb += self.in_mid.eq(in_mid)
847
848 def action(self, m):
849 self.idsync(m)
850 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
851 m.next = "round"
852
853
854 class FPNorm1Multi(FPState, FPID):
855
856 def __init__(self, width, id_wid):
857 FPID.__init__(self, id_wid)
858 FPState.__init__(self, "normalise_1")
859 self.mod = FPNorm1ModMulti(width)
860 self.stb = Signal(reset_less=True)
861 self.ack = Signal(reset=0, reset_less=True)
862 self.out_norm = Signal(reset_less=True)
863 self.in_accept = Signal(reset_less=True)
864 self.temp_z = FPNumBase(width)
865 self.temp_of = Overflow()
866 self.out_z = FPNumBase(width)
867 self.out_roundz = Signal(reset_less=True)
868
869 def setup(self, m, in_z, in_of, norm_stb, in_mid):
870 """ links module to inputs and outputs
871 """
872 self.mod.setup(m, in_z, in_of, norm_stb,
873 self.in_accept, self.temp_z, self.temp_of,
874 self.out_z, self.out_norm)
875
876 m.d.comb += self.stb.eq(norm_stb)
877 m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
878
879 if self.in_mid is not None:
880 m.d.comb += self.in_mid.eq(in_mid)
881
882 def action(self, m):
883 self.idsync(m)
884 m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
885 m.d.sync += self.temp_of.copy(self.mod.out_of)
886 m.d.sync += self.temp_z.copy(self.out_z)
887 with m.If(self.out_norm):
888 with m.If(self.in_accept):
889 m.d.sync += [
890 self.ack.eq(1),
891 ]
892 with m.Else():
893 m.d.sync += self.ack.eq(0)
894 with m.Else():
895 # normalisation not required (or done).
896 m.next = "round"
897 m.d.sync += self.ack.eq(1)
898 m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
899
900
901 class FPNormToPack(FPState, FPID):
902
903 def __init__(self, width, id_wid):
904 FPID.__init__(self, id_wid)
905 FPState.__init__(self, "normalise_1")
906 self.width = width
907
908 def setup(self, m, in_z, in_of, in_mid):
909 """ links module to inputs and outputs
910 """
911
912 # Normalisation (chained to input in_z+in_of)
913 nmod = FPNorm1ModSingle(self.width)
914 n_out_z = FPNumBase(self.width)
915 n_out_roundz = Signal(reset_less=True)
916 nmod.setup(m, in_z, in_of, n_out_z)
917
918 # Rounding (chained to normalisation)
919 rmod = FPRoundMod(self.width)
920 r_out_z = FPNumBase(self.width)
921 rmod.setup(m, n_out_z, n_out_roundz)
922 m.d.comb += n_out_roundz.eq(nmod.out_of.roundz)
923 m.d.comb += r_out_z.copy(rmod.out_z)
924
925 # Corrections (chained to rounding)
926 cmod = FPCorrectionsMod(self.width)
927 c_out_z = FPNumBase(self.width)
928 cmod.setup(m, r_out_z)
929 m.d.comb += c_out_z.copy(cmod.out_z)
930
931 # Pack (chained to corrections)
932 self.pmod = FPPackMod(width)
933 self.out_z = FPNumBase(width)
934 self.pmod.setup(m, c_out_z)
935
936 # Multiplex ID
937 if self.in_mid is not None:
938 m.d.comb += self.in_mid.eq(in_mid)
939
940 def action(self, m):
941 self.idsync(m) # copies incoming ID to outgoing
942 m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) # outputs packed result
943 m.next = "pack_put_z"
944
945
946 class FPRoundMod:
947
948 def __init__(self, width):
949 self.in_roundz = Signal(reset_less=True)
950 self.in_z = FPNumBase(width, False)
951 self.out_z = FPNumBase(width, False)
952
953 def setup(self, m, in_z, roundz):
954 m.submodules.roundz = self
955
956 m.d.comb += self.in_z.copy(in_z)
957 m.d.comb += self.in_roundz.eq(roundz)
958
959 def elaborate(self, platform):
960 m = Module()
961 m.d.comb += self.out_z.copy(self.in_z)
962 with m.If(self.in_roundz):
963 m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
964 with m.If(self.in_z.m == self.in_z.m1s): # all 1s
965 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
966 return m
967
968
969 class FPRound(FPState, FPID):
970
971 def __init__(self, width, id_wid):
972 FPState.__init__(self, "round")
973 FPID.__init__(self, id_wid)
974 self.mod = FPRoundMod(width)
975 self.out_z = FPNumBase(width)
976
977 def setup(self, m, in_z, roundz, in_mid):
978 """ links module to inputs and outputs
979 """
980 self.mod.setup(m, in_z, roundz)
981
982 if self.in_mid is not None:
983 m.d.comb += self.in_mid.eq(in_mid)
984
985 def action(self, m):
986 self.idsync(m)
987 m.d.sync += self.out_z.copy(self.mod.out_z)
988 m.next = "corrections"
989
990
991 class FPCorrectionsMod:
992
993 def __init__(self, width):
994 self.in_z = FPNumOut(width, False)
995 self.out_z = FPNumOut(width, False)
996
997 def setup(self, m, in_z):
998 """ links module to inputs and outputs
999 """
1000 m.submodules.corrections = self
1001 m.d.comb += self.in_z.copy(in_z)
1002
1003 def elaborate(self, platform):
1004 m = Module()
1005 m.submodules.corr_in_z = self.in_z
1006 m.submodules.corr_out_z = self.out_z
1007 m.d.comb += self.out_z.copy(self.in_z)
1008 with m.If(self.in_z.is_denormalised):
1009 m.d.comb += self.out_z.e.eq(self.in_z.N127)
1010 return m
1011
1012
1013 class FPCorrections(FPState, FPID):
1014
1015 def __init__(self, width, id_wid):
1016 FPState.__init__(self, "corrections")
1017 FPID.__init__(self, id_wid)
1018 self.mod = FPCorrectionsMod(width)
1019 self.out_z = FPNumBase(width)
1020
1021 def setup(self, m, in_z, in_mid):
1022 """ links module to inputs and outputs
1023 """
1024 self.mod.setup(m, in_z)
1025 if self.in_mid is not None:
1026 m.d.comb += self.in_mid.eq(in_mid)
1027
1028 def action(self, m):
1029 self.idsync(m)
1030 m.d.sync += self.out_z.copy(self.mod.out_z)
1031 m.next = "pack"
1032
1033
1034 class FPPackMod:
1035
1036 def __init__(self, width):
1037 self.in_z = FPNumOut(width, False)
1038 self.out_z = FPNumOut(width, False)
1039
1040 def setup(self, m, in_z):
1041 """ links module to inputs and outputs
1042 """
1043 m.submodules.pack = self
1044 m.d.comb += self.in_z.copy(in_z)
1045
1046 def elaborate(self, platform):
1047 m = Module()
1048 m.submodules.pack_in_z = self.in_z
1049 with m.If(self.in_z.is_overflowed):
1050 m.d.comb += self.out_z.inf(self.in_z.s)
1051 with m.Else():
1052 m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
1053 return m
1054
1055
1056 class FPPack(FPState, FPID):
1057
1058 def __init__(self, width, id_wid):
1059 FPState.__init__(self, "pack")
1060 FPID.__init__(self, id_wid)
1061 self.mod = FPPackMod(width)
1062 self.out_z = FPNumOut(width, False)
1063
1064 def setup(self, m, in_z, in_mid):
1065 """ links module to inputs and outputs
1066 """
1067 self.mod.setup(m, in_z)
1068 if self.in_mid is not None:
1069 m.d.comb += self.in_mid.eq(in_mid)
1070
1071 def action(self, m):
1072 self.idsync(m)
1073 m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
1074 m.next = "pack_put_z"
1075
1076
1077 class FPPutZ(FPState):
1078
1079 def __init__(self, state, in_z, out_z, in_mid, out_mid):
1080 FPState.__init__(self, state)
1081 self.in_z = in_z
1082 self.out_z = out_z
1083 self.in_mid = in_mid
1084 self.out_mid = out_mid
1085
1086 def action(self, m):
1087 if self.in_mid is not None:
1088 m.d.sync += self.out_mid.eq(self.in_mid)
1089 m.d.sync += [
1090 self.out_z.v.eq(self.in_z.v)
1091 ]
1092 with m.If(self.out_z.stb & self.out_z.ack):
1093 m.d.sync += self.out_z.stb.eq(0)
1094 m.next = "get_ops"
1095 with m.Else():
1096 m.d.sync += self.out_z.stb.eq(1)
1097
1098
1099 class FPADDBaseMod(FPID):
1100
1101 def __init__(self, width, id_wid=None, single_cycle=False, compact=True):
1102 """ IEEE754 FP Add
1103
1104 * width: bit-width of IEEE754. supported: 16, 32, 64
1105 * id_wid: an identifier that is sync-connected to the input
1106 * single_cycle: True indicates each stage to complete in 1 clock
1107 * compact: True indicates a reduced number of stages
1108 """
1109 FPID.__init__(self, id_wid)
1110 self.width = width
1111 self.single_cycle = single_cycle
1112 self.compact = compact
1113
1114 self.in_t = Trigger()
1115 self.in_a = Signal(width)
1116 self.in_b = Signal(width)
1117 self.out_z = FPOp(width)
1118
1119 self.states = []
1120
1121 def add_state(self, state):
1122 self.states.append(state)
1123 return state
1124
1125 def get_fragment(self, platform=None):
1126 """ creates the HDL code-fragment for FPAdd
1127 """
1128 m = Module()
1129 m.submodules.out_z = self.out_z
1130 m.submodules.in_t = self.in_t
1131 if self.compact:
1132 self.get_compact_fragment(m, platform)
1133 else:
1134 self.get_longer_fragment(m, platform)
1135
1136 with m.FSM() as fsm:
1137
1138 for state in self.states:
1139 with m.State(state.state_from):
1140 state.action(m)
1141
1142 return m
1143
1144 def get_longer_fragment(self, m, platform=None):
1145
1146 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1147 self.in_a, self.in_b, self.width))
1148 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1149 a = get.out_op1
1150 b = get.out_op2
1151
1152 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1153 sc.setup(m, a, b, self.in_mid)
1154
1155 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1156 dn.setup(m, a, b, sc.in_mid)
1157
1158 if self.single_cycle:
1159 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1160 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1161 else:
1162 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1163 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1164
1165 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1166 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1167
1168 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1169 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1170
1171 if self.single_cycle:
1172 n1 = self.add_state(FPNorm1Single(self.width, self.id_wid))
1173 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1174 else:
1175 n1 = self.add_state(FPNorm1Multi(self.width, self.id_wid))
1176 n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb, add0.in_mid)
1177
1178 rn = self.add_state(FPRound(self.width, self.id_wid))
1179 rn.setup(m, n1.out_z, n1.out_roundz, n1.in_mid)
1180
1181 cor = self.add_state(FPCorrections(self.width, self.id_wid))
1182 cor.setup(m, rn.out_z, rn.in_mid)
1183
1184 pa = self.add_state(FPPack(self.width, self.id_wid))
1185 pa.setup(m, cor.out_z, rn.in_mid)
1186
1187 ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z,
1188 pa.in_mid, self.out_mid))
1189
1190 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1191 pa.in_mid, self.out_mid))
1192
1193 def get_compact_fragment(self, m, platform=None):
1194
1195 get = self.add_state(FPGet2Op("get_ops", "special_cases",
1196 self.in_a, self.in_b, self.width))
1197 get.setup(m, self.in_a, self.in_b, self.in_t.stb, self.in_t.ack)
1198 a = get.out_op1
1199 b = get.out_op2
1200
1201 sc = self.add_state(FPAddSpecialCases(self.width, self.id_wid))
1202 sc.setup(m, a, b, self.in_mid)
1203
1204 dn = self.add_state(FPAddDeNorm(self.width, self.id_wid))
1205 dn.setup(m, a, b, sc.in_mid)
1206
1207 if self.single_cycle:
1208 alm = self.add_state(FPAddAlignSingle(self.width, self.id_wid))
1209 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1210 else:
1211 alm = self.add_state(FPAddAlignMulti(self.width, self.id_wid))
1212 alm.setup(m, dn.out_a, dn.out_b, dn.in_mid)
1213
1214 add0 = self.add_state(FPAddStage0(self.width, self.id_wid))
1215 add0.setup(m, alm.out_a, alm.out_b, alm.in_mid)
1216
1217 add1 = self.add_state(FPAddStage1(self.width, self.id_wid))
1218 add1.setup(m, add0.out_tot, add0.out_z, add0.in_mid)
1219
1220 n1 = self.add_state(FPNormToPack(self.width, self.id_wid))
1221 n1.setup(m, add1.out_z, add1.out_of, add0.in_mid)
1222
1223 ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z,
1224 n1.in_mid, self.out_mid))
1225
1226 pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z,
1227 sc.in_mid, self.out_mid))
1228
1229
1230 class FPADDBase(FPState, FPID):
1231
1232 def __init__(self, width, id_wid=None, single_cycle=False):
1233 """ IEEE754 FP Add
1234
1235 * width: bit-width of IEEE754. supported: 16, 32, 64
1236 * id_wid: an identifier that is sync-connected to the input
1237 * single_cycle: True indicates each stage to complete in 1 clock
1238 """
1239 FPID.__init__(self, id_wid)
1240 FPState.__init__(self, "fpadd")
1241 self.width = width
1242 self.single_cycle = single_cycle
1243 self.mod = FPADDBaseMod(width, id_wid, single_cycle)
1244
1245 self.in_t = Trigger()
1246 self.in_a = Signal(width)
1247 self.in_b = Signal(width)
1248 #self.out_z = FPOp(width)
1249
1250 self.z_done = Signal(reset_less=True) # connects to out_z Strobe
1251 self.in_accept = Signal(reset_less=True)
1252 self.add_stb = Signal(reset_less=True)
1253 self.add_ack = Signal(reset=0, reset_less=True)
1254
1255 def setup(self, m, a, b, add_stb, in_mid, out_z, out_mid):
1256 self.out_z = out_z
1257 self.out_mid = out_mid
1258 m.d.comb += [self.in_a.eq(a),
1259 self.in_b.eq(b),
1260 self.mod.in_a.eq(self.in_a),
1261 self.mod.in_b.eq(self.in_b),
1262 self.in_mid.eq(in_mid),
1263 self.mod.in_mid.eq(self.in_mid),
1264 self.z_done.eq(self.mod.out_z.trigger),
1265 #self.add_stb.eq(add_stb),
1266 self.mod.in_t.stb.eq(self.in_t.stb),
1267 self.in_t.ack.eq(self.mod.in_t.ack),
1268 self.out_mid.eq(self.mod.out_mid),
1269 self.out_z.v.eq(self.mod.out_z.v),
1270 self.out_z.stb.eq(self.mod.out_z.stb),
1271 self.mod.out_z.ack.eq(self.out_z.ack),
1272 ]
1273
1274 m.d.sync += self.add_stb.eq(add_stb)
1275 m.d.sync += self.add_ack.eq(0) # sets to zero when not in active state
1276 #m.d.sync += self.in_t.stb.eq(0)
1277
1278 m.submodules.fpadd = self.mod
1279
1280 def action(self, m):
1281
1282 # in_accept is set on incoming strobe HIGH and ack LOW.
1283 m.d.comb += self.in_accept.eq((~self.add_ack) & (self.add_stb))
1284
1285 #with m.If(self.in_t.ack):
1286 # m.d.sync += self.in_t.stb.eq(0)
1287 with m.If(~self.z_done):
1288 # not done: test for accepting an incoming operand pair
1289 with m.If(self.in_accept):
1290 m.d.sync += [
1291 self.add_ack.eq(1), # acknowledge receipt...
1292 self.in_t.stb.eq(1), # initiate add
1293 ]
1294 with m.Else():
1295 m.d.sync += [self.add_ack.eq(0),
1296 self.in_t.stb.eq(0),
1297 ]
1298 with m.Else():
1299 # done: acknowledge, and write out id and value
1300 m.d.sync += [self.add_ack.eq(1),
1301 self.in_t.stb.eq(0)
1302 ]
1303 m.next = "get_a"
1304
1305 return
1306
1307 if self.in_mid is not None:
1308 m.d.sync += self.out_mid.eq(self.mod.out_mid)
1309
1310 m.d.sync += [
1311 self.out_z.v.eq(self.mod.out_z.v)
1312 ]
1313 # move to output state on detecting z ack
1314 with m.If(self.out_z.trigger):
1315 m.d.sync += self.out_z.stb.eq(0)
1316 m.next = "put_z"
1317 with m.Else():
1318 m.d.sync += self.out_z.stb.eq(1)
1319
1320
1321 class FPADD(FPID):
1322 """ FPADD: stages as follows:
1323
1324 FPGetOp (a)
1325 |
1326 FPGetOp (b)
1327 |
1328 FPAddBase---> FPAddBaseMod
1329 | |
1330 PutZ GetOps->Specials->Align->Add1/2->Norm->Round/Pack->PutZ
1331
1332 FPAddBase is tricky: it is both a stage and *has* stages.
1333 Connection to FPAddBaseMod therefore requires an in stb/ack
1334 and an out stb/ack. Just as with Add1-Norm1 interaction, FPGetOp
1335 needs to be the thing that raises the incoming stb.
1336 """
1337
1338 def __init__(self, width, id_wid=None, single_cycle=False):
1339 """ IEEE754 FP Add
1340
1341 * width: bit-width of IEEE754. supported: 16, 32, 64
1342 * id_wid: an identifier that is sync-connected to the input
1343 * single_cycle: True indicates each stage to complete in 1 clock
1344 """
1345 FPID.__init__(self, id_wid)
1346 self.width = width
1347 self.id_wid = id_wid
1348 self.single_cycle = single_cycle
1349
1350 self.in_a = FPOp(width)
1351 self.in_b = FPOp(width)
1352 self.out_z = FPOp(width)
1353
1354 self.states = []
1355
1356 def add_state(self, state):
1357 self.states.append(state)
1358 return state
1359
1360 def get_fragment(self, platform=None):
1361 """ creates the HDL code-fragment for FPAdd
1362 """
1363 m = Module()
1364 m.submodules.in_a = self.in_a
1365 m.submodules.in_b = self.in_b
1366 m.submodules.out_z = self.out_z
1367
1368 geta = self.add_state(FPGetOp("get_a", "get_b",
1369 self.in_a, self.width))
1370 geta.setup(m, self.in_a)
1371 a = geta.out_op
1372
1373 getb = self.add_state(FPGetOp("get_b", "fpadd",
1374 self.in_b, self.width))
1375 getb.setup(m, self.in_b)
1376 b = getb.out_op
1377
1378 ab = FPADDBase(self.width, self.id_wid, self.single_cycle)
1379 ab = self.add_state(ab)
1380 ab.setup(m, a, b, getb.out_decode, self.in_mid,
1381 self.out_z, self.out_mid)
1382
1383 #pz = self.add_state(FPPutZ("put_z", ab.out_z, self.out_z,
1384 # ab.out_mid, self.out_mid))
1385
1386 with m.FSM() as fsm:
1387
1388 for state in self.states:
1389 with m.State(state.state_from):
1390 state.action(m)
1391
1392 return m
1393
1394
1395 if __name__ == "__main__":
1396 if True:
1397 alu = FPADD(width=32, id_wid=5, single_cycle=True)
1398 main(alu, ports=alu.in_a.ports() + \
1399 alu.in_b.ports() + \
1400 alu.out_z.ports() + \
1401 [alu.in_mid, alu.out_mid])
1402 else:
1403 alu = FPADDBase(width=32, id_wid=5, single_cycle=True)
1404 main(alu, ports=[alu.in_a, alu.in_b] + \
1405 alu.in_t.ports() + \
1406 alu.out_z.ports() + \
1407 [alu.in_mid, alu.out_mid])
1408
1409
1410 # works... but don't use, just do "python fname.py convert -t v"
1411 #print (verilog.convert(alu, ports=[
1412 # ports=alu.in_a.ports() + \
1413 # alu.in_b.ports() + \
1414 # alu.out_z.ports())