src/add/nmigen_add_experiment.py

   1 # IEEE Floating Point Adder (Single Precision)
   2 # Copyright (C) Jonathan P Dawson 2013
   3 # 2013-12-12
   4
   5 from nmigen import Module, Signal, Cat
   6 from nmigen.cli import main, verilog
   7
   8 from fpbase import FPNumIn, FPNumOut, FPOp, Overflow, FPBase, FPNumBase
   9
  10
  11 class FPState(FPBase):
  12     def __init__(self, state_from):
  13         self.state_from = state_from
  14
  15     def set_inputs(self, inputs):
  16         self.inputs = inputs
  17         for k,v in inputs.items():
  18             setattr(self, k, v)
  19
  20     def set_outputs(self, outputs):
  21         self.outputs = outputs
  22         for k,v in outputs.items():
  23             setattr(self, k, v)
  24
  25
  26 class FPGetOpMod:
  27     def __init__(self, width):
  28         self.in_op = FPOp(width)
  29         self.out_op = FPNumIn(self.in_op, width)
  30         self.out_decode = Signal(reset_less=True)
  31
  32     def setup(self, m, in_op, out_op, out_decode):
  33         """ links module to inputs and outputs
  34         """
  35         m.d.comb += self.in_op.copy(in_op)
  36         m.d.comb += out_op.v.eq(self.out_op.v)
  37         m.d.comb += out_decode.eq(self.out_decode)
  38
  39     def elaborate(self, platform):
  40         m = Module()
  41         m.d.comb += self.out_decode.eq((self.in_op.ack) & (self.in_op.stb))
  42         #m.submodules.get_op_in = self.in_op
  43         m.submodules.get_op_out = self.out_op
  44         with m.If(self.out_decode):
  45             m.d.comb += [
  46                 self.out_op.decode(self.in_op.v),
  47             ]
  48         return m
  49
  50
  51 class FPGetOp(FPState):
  52     """ gets operand
  53     """
  54
  55     def __init__(self, in_state, out_state, in_op, width):
  56         FPState.__init__(self, in_state)
  57         self.out_state = out_state
  58         self.mod = FPGetOpMod(width)
  59         self.in_op = in_op
  60         self.out_op = FPNumIn(in_op, width)
  61         self.out_decode = Signal(reset_less=True)
  62
  63     def action(self, m):
  64         with m.If(self.out_decode):
  65             m.next = self.out_state
  66             m.d.sync += [
  67                 self.in_op.ack.eq(0),
  68                 self.out_op.copy(self.mod.out_op)
  69             ]
  70         with m.Else():
  71             m.d.sync += self.in_op.ack.eq(1)
  72
  73
  74 class FPGetOpB(FPState):
  75     """ gets operand b
  76     """
  77
  78     def __init__(self, in_b, width):
  79         FPState.__init__(self, "get_b")
  80         self.in_b = in_b
  81         self.b = FPNumIn(self.in_b, width)
  82
  83     def action(self, m):
  84         self.get_op(m, self.in_b, self.b, "special_cases")
  85
  86
  87 class FPAddSpecialCasesMod:
  88     """ special cases: NaNs, infs, zeros, denormalised
  89         NOTE: some of these are unique to add.  see "Special Operations"
  90         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
  91     """
  92
  93     def __init__(self, width):
  94         self.in_a = FPNumBase(width)
  95         self.in_b = FPNumBase(width)
  96         self.out_z = FPNumOut(width, False)
  97         self.out_do_z = Signal(reset_less=True)
  98
  99     def setup(self, m, in_a, in_b, out_z, out_do_z):
 100         """ links module to inputs and outputs
 101         """
 102         m.d.comb += self.in_a.copy(in_a)
 103         m.d.comb += self.in_b.copy(in_b)
 104         #m.d.comb += out_z.v.eq(self.out_z.v)
 105         m.d.comb += out_do_z.eq(self.out_do_z)
 106
 107     def elaborate(self, platform):
 108         m = Module()
 109
 110         m.submodules.sc_in_a = self.in_a
 111         m.submodules.sc_in_b = self.in_b
 112         m.submodules.sc_out_z = self.out_z
 113
 114         s_nomatch = Signal()
 115         m.d.comb += s_nomatch.eq(self.in_a.s != self.in_b.s)
 116
 117         m_match = Signal()
 118         m.d.comb += m_match.eq(self.in_a.m == self.in_b.m)
 119
 120         # if a is NaN or b is NaN return NaN
 121         with m.If(self.in_a.is_nan | self.in_b.is_nan):
 122             m.d.comb += self.out_do_z.eq(1)
 123             m.d.comb += self.out_z.nan(0)
 124
 125         # XXX WEIRDNESS for FP16 non-canonical NaN handling
 126         # under review
 127
 128         ## if a is zero and b is NaN return -b
 129         #with m.If(a.is_zero & (a.s==0) & b.is_nan):
 130         #    m.d.comb += self.out_do_z.eq(1)
 131         #    m.d.comb += z.create(b.s, b.e, Cat(b.m[3:-2], ~b.m[0]))
 132
 133         ## if b is zero and a is NaN return -a
 134         #with m.Elif(b.is_zero & (b.s==0) & a.is_nan):
 135         #    m.d.comb += self.out_do_z.eq(1)
 136         #    m.d.comb += z.create(a.s, a.e, Cat(a.m[3:-2], ~a.m[0]))
 137
 138         ## if a is -zero and b is NaN return -b
 139         #with m.Elif(a.is_zero & (a.s==1) & b.is_nan):
 140         #    m.d.comb += self.out_do_z.eq(1)
 141         #    m.d.comb += z.create(a.s & b.s, b.e, Cat(b.m[3:-2], 1))
 142
 143         ## if b is -zero and a is NaN return -a
 144         #with m.Elif(b.is_zero & (b.s==1) & a.is_nan):
 145         #    m.d.comb += self.out_do_z.eq(1)
 146         #    m.d.comb += z.create(a.s & b.s, a.e, Cat(a.m[3:-2], 1))
 147
 148         # if a is inf return inf (or NaN)
 149         with m.Elif(self.in_a.is_inf):
 150             m.d.comb += self.out_do_z.eq(1)
 151             m.d.comb += self.out_z.inf(self.in_a.s)
 152             # if a is inf and signs don't match return NaN
 153             with m.If(self.in_b.exp_128 & s_nomatch):
 154                 m.d.comb += self.out_z.nan(0)
 155
 156         # if b is inf return inf
 157         with m.Elif(self.in_b.is_inf):
 158             m.d.comb += self.out_do_z.eq(1)
 159             m.d.comb += self.out_z.inf(self.in_b.s)
 160
 161         # if a is zero and b zero return signed-a/b
 162         with m.Elif(self.in_a.is_zero & self.in_b.is_zero):
 163             m.d.comb += self.out_do_z.eq(1)
 164             m.d.comb += self.out_z.create(self.in_a.s & self.in_b.s,
 165                                           self.in_b.e,
 166                                           self.in_b.m[3:-1])
 167
 168         # if a is zero return b
 169         with m.Elif(self.in_a.is_zero):
 170             m.d.comb += self.out_do_z.eq(1)
 171             m.d.comb += self.out_z.create(self.in_b.s, self.in_b.e,
 172                                       self.in_b.m[3:-1])
 173
 174         # if b is zero return a
 175         with m.Elif(self.in_b.is_zero):
 176             m.d.comb += self.out_do_z.eq(1)
 177             m.d.comb += self.out_z.create(self.in_a.s, self.in_a.e,
 178                                       self.in_a.m[3:-1])
 179
 180         # if a equal to -b return zero (+ve zero)
 181         with m.Elif(s_nomatch & m_match & (self.in_a.e == self.in_b.e)):
 182             m.d.comb += self.out_do_z.eq(1)
 183             m.d.comb += self.out_z.zero(0)
 184
 185         # Denormalised Number checks
 186         with m.Else():
 187             m.d.comb += self.out_do_z.eq(0)
 188
 189         return m
 190
 191
 192 class FPAddSpecialCases(FPState):
 193     """ special cases: NaNs, infs, zeros, denormalised
 194         NOTE: some of these are unique to add.  see "Special Operations"
 195         https://steve.hollasch.net/cgindex/coding/ieeefloat.html
 196     """
 197
 198     def __init__(self, width):
 199         FPState.__init__(self, "special_cases")
 200         self.mod = FPAddSpecialCasesMod(width)
 201         self.out_z = FPNumOut(width, False)
 202         self.out_do_z = Signal(reset_less=True)
 203
 204     def action(self, m):
 205         with m.If(self.out_do_z):
 206             m.d.sync += self.out_z.v.eq(self.mod.out_z.v) # only take the output
 207             m.next = "put_z"
 208         with m.Else():
 209             m.next = "denormalise"
 210
 211
 212 class FPAddDeNormMod(FPState):
 213
 214     def __init__(self, width):
 215         self.in_a = FPNumBase(width)
 216         self.in_b = FPNumBase(width)
 217         self.out_a = FPNumBase(width)
 218         self.out_b = FPNumBase(width)
 219
 220     def setup(self, m, in_a, in_b, out_a, out_b):
 221         """ links module to inputs and outputs
 222         """
 223         m.d.comb += self.in_a.copy(in_a)
 224         m.d.comb += self.in_b.copy(in_b)
 225         m.d.comb += out_a.copy(self.out_a)
 226         m.d.comb += out_b.copy(self.out_b)
 227
 228     def elaborate(self, platform):
 229         m = Module()
 230         m.submodules.denorm_in_a = self.in_a
 231         m.submodules.denorm_in_b = self.in_b
 232         m.submodules.denorm_out_a = self.out_a
 233         m.submodules.denorm_out_b = self.out_b
 234         # hmmm, don't like repeating identical code
 235         m.d.comb += self.out_a.copy(self.in_a)
 236         with m.If(self.in_a.exp_n127):
 237             m.d.comb += self.out_a.e.eq(self.in_a.N126) # limit a exponent
 238         with m.Else():
 239             m.d.comb += self.out_a.m[-1].eq(1) # set top mantissa bit
 240
 241         m.d.comb += self.out_b.copy(self.in_b)
 242         with m.If(self.in_b.exp_n127):
 243             m.d.comb += self.out_b.e.eq(self.in_b.N126) # limit a exponent
 244         with m.Else():
 245             m.d.comb += self.out_b.m[-1].eq(1) # set top mantissa bit
 246
 247         return m
 248
 249
 250 class FPAddDeNorm(FPState):
 251
 252     def __init__(self, width):
 253         FPState.__init__(self, "denormalise")
 254         self.mod = FPAddDeNormMod(width)
 255         self.out_a = FPNumBase(width)
 256         self.out_b = FPNumBase(width)
 257
 258     def action(self, m):
 259         # Denormalised Number checks
 260         m.next = "align"
 261         m.d.sync += self.a.copy(self.out_a)
 262         m.d.sync += self.b.copy(self.out_b)
 263
 264
 265 class FPAddAlignMultiMod(FPState):
 266
 267     def __init__(self, width):
 268         self.in_a = FPNumBase(width)
 269         self.in_b = FPNumBase(width)
 270         self.out_a = FPNumIn(None, width)
 271         self.out_b = FPNumIn(None, width)
 272         self.exp_eq = Signal(reset_less=True)
 273
 274     def setup(self, m, in_a, in_b, out_a, out_b, exp_eq):
 275         """ links module to inputs and outputs
 276         """
 277         m.d.comb += self.in_a.copy(in_a)
 278         m.d.comb += self.in_b.copy(in_b)
 279         m.d.comb += out_a.copy(self.out_a)
 280         m.d.comb += out_b.copy(self.out_b)
 281         m.d.comb += exp_eq.eq(self.exp_eq)
 282
 283     def elaborate(self, platform):
 284         # This one however (single-cycle) will do the shift
 285         # in one go.
 286
 287         m = Module()
 288
 289         #m.submodules.align_in_a = self.in_a
 290         #m.submodules.align_in_b = self.in_b
 291         m.submodules.align_out_a = self.out_a
 292         m.submodules.align_out_b = self.out_b
 293
 294         # NOTE: this does *not* do single-cycle multi-shifting,
 295         #       it *STAYS* in the align state until exponents match
 296
 297         # exponent of a greater than b: shift b down
 298         m.d.comb += self.exp_eq.eq(0)
 299         m.d.comb += self.out_a.copy(self.in_a)
 300         m.d.comb += self.out_b.copy(self.in_b)
 301         agtb = Signal(reset_less=True)
 302         altb = Signal(reset_less=True)
 303         m.d.comb += agtb.eq(self.in_a.e > self.in_b.e)
 304         m.d.comb += altb.eq(self.in_a.e < self.in_b.e)
 305         with m.If(agtb):
 306             m.d.comb += self.out_b.shift_down(self.in_b)
 307         # exponent of b greater than a: shift a down
 308         with m.Elif(altb):
 309             m.d.comb += self.out_a.shift_down(self.in_a)
 310         # exponents equal: move to next stage.
 311         with m.Else():
 312             m.d.comb += self.exp_eq.eq(1)
 313         return m
 314
 315
 316 class FPAddAlignMulti(FPState):
 317
 318     def __init__(self, width):
 319         FPState.__init__(self, "align")
 320         self.mod = FPAddAlignMultiMod(width)
 321         self.out_a = FPNumIn(None, width)
 322         self.out_b = FPNumIn(None, width)
 323         self.exp_eq = Signal(reset_less=True)
 324
 325     def action(self, m):
 326         m.d.sync += self.a.copy(self.out_a)
 327         m.d.sync += self.b.copy(self.out_b)
 328         with m.If(self.exp_eq):
 329             m.next = "add_0"
 330
 331
 332 class FPAddAlignSingleMod:
 333
 334     def __init__(self, width):
 335         self.in_a = FPNumBase(width)
 336         self.in_b = FPNumBase(width)
 337         self.out_a = FPNumIn(None, width)
 338         self.out_b = FPNumIn(None, width)
 339         #self.out_a = FPNumBase(width)
 340         #self.out_b = FPNumBase(width)
 341
 342     def setup(self, m, in_a, in_b, out_a, out_b):
 343         """ links module to inputs and outputs
 344         """
 345         m.d.comb += self.in_a.copy(in_a)
 346         m.d.comb += self.in_b.copy(in_b)
 347         m.d.comb += out_a.copy(self.out_a)
 348         m.d.comb += out_b.copy(self.out_b)
 349
 350     def elaborate(self, platform):
 351         # This one however (single-cycle) will do the shift
 352         # in one go.
 353
 354         m = Module()
 355
 356         #m.submodules.align_in_a = self.in_a
 357         #m.submodules.align_in_b = self.in_b
 358         m.submodules.align_out_a = self.out_a
 359         m.submodules.align_out_b = self.out_b
 360
 361         # XXX TODO: the shifter used here is quite expensive
 362         # having only one would be better
 363
 364         ediff = Signal((len(self.in_a.e), True), reset_less=True)
 365         ediffr = Signal((len(self.in_a.e), True), reset_less=True)
 366         m.d.comb += ediff.eq(self.in_a.e - self.in_b.e)
 367         m.d.comb += ediffr.eq(self.in_b.e - self.in_a.e)
 368         m.d.comb += self.out_a.copy(self.in_a)
 369         m.d.comb += self.out_b.copy(self.in_b)
 370         with m.If(ediff > 0):
 371             m.d.comb += self.out_b.shift_down_multi(ediff)
 372         # exponent of b greater than a: shift a down
 373         with m.Elif(ediff < 0):
 374             m.d.comb += self.out_a.shift_down_multi(ediffr)
 375         return m
 376
 377
 378 class FPAddAlignSingle(FPState):
 379
 380     def __init__(self, width):
 381         FPState.__init__(self, "align")
 382         self.mod = FPAddAlignSingleMod(width)
 383         self.out_a = FPNumIn(None, width)
 384         self.out_b = FPNumIn(None, width)
 385
 386     def action(self, m):
 387         m.d.sync += self.a.copy(self.out_a)
 388         m.d.sync += self.b.copy(self.out_b)
 389         m.next = "add_0"
 390
 391
 392 class FPAddStage0Mod:
 393
 394     def __init__(self, width):
 395         self.in_a = FPNumBase(width)
 396         self.in_b = FPNumBase(width)
 397         self.in_z = FPNumBase(width, False)
 398         self.out_z = FPNumBase(width, False)
 399         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 400
 401     def elaborate(self, platform):
 402         m = Module()
 403         m.submodules.add0_in_a = self.in_a
 404         m.submodules.add0_in_b = self.in_b
 405         m.submodules.add0_out_z = self.out_z
 406
 407         m.d.comb += self.out_z.e.eq(self.in_a.e)
 408
 409         # store intermediate tests (and zero-extended mantissas)
 410         seq = Signal(reset_less=True)
 411         mge = Signal(reset_less=True)
 412         am0 = Signal(len(self.in_a.m)+1, reset_less=True)
 413         bm0 = Signal(len(self.in_b.m)+1, reset_less=True)
 414         m.d.comb += [seq.eq(self.in_a.s == self.in_b.s),
 415                      mge.eq(self.in_a.m >= self.in_b.m),
 416                      am0.eq(Cat(self.in_a.m, 0)),
 417                      bm0.eq(Cat(self.in_b.m, 0))
 418                     ]
 419         # same-sign (both negative or both positive) add mantissas
 420         with m.If(seq):
 421             m.d.comb += [
 422                 self.out_tot.eq(am0 + bm0),
 423                 self.out_z.s.eq(self.in_a.s)
 424             ]
 425         # a mantissa greater than b, use a
 426         with m.Elif(mge):
 427             m.d.comb += [
 428                 self.out_tot.eq(am0 - bm0),
 429                 self.out_z.s.eq(self.in_a.s)
 430             ]
 431         # b mantissa greater than a, use b
 432         with m.Else():
 433             m.d.comb += [
 434                 self.out_tot.eq(bm0 - am0),
 435                 self.out_z.s.eq(self.in_b.s)
 436         ]
 437         return m
 438
 439
 440 class FPAddStage0(FPState):
 441     """ First stage of add.  covers same-sign (add) and subtract
 442         special-casing when mantissas are greater or equal, to
 443         give greatest accuracy.
 444     """
 445
 446     def __init__(self, width):
 447         FPState.__init__(self, "add_0")
 448         self.mod = FPAddStage0Mod(width)
 449         self.out_z = FPNumBase(width, False)
 450         self.out_tot = Signal(self.out_z.m_width + 4, reset_less=True)
 451
 452     def setup(self, m, in_a, in_b):
 453         """ links module to inputs and outputs
 454         """
 455         m.submodules.add0 = self.mod
 456
 457         m.d.comb += self.mod.in_a.copy(in_a)
 458         m.d.comb += self.mod.in_b.copy(in_b)
 459
 460     def action(self, m):
 461         m.next = "add_1"
 462         # NOTE: these could be done as combinatorial (merge add0+add1)
 463         m.d.sync += self.out_z.copy(self.mod.out_z)
 464         m.d.sync += self.out_tot.eq(self.mod.out_tot)
 465
 466
 467 class FPAddStage1Mod(FPState):
 468     """ Second stage of add: preparation for normalisation.
 469         detects when tot sum is too big (tot[27] is kinda a carry bit)
 470     """
 471
 472     def __init__(self, width):
 473         self.out_norm = Signal(reset_less=True)
 474         self.in_z = FPNumBase(width, False)
 475         self.in_tot = Signal(self.in_z.m_width + 4, reset_less=True)
 476         self.out_z = FPNumBase(width, False)
 477         self.out_of = Overflow()
 478
 479     def elaborate(self, platform):
 480         m = Module()
 481         #m.submodules.norm1_in_overflow = self.in_of
 482         #m.submodules.norm1_out_overflow = self.out_of
 483         #m.submodules.norm1_in_z = self.in_z
 484         #m.submodules.norm1_out_z = self.out_z
 485         m.d.comb += self.out_z.copy(self.in_z)
 486         # tot[27] gets set when the sum overflows. shift result down
 487         with m.If(self.in_tot[-1]):
 488             m.d.comb += [
 489                 self.out_z.m.eq(self.in_tot[4:]),
 490                 self.out_of.m0.eq(self.in_tot[4]),
 491                 self.out_of.guard.eq(self.in_tot[3]),
 492                 self.out_of.round_bit.eq(self.in_tot[2]),
 493                 self.out_of.sticky.eq(self.in_tot[1] | self.in_tot[0]),
 494                 self.out_z.e.eq(self.in_z.e + 1)
 495         ]
 496         # tot[27] zero case
 497         with m.Else():
 498             m.d.comb += [
 499                 self.out_z.m.eq(self.in_tot[3:]),
 500                 self.out_of.m0.eq(self.in_tot[3]),
 501                 self.out_of.guard.eq(self.in_tot[2]),
 502                 self.out_of.round_bit.eq(self.in_tot[1]),
 503                 self.out_of.sticky.eq(self.in_tot[0])
 504         ]
 505         return m
 506
 507
 508 class FPAddStage1(FPState):
 509
 510     def __init__(self, width):
 511         FPState.__init__(self, "add_1")
 512         self.mod = FPAddStage1Mod(width)
 513         self.out_z = FPNumBase(width, False)
 514         self.out_of = Overflow()
 515         self.norm_stb = Signal()
 516
 517     def setup(self, m, in_tot, in_z):
 518         """ links module to inputs and outputs
 519         """
 520         m.submodules.add1 = self.mod
 521
 522         m.d.comb += self.mod.in_z.copy(in_z)
 523         m.d.comb += self.mod.in_tot.eq(in_tot)
 524
 525         m.d.sync += self.norm_stb.eq(0) # sets to zero when not in add1 state
 526
 527     def action(self, m):
 528         m.submodules.add1_out_overflow = self.out_of
 529         m.d.sync += self.out_of.copy(self.mod.out_of)
 530         m.d.sync += self.out_z.copy(self.mod.out_z)
 531         m.d.sync += self.norm_stb.eq(1)
 532         m.next = "normalise_1"
 533
 534
 535 class FPNorm1Mod:
 536
 537     def __init__(self, width):
 538         self.width = width
 539         self.in_select = Signal(reset_less=True)
 540         self.out_norm = Signal(reset_less=True)
 541         self.in_z = FPNumBase(width, False)
 542         self.in_of = Overflow()
 543         self.temp_z = FPNumBase(width, False)
 544         self.temp_of = Overflow()
 545         self.out_z = FPNumBase(width, False)
 546         self.out_of = Overflow()
 547
 548     def elaborate(self, platform):
 549         m = Module()
 550         m.submodules.norm1_out_z = self.out_z
 551         m.submodules.norm1_out_overflow = self.out_of
 552         m.submodules.norm1_temp_z = self.temp_z
 553         m.submodules.norm1_temp_of = self.temp_of
 554         m.submodules.norm1_in_z = self.in_z
 555         m.submodules.norm1_in_overflow = self.in_of
 556         in_z = FPNumBase(self.width, False)
 557         in_of = Overflow()
 558         m.submodules.norm1_insel_z = in_z
 559         m.submodules.norm1_insel_overflow = in_of
 560         # select which of temp or in z/of to use
 561         with m.If(self.in_select):
 562             m.d.comb += in_z.copy(self.in_z)
 563             m.d.comb += in_of.copy(self.in_of)
 564         with m.Else():
 565             m.d.comb += in_z.copy(self.temp_z)
 566             m.d.comb += in_of.copy(self.temp_of)
 567         # initialise out from in (overridden below)
 568         m.d.comb += self.out_z.copy(in_z)
 569         m.d.comb += self.out_of.copy(in_of)
 570         # normalisation increase/decrease conditions
 571         decrease = Signal(reset_less=True)
 572         increase = Signal(reset_less=True)
 573         m.d.comb += decrease.eq(in_z.m_msbzero & in_z.exp_gt_n126)
 574         m.d.comb += increase.eq(in_z.exp_lt_n126)
 575         m.d.comb += self.out_norm.eq(decrease | increase) # loop-end condition
 576         # decrease exponent
 577         with m.If(decrease):
 578             m.d.comb += [
 579                 self.out_z.e.eq(in_z.e - 1),  # DECREASE exponent
 580                 self.out_z.m.eq(in_z.m << 1), # shift mantissa UP
 581                 self.out_z.m[0].eq(in_of.guard), # steal guard (was tot[2])
 582                 self.out_of.guard.eq(in_of.round_bit), # round (was tot[1])
 583                 self.out_of.round_bit.eq(0),        # reset round bit
 584                 self.out_of.m0.eq(in_of.guard),
 585             ]
 586         # increase exponent
 587         with m.If(increase):
 588             m.d.comb += [
 589                 self.out_z.e.eq(in_z.e + 1),  # INCREASE exponent
 590                 self.out_z.m.eq(in_z.m >> 1), # shift mantissa DOWN
 591                 self.out_of.guard.eq(in_z.m[0]),
 592                 self.out_of.m0.eq(in_z.m[1]),
 593                 self.out_of.round_bit.eq(in_of.guard),
 594                 self.out_of.sticky.eq(in_of.sticky | in_of.round_bit)
 595             ]
 596
 597         return m
 598
 599
 600 class FPNorm1(FPState):
 601
 602     def __init__(self, width):
 603         FPState.__init__(self, "normalise_1")
 604         self.mod = FPNorm1Mod(width)
 605         self.stb = Signal(reset_less=True)
 606         self.ack = Signal(reset=0, reset_less=True)
 607         self.out_norm = Signal(reset_less=True)
 608         self.in_accept = Signal(reset_less=True)
 609         self.temp_z = FPNumBase(width)
 610         self.temp_of = Overflow()
 611         self.out_z = FPNumBase(width)
 612         self.out_roundz = Signal(reset_less=True)
 613
 614     def setup(self, m, in_z, in_of, norm_stb):
 615         """ links module to inputs and outputs
 616         """
 617         m.submodules.normalise_1 = self.mod
 618
 619         m.d.comb += self.mod.in_z.copy(in_z)
 620         m.d.comb += self.mod.in_of.copy(in_of)
 621
 622         m.d.comb += self.mod.in_select.eq(self.in_accept)
 623         m.d.comb += self.mod.temp_z.copy(self.temp_z)
 624         m.d.comb += self.mod.temp_of.copy(self.temp_of)
 625
 626         m.d.comb += self.out_z.copy(self.mod.out_z)
 627         m.d.comb += self.out_norm.eq(self.mod.out_norm)
 628
 629         m.d.comb += self.stb.eq(norm_stb)
 630         m.d.sync += self.ack.eq(0) # sets to zero when not in normalise_1 state
 631
 632     def action(self, m):
 633
 634         m.d.comb += self.in_accept.eq((~self.ack) & (self.stb))
 635         m.d.sync += self.temp_of.copy(self.mod.out_of)
 636         m.d.sync += self.temp_z.copy(self.out_z)
 637         with m.If(self.out_norm):
 638             with m.If(self.in_accept):
 639                 m.d.sync += [
 640                     self.ack.eq(1),
 641                 ]
 642             with m.Else():
 643                 m.d.sync += self.ack.eq(0)
 644         with m.Else():
 645             # normalisation not required (or done).
 646             m.next = "round"
 647             m.d.sync += self.ack.eq(1)
 648             m.d.sync += self.out_roundz.eq(self.mod.out_of.roundz)
 649
 650
 651 class FPRoundMod:
 652
 653     def __init__(self, width):
 654         self.in_roundz = Signal(reset_less=True)
 655         self.in_z = FPNumBase(width, False)
 656         self.out_z = FPNumBase(width, False)
 657
 658     def elaborate(self, platform):
 659         m = Module()
 660         m.d.comb += self.out_z.copy(self.in_z)
 661         with m.If(self.in_roundz):
 662             m.d.comb += self.out_z.m.eq(self.in_z.m + 1) # mantissa rounds up
 663             with m.If(self.in_z.m == self.in_z.m1s): # all 1s
 664                 m.d.comb += self.out_z.e.eq(self.in_z.e + 1) # exponent up
 665         return m
 666
 667
 668 class FPRound(FPState):
 669
 670     def __init__(self, width):
 671         FPState.__init__(self, "round")
 672         self.mod = FPRoundMod(width)
 673         self.out_z = FPNumBase(width)
 674
 675     def setup(self, m, in_z, roundz):
 676         """ links module to inputs and outputs
 677         """
 678         m.submodules.roundz = self.mod
 679
 680         m.d.comb += self.mod.in_z.copy(in_z)
 681         m.d.comb += self.mod.in_roundz.eq(roundz)
 682
 683     def action(self, m):
 684         m.d.sync += self.out_z.copy(self.mod.out_z)
 685         m.next = "corrections"
 686
 687
 688 class FPCorrectionsMod:
 689
 690     def __init__(self, width):
 691         self.in_z = FPNumOut(width, False)
 692         self.out_z = FPNumOut(width, False)
 693
 694     def elaborate(self, platform):
 695         m = Module()
 696         m.submodules.corr_in_z = self.in_z
 697         m.submodules.corr_out_z = self.out_z
 698         m.d.comb += self.out_z.copy(self.in_z)
 699         with m.If(self.in_z.is_denormalised):
 700             m.d.comb += self.out_z.e.eq(self.in_z.N127)
 701
 702         #        with m.If(self.in_z.is_overflowed):
 703         #            m.d.comb += self.out_z.inf(self.in_z.s)
 704         #        with m.Else():
 705         #            m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 706         return m
 707
 708
 709 class FPCorrections(FPState):
 710
 711     def __init__(self, width):
 712         FPState.__init__(self, "corrections")
 713         self.mod = FPCorrectionsMod(width)
 714         self.out_z = FPNumBase(width)
 715
 716     def setup(self, m, in_z):
 717         """ links module to inputs and outputs
 718         """
 719         m.submodules.corrections = self.mod
 720         m.d.comb += self.mod.in_z.copy(in_z)
 721
 722     def action(self, m):
 723         m.d.sync += self.out_z.copy(self.mod.out_z)
 724         m.next = "pack"
 725
 726
 727 class FPPackMod:
 728
 729     def __init__(self, width):
 730         self.in_z = FPNumOut(width, False)
 731         self.out_z = FPNumOut(width, False)
 732
 733     def elaborate(self, platform):
 734         m = Module()
 735         m.submodules.pack_in_z = self.in_z
 736         with m.If(self.in_z.is_overflowed):
 737             m.d.comb += self.out_z.inf(self.in_z.s)
 738         with m.Else():
 739             m.d.comb += self.out_z.create(self.in_z.s, self.in_z.e, self.in_z.m)
 740         return m
 741
 742
 743 class FPPack(FPState):
 744
 745     def __init__(self, width):
 746         FPState.__init__(self, "pack")
 747         self.mod = FPPackMod(width)
 748         self.out_z = FPNumOut(width, False)
 749
 750     def setup(self, m, in_z):
 751         """ links module to inputs and outputs
 752         """
 753         m.submodules.pack = self.mod
 754         m.d.comb += self.mod.in_z.copy(in_z)
 755
 756     def action(self, m):
 757         m.d.sync += self.out_z.v.eq(self.mod.out_z.v)
 758         m.next = "pack_put_z"
 759
 760
 761 class FPPutZ(FPState):
 762
 763     def action(self, m):
 764         self.put_z(m, self.z, self.out_z, "get_a")
 765
 766
 767 class FPADD:
 768
 769     def __init__(self, width, single_cycle=False):
 770         self.width = width
 771         self.single_cycle = single_cycle
 772
 773         self.in_a  = FPOp(width)
 774         self.in_b  = FPOp(width)
 775         self.out_z = FPOp(width)
 776
 777         self.states = []
 778
 779     def add_state(self, state):
 780         self.states.append(state)
 781         return state
 782
 783     def get_fragment(self, platform=None):
 784         """ creates the HDL code-fragment for FPAdd
 785         """
 786         m = Module()
 787
 788         geta = self.add_state(FPGetOp("get_a", "get_b",
 789                                       self.in_a, self.width))
 790         a = geta.out_op
 791         geta.mod.setup(m, self.in_a, geta.out_op, geta.out_decode)
 792         m.submodules.get_a = geta.mod
 793
 794         getb = self.add_state(FPGetOp("get_b", "special_cases",
 795                                       self.in_b, self.width))
 796         b = getb.out_op
 797         getb.mod.setup(m, self.in_b, getb.out_op, getb.out_decode)
 798         m.submodules.get_b = getb.mod
 799
 800         sc = self.add_state(FPAddSpecialCases(self.width))
 801         sc.mod.setup(m, a, b, sc.out_z, sc.out_do_z)
 802         m.submodules.specialcases = sc.mod
 803
 804         dn = self.add_state(FPAddDeNorm(self.width))
 805         dn.set_inputs({"a": a, "b": b})
 806         #dn.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 807         dn.mod.setup(m, a, b, dn.out_a, dn.out_b)
 808         m.submodules.denormalise = dn.mod
 809
 810         if self.single_cycle:
 811             alm = self.add_state(FPAddAlignSingle(self.width))
 812             alm.set_inputs({"a": a, "b": b})
 813             alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 814             alm.mod.setup(m, a, b, alm.out_a, alm.out_b)
 815         else:
 816             alm = self.add_state(FPAddAlignMulti(self.width))
 817             alm.set_inputs({"a": a, "b": b})
 818             #alm.set_outputs({"a": a, "b": b}) # XXX outputs same as inputs
 819             alm.mod.setup(m, a, b, alm.out_a, alm.out_b, alm.exp_eq)
 820         m.submodules.align = alm.mod
 821
 822         add0 = self.add_state(FPAddStage0(self.width))
 823         add0.setup(m, alm.out_a, alm.out_b)
 824
 825         add1 = self.add_state(FPAddStage1(self.width))
 826         add1.setup(m, add0.out_tot, add0.out_z)
 827
 828         n1 = self.add_state(FPNorm1(self.width))
 829         n1.setup(m, add1.out_z, add1.out_of, add1.norm_stb)
 830
 831         rn = self.add_state(FPRound(self.width))
 832         rn.setup(m, n1.out_z, n1.out_roundz)
 833
 834         cor = self.add_state(FPCorrections(self.width))
 835         cor.setup(m, rn.out_z)
 836
 837         pa = self.add_state(FPPack(self.width))
 838         pa.setup(m, cor.out_z)
 839
 840         ppz = self.add_state(FPPutZ("pack_put_z"))
 841         ppz.set_inputs({"z": pa.out_z})
 842         ppz.set_outputs({"out_z": self.out_z})
 843
 844         pz = self.add_state(FPPutZ("put_z"))
 845         pz.set_inputs({"z": sc.out_z})
 846         pz.set_outputs({"out_z": self.out_z})
 847
 848         with m.FSM() as fsm:
 849
 850             for state in self.states:
 851                 with m.State(state.state_from):
 852                     state.action(m)
 853
 854         return m
 855
 856
 857 if __name__ == "__main__":
 858     alu = FPADD(width=32)
 859     main(alu, ports=alu.in_a.ports() + alu.in_b.ports() + alu.out_z.ports())
 860
 861
 862     # works... but don't use, just do "python fname.py convert -t v"
 863     #print (verilog.convert(alu, ports=[
 864     #                        ports=alu.in_a.ports() + \
 865     #                              alu.in_b.ports() + \
 866     #                              alu.out_z.ports())